JPH07201862A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily remove an unrequired plating layer formed on a plating electrode at the time of forming a bump electrode in the pad of a silicon wafer by electrolytic plating. CONSTITUTION:A simple etching layer 25 made of aluminum is formed in a plating electrode formation region on a passivation film 22 formed on a silicon wafer 21 and a surface layer combined with a barrier layer is formed thereon. After a plating resist layer 29 is formed, the surface layer 28 combined with the barrier layer on the simple etching layer 25 is electrolytic-plated as a plating electrode and a bump electrode 32 is formed, and a plating layer 33 is formed on the plating layer composed of the surface layer 28 combined with the barrier layer on the simple etching layer 25. After that, a plating resist layer 29 is removed and then in order to remove the unrequired part of the surface layer 28 combined with the barrier layer, wet-etching is performed. At that time, the simple etching layer is lifted off and the plating electrode composed of the surface layer 28 combined with the barrier layer thereon and also the plating layer are removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Generally, semiconductor devices such as IC chips are
The pad formed on the silicon wafer is exposed through the opening formed in the passivation film formed on the silicon wafer (semiconductor device main body), and the bump electrode is formed on the exposed pad through the underlying metal layer. Is formed.

By the way, when manufacturing a semiconductor device having such a structure, as an example, first, as shown in FIG.
As shown in (B), the pad (not shown) formed on the silicon wafer 1 is exposed through the pad exposing opening 3 formed on the passivation film 2 formed on the silicon wafer 1. Prepare the items. Next, the underlying metal layer forming layer 5 is formed on the entire upper surface. Next, a plating resist layer 6 is formed on the entire upper surface of the underlying metal layer forming layer 5, exposed by using a glass mask, and then developed. An opening 7 on the pad side and an opening 8 for forming a plating electrode are formed in a portion corresponding to
As a result, the underlying metal layer forming layer 5 is exposed through the openings 7 and 8. Next, electrolytic plating is performed using the underlying metal layer forming layer 5 exposed through the opening 8 for forming the plating electrode as one of the plating electrodes to form the underlying metal layer exposed in the opening 7 on the pad side. A plating of gold or the like is deposited on the working layer 5, and the bump electrodes 9 are formed by this plating. In this case, the plating layer 10 having substantially the same height as the bump electrode 9 is also formed on the plating electrode formed of the base metal layer forming layer 5 exposed in the opening 8 for forming the plating electrode.
After that, the plating resist layer 6 is removed. Next, by wet etching, under the bump electrode 9 and the plating layer 1
Underlying metal layer forming layer 5 except for 0 is removed, thereby forming underlying metal layer 5a under bump electrode 9 as shown in FIGS. 6 (A) and 6 (B). In this case, the plated electrode made of the underlying metal layer forming layer 5 remains below the plated layer 10. Next, as shown in FIG. 6B, along the dicing street 11 indicated by the chain double-dashed line in FIG.
When the silicon wafer 1 is diced by the dicing blade 12, a plurality of semiconductor devices are formed.

[0004]

However, in the conventional method for manufacturing a semiconductor device as described above, the plating of the base metal layer forming layer 5 in the opening 8 for forming the plating electrode formed in the plating resist layer 6 is performed. Since the plating layer 10 is formed on the electrode and the plating layer 10 is strongly adhered to the plating electrode composed of the underlying metal layer forming layer 5 thereunder, the bump electrode 9 is not affected at all. It is extremely difficult to remove only the plating layer 10. On the other hand, since the plating electrodes are generally formed at predetermined three locations on the silicon wafer 1 that are equally spaced from each other, the plating layer 10 is also formed on the silicon wafer 1 at predetermined three locations around the periphery. It will be. Further, as shown in FIG. 6 (A), the plating layer 10 inevitably overlaps the dicing street 11. As a result, when the silicon wafer 1 is diced, the plating layer 10 and the underlying metal layer forming layer 5 remaining thereunder are also diced, so that the dicing blade 12 wears quickly, and the dicing blade 12 correspondingly. However, there is a problem that the dicing blade 12 may be damaged in an extreme case. An object of the present invention is to provide a method of manufacturing a semiconductor device that can easily remove an unnecessary plating layer formed on a plating electrode.

[0005]

According to the present invention, a pad formed on the semiconductor device body is exposed through a pad exposing opening formed on a passivation film formed on the semiconductor device body. After preparing an easy etching layer in the plating electrode formation region on the passivation film, a base metal layer forming layer is formed on the entire upper surface thereof, and the base metal layer forming layer on the easy etching layer is formed. Electroplating with one plating electrode as a plating electrode to form a bump electrode on the underlying metal layer forming layer on the pad, and a plating layer on the underlying metal layer forming layer on the easy-etching layer. And removing the base metal layer forming layer other than under the bump electrodes and under the plating layer by wet etching, and forming a base metal layer under the bump electrodes. And forming, in which so as to remove with plated electrodes and the plating layer made of the base metal layer forming layer thereon by a lift-off the easily etchable layer.

[0006]

According to the present invention, the easy-etching layer is formed on the passivation film on the plating electrode forming region, and when the base metal layer is formed under the bump electrode by wet etching, the easy-etching layer is lifted off on the base metal layer. Since the plating electrode and the plating layer made of the underlying metal layer forming layer are removed together, the unnecessary plating layer formed on the plating electrode can be easily removed.

[0007]

1 to 4 show respective steps of manufacturing a semiconductor device according to an embodiment of the present invention. Therefore, a method of manufacturing the semiconductor device of this embodiment will be described with reference to these drawings in order.

First, as shown in FIGS. 1 (A) and 1 (B),
The pad (not shown) formed on the silicon wafer 21 is exposed through the pad exposing opening 23 formed on the passivation film 22 formed on the silicon wafer (semiconductor device main body) 21. prepare. next,
An easy-etching layer 25 made of an amphoteric metal such as aluminum is formed on the passivation film 22 in the plating electrode forming region.
Is deposited on the entire upper surface by sputtering or vacuum deposition, and then patterned by using a technique such as photolithography. Next, an adhesive layer 26 for forming a lower layer of the underlying metal layer is formed on the upper surface of the passivation film 22 including the inside of the opening 23 for exposing the pad except the easy etching layer 25 by sputtering or vacuum. It is formed by depositing on the entire upper surface by a vapor deposition method or the like and then patterning by a method such as photolithography. In this case, a space 27 having a predetermined interval is formed between the easy etching layer 25 and the adhesive layer 26. Next, a barrier layer / surface layer 28 for forming an upper layer of the base metal layer is formed on the entire upper surface.

Next, as shown in FIGS. 2 (A) and 2 (B),
A plating resist layer 29 is formed on the upper surface of the barrier layer / surface layer 28, exposed by using a glass mask, and then developed. The opening 30 on the side and the opening 31 for forming the plating electrode are formed. In this case, the size of the opening 31 for forming the plating electrode is made smaller than the size of the easy etching layer 25. Next, an opening 31 for forming a plating electrode
When electrolytic plating is performed using the barrier layer / surface layer 28 exposed through the one side as one plating electrode, the opening 3 on the pad side is formed.
A plating of gold or the like is deposited on the barrier layer / surface layer 28 exposed at 0, and the bump electrode 32 is formed by this plating. In this case, the plating layer 33 having substantially the same height as the bump electrode 32 is also formed on the plating electrode formed of the barrier layer / surface layer 28 exposed in the opening 31 for forming the plating electrode. In this case, since the size of the opening 31 for forming the plating electrode is smaller than the size of the easy etching layer 25, the plating layer 33 is formed slightly smaller than the easy etching layer 25. After that, the plating resist layer 29 is removed.

Next, the bump electrode 32 and the plating layer 33.
Is used as an etching mask to wet-etch the barrier layer / surface layer 28 with an acidic etching solution. Then, since the plating layer 33 is formed to be slightly smaller than the easy etching layer 25, the easy etching layer 25 is exposed as the etching of the barrier layer / surface layer 28 proceeds. In this case, the adhesive layer 26 is also exposed. Then, as shown in FIGS. 3A and 3B, the adhesive layer 26 is not etched, but the easy-etching layer 25 made of an amphoteric metal such as aluminum is considerably faster than the etching rate of the barrier layer / surface layer 28. Etched at the etching rate. Then, the easily-etched layer 25 is removed by lift-off together with the plating electrode and the plating layer 33 formed of the barrier layer / surface layer 28 thereon. Next, when the adhesive layer 26 is dry-etched using the bump electrode 32 as an etching mask, as shown in FIGS. 4A and 4B, a barrier layer / surface layer that forms an upper underlying metal layer only under the bump electrode 32. 28 and the adhesive layer 26 forming the lower underlying metal layer remains.

In this way, when the easy-etching layer 25 is formed in the plating electrode forming region on the passivation film 22 and the barrier layer / surface layer 28 serving as the upper underlying metal layer is formed under the bump electrode 32 by wet etching. Since the easy-etching layer 25 is removed by lift-off together with the plating electrode and the plating layer 33 formed of the barrier layer / surface layer 28 thereon, the unnecessary plating layer 33 formed on the plating electrode can be easily removed. You can Therefore, the plating layer 33 and the like do not hinder the dicing, and there is no possibility of shortening the life of the dicing blade or damaging the dicing blade.

[0012]

As described above, according to the present invention, an easy etching layer is formed in the plating electrode forming region on the passivation film, and a base metal layer is easily formed under the bump electrode by wet etching. Since the etching layer is removed by lift-off together with the plating electrode and the plating layer formed on the underlying metal layer forming layer, the unnecessary plating layer formed on the plating electrode can be easily removed. Therefore, the plating layer or the like does not hinder the dicing, and there is no possibility of shortening the life of the dicing blade or damaging the dicing blade.

[Brief description of drawings]

FIG. 1A is a partial plan view showing a state in which an easy-etching layer, an adhesive layer, and a barrier layer / surface layer are formed in a manufacturing process of a semiconductor device according to an embodiment of the present invention; FIG. Sectional drawing which follows the BB line.

2A is a partial plan view showing a state in which a plating resist layer is formed and then electroplating is performed in the manufacturing process, and FIG. 2B is a cross-sectional view taken along the line BB.

FIG. 3A is a partial plan view showing a state where the plating resist layer is removed and then wet etching is performed in the same manufacturing process, and FIG. 3B is a sectional view taken along the line BB.

FIG. 4A is a partial plan view showing a state in which a barrier layer / surface layer and an adhesive layer are left only under the bump electrodes in the same manufacturing process, and FIG. 4B is a cross section taken along line BB thereof. Fig.

FIG. 5A is a partial plan view showing a state in which a plating resist layer is formed and post-electrolytic plating is performed in a conventional semiconductor device manufacturing process, and FIG. 5B is a sectional view taken along line BB thereof. .

6A is a partial plan view showing a dicing state in a conventional semiconductor device manufacturing process, and FIG.
-A sectional view taken along line B.

[Explanation of symbols]

 21 Silicon Wafer (Semiconductor Device Main Body) 22 Passivation Film 23, 24 Opening 25 Easy Etching Layer 26 Adhesive Layer 28 Barrier Layer / Surface Layer 29 Plating Resist Layer 32 Bump Electrode 33 Plating Layer

Claims (1)

[Claims] 1. A passivation film is provided in which a pad formed on the semiconductor device main body is exposed through an opening for pad exposure formed on a passivation film formed on the semiconductor device main body. After forming an easy etching layer in the upper plating electrode forming region, a base metal layer forming layer is formed on the entire upper surface thereof, and the base metal layer forming layer on the easy etching layer is used as one plating electrode for electrolytic plating. By forming a bump electrode on the underlying metal layer forming layer on the pad, forming a plating layer on the underlying metal layer forming layer on the easy-etching layer, by wet etching, Removing the underlying metal layer forming layer except under the bump electrode and under the plating layer,
A base metal layer is formed under the bump electrode, and the easily-etched layer is removed by lift-off together with the plating electrode formed of the base metal layer forming layer and the plating layer thereon. Manufacturing method of semiconductor device.