JPH071886B2 - Parallel data transmission processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data transmission processing circuit, and more particularly, a plurality of parallel data is serially transmitted through a single wired channel and then reproduced as parallel data to minimize the number of channels. The present invention relates to a parallel data transmission processing circuit that facilitates long-distance data transmission.

[0002]

2. Description of the Related Art A conventional serial transmission processing technique is a custom IC manufactured by Matsushita Co., Ltd., MN6124, which was used for digital serial data processing between a video camera and a remote controller. One channel has the advantage of being minimized, but it has the problem that only digital data can be processed, analog data cannot be processed, and peripheral circuits for performing other analog data processing become complicated. It was In addition, custom ICs such as M46015 and TP4508, which have been widely used recently, have an advantage of being able to process all digital data and analog data. On the other hand, it should have two channels for processing data signals and control signals respectively. Due to the problems, it was difficult to realize analog and digital data processing and single channel transmission required for data transmission processing.

[0003]

SUMMARY OF THE INVENTION The present invention is to solve such a problem, and an object of the present invention is to transmit a large number of parallel data in a single channel and to transmit all analog signals and digital signals. It is to provide a parallel data transmission processing circuit capable of processing.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is directed to a serial conversion section for converting parallel data, which is an analog and digital signal, into digital serial data and transmitting it to one channel, and a predetermined frequency. Control signal for controlling the serial conversion unit with the oscillation output pulse of the above, an oscillation and control unit for imparting synchronization to the transmitted serial data, and a parallel conversion unit for converting the serial data transmitted from the serial conversion unit into parallel data. And an oscillation and impulse generator for controlling the parallel converter by providing a reset signal for synchronizing the parallel converter to the serial converter in synchronization with the output from the oscillator and controller, and the output of the parallel converter. Sampling and holding the basic signal Is its features parallel data transmission processing circuit comprising a current sample-and-hold circuit.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the parallel data transmission processing circuit according to the present invention will be described in detail with reference to the accompanying drawings. Figure 1
Shows a block configuration of a parallel data transmission processing circuit according to the present invention, which comprises a multiplexer (hereinafter referred to as MUX) stage 11 and an analog / digital (hereinafter referred to as A / D) converter stage 12, and converts parallel data into serial data. The serial conversion unit 10 for outputting, the oscillation control stage 21, and the synchronization control stage 22 output a pulse having a predetermined frequency to control the serial conversion unit 10 and oscillate so as to impart synchronization to the output data of the serial conversion unit 10. And a parallel conversion unit that includes a control unit 20, a digital / analog (hereinafter referred to as D / A) converter stage 31, and a demultiplexer (hereinafter referred to as DMUX) 32 to convert the serial data transmitted from the serial conversion unit 10 into parallel data. 30 and reset circuit stage 41 An oscillation and impulse generation unit for controlling the parallel conversion unit 30 by providing a reset signal for synchronizing the parallel conversion unit 30 with the serial conversion unit 10 in synchronization with the oscillation and control unit 20 and comprising the control stage 42. 40 and a sample-and-hold circuit section 50 that samples and holds the parallel data output from the parallel conversion section 30 and reproduces the original signal.

2 and 3 show the detailed circuit of FIG. 1, FIG. 2 is a detailed circuit diagram of the serial conversion section 10 and the oscillation and control section 20, and FIG. 3 is the parallel conversion section 30.
FIG. 3 is a detailed circuit diagram of an oscillation and impulse generating section 40 and a sample hold circuit section 50. 2 and 3, first, the MUX stage 11 is composed of MUXIC1 and MUXIC2 each having 8 inputs and 1 output, and the data input stages A, B, C ... O.
Parallel data is input to the data input stages A, B, ...
The input signals of O are output with a time difference. The A / D converter stage 12 comprises an A / D converter IC3 for digitally converting each input signal selected and output by the MUXIC1 and a MUXIC4 for receiving and outputting the output of the A / D converter IC3 as serial data.
After the output data of the stage 11 is digitally converted, it is converted into serial data and output through a single channel.
The oscillation control stage 21 is 500K from the crystal oscillator X1.
When the pulse of Hz is supplied, this pulse is divided into 8 and output. The 4-bit hexadecimal counter IC5 and the control signal (f of the MUXIC4 of the A / D converter stage 12 are provided by the clock input of the output signal of the counter IC5.
b ₁ , fb ₂ , fb ₄ , fb ₈ : generically fb), and the control signal fb is 5 of the crystal oscillator X1.
Dual 4-bit hexadecimal counter IC6 that is generated by dividing a 00 KHz pulse by 9 and 500 KHz 1
Input the control signal fb4, which is 1 frequency division, to the MU
Control signals of the MUXIC1 and IC2 of the X stage 11 (fa ₁ , fa ₂ , fa ₄ , fa ₈ : generically fa)
And a counter IC 7 for generating
And the A / D converter stage 12 are controlled. The synchronous control stage 22 includes an 8-input NMOR gate G1, an inverter G2 and a transistor Q1, and controls signals (fa ₁ , fa ₂ , fa ₄ , fa ₈ ) and (f
When b ₁ , fb ₂ , fb ₄ , fb ₈ ) are all logic "0", a logic "1" output is generated (20V in one example) and a peak output is generated and output to the channel. The D / A converter stage 31 of the parallel conversion unit 30 includes a demultiplexer DMUXIC8 for converting a serially transmitted A / D conversion data into a parallel signal for D / A conversion, and data for directly outputting the parallel data signal of the DMUXIC8. The buffer IC 9 and the D / A converter IC 10 which D / A converts the 8-bit output of the data buffer IC 9 and outputs the serially converted data are converted into parallel data and converted into analog signals for output. .

The DMUX 32 is the MU of the serial conversion unit 10.
The data A, which is synchronized with the MUXIC1 and IC2 of the X stage 11,
It is composed of MUX IC11 and IC12 which output B, C ... O, and outputs the output of the D / A converter IC10 in parallel data. The reset circuit stage 41 uses the serial data input through the channel to synchronize the synchronous control stage 22.
The output of the inverter G4 whose level is lowered by connecting the output side of the inverter G3 which inverts the synchronized output pulse of the
The output side of the inverter G4 is again connected to one input of the AND gate G8 through the series circuit of G6 and G7.
In addition to the ND gate G8, the AND gate G is connected to the input.
An impulse is generated from the output of 8.

The oscillation control stage 42 is composed of counters IC13, IC14PIC15 which are reset by the impulse output of the reset circuit stage 41. The oscillation control stage 42 includes the oscillation and control unit 2.
A counter IC13 having the same configuration as the 0 oscillation control stage 21 and being supplied with a pulse of 500 KHz from the crystal oscillator X2 to generate an output divided by eight, and an output signal of the counter IC13 are provided by a clock input. D
A counter that generates a control signal (fb ' ₁ , fb' ₂ , fb ' _4, generically fb') of the DMUXIC 8 of the / A converter stage 31 and generates a pulse obtained by dividing the 500 KHz pulse of the crystal oscillator X2 by 9. IC14 and 50
The DMUX IC11, IC12 of the DMUX stage 32 is input with the control signal fb4, which is 0 KHz divided by 11, as an input.
Control signals (fa ′ ₁ , fa ′ ₂ , fa ′ ₄ f
a: counter IC1 to generate a) that the _'8 collectively fa'
5, D / A converter stage 31 and DMUX stage 3
Control 2

In the parallel data transmission processing circuit according to the present invention constructed as described above, analog signals including digital signals are input to the input stages A, B, ... O of the MUX stage 11 of the serial converter 10 as shown in FIG. Then, the input is sequentially output and output as serial data. Here, as an example, the analog signal is a signal that continuously changes from 0 to 5 V, and the digital signal is a signal that reciprocates between CV and 5 V. Is. MUXIC1 and IC2 are control signals (fa ₁ , f of the counter IC7 of the oscillation control stage 21).
a ₂ , fa ₄ ) will output the serial data including the analog signal. As shown in the waveform diagram of the control output signals of the counters IC6 and IC7 of the oscillation control stages 21 and 41 in FIG.
Control signals fb ₂ and Fb ′ ₂ having one cycle in two cycles of b ₁ and fb ′ ₁ , and the control signals fb ₂ and
Control signal fb having one cycle in two cycles of Fb ' _2.
4 , fb ' ₄ and the control signals fb ₄ , fb'
Control signals fa ₁ and f having one cycle in two cycles of ₄
a ′ ₁ , control signals fa ₂ and fa ′ ₂ having one cycle every two cycles, and the control signal fa
Control signal f having one cycle in the cycle of ₂ and fa ' _2.
a ₄ and fa ′ ₄ .

Input stages A, B, ... Of MUX IC1, IC2
The parallel input of O is sequentially output at the output stage and converted into serial data, and this signal is input to the A / D converter IC3 and is output to the eight output stages of the A / D converter IC3.
Output in bits, this 8-bit parallel data is MUX
The serial data is output from the IC4 and transmitted to the channel. At this time, each control signal (f
a ₁ , fa ₂ , fa ₄ , fa ₈ ), (fb ₁ , fb ₂ ,
fb ₄ , fb ₈ ) is the gate G of the synchronous control stage 22
When it is input to 1 and is all logic "0", its output becomes logic "1" and again passes through the inverter G2 to logic "0".
Then, the transistor Q1 is turned on and VCC20V is applied to the resistor R2 and the emitter connection portion. Here, the time during which the control signals fa and fb are all at logic "0" becomes very short, so a pulsed output is generated and transmitted through the channel together with serial data, and this pulse output is generated at a constant cycle. And is used as a sync signal.

This transmitted signal is input from the D / A converter stage 31, but the DM of the D / A converter stage 31 receives it.
Data buffer I converted by parallel data with UXIC8
Input to D / A converter IC10 through C9.
The D / A converter IC10 converts the input 8-bit parallel data into an analog signal and outputs it to the DMUX stage 32, and the DMUXIC11 and IC12 of the DMUX stage 32 process the analog-converted output data in parallel to perform sample-and-hold. It is output to the circuit unit 50. Before the operation of the parallel conversion unit 30, the oscillation and impulse generation unit 40 and the reset circuit stage 41 are input with a signal of 20V pitch from the NOR gate G3 as shown in the waveform diagram of FIG. The signal is ignored and only the level of 20 V is output as the input.

Therefore, the output pattern of the synchronization control unit 22 is
Only the loose signal becomes the input signal and is oscillated and output.
3, divided by R4 and input to inverter G4
It The output of this inverter G4 is level 5V.
Force pulse is generated and this pulse is generated by the NAND gate G
Delayed through the series circuit of 5, G6 and G7
To the output G8, and the output of the inverter G4 is ANDed again.
These two signals are applied to one input of gate G8
Matching level output pulses are generated. This pulse
Is a very narrow impulse. Generated like this
The generated impulse is the counter I of the oscillation control stage 42.
Reset C13, IC14, IC15 in the initial operating state
The data transmitted from the serial conversion unit 10 will be created.
Data, synchronous parallel converter 30, and oscillation control stage 42
Is driven. Here, as shown in the waveform diagram of FIG.
Control the time when the sync pulse that is the
Signal fb ₁, Fb₂, Fb_FourAnd control signal fa
₁, Fa₂, Fa_Four, Fa₈Is "0",
At this moment, the control signal fb '₁, Fb '₂, F
b ’ _Four, And the control signal fa ′₁, Fa '₂，
fa '_Fourfa '₈Becomes "0". Control signal
(Fa or fa ') and the control signal (fb or f
b ') becomes fb' at 8 times the frequency of fa '
And fa₂8 times the frequency of fb₂And fa_FourOf 8
Fb at double frequency_Fourbecome. That is, the frequency from fa to fb
The number is 8 times higher and the frequency is higher. Therefore, 8 bits of fa
As a value, fb has 8 bits for each bit.
Here, each water of the counter IC5 and the counter IC13
Crystal oscillators X1 and X2 have a phase of an output pulse of 500 KHz
When there is a 180 ° difference, the control signal fb₁And f
b ’₁The maximum phase difference is generated between the
Control signal fb₁I want about 1/512 times the cycle
It becomes very short and is generated by the crystal oscillators X1 and X2.
Error in the serial data transmission
The real conversion unit 10 and the oscillation and control unit 20 are
Transmission unit, parallel conversion unit 30, oscillation and impulse generation
Make sure that the pulse synchronization of the reception section consisting of the composition unit 40 matches.
become.

Therefore, when serial data is input by the DMuXIC 8 and input in parallel to the data buffer IC 9, it is approximately synchronized with the control signals fb ₁ , fb ₂ , fb ₄ . The data buffer IC9 has a waveform diagram as shown in FIG. 5, that is, each has a frequency division of 2. With the control signals fb ′ ₁ , fb ′ ₂ and fb ′ ₄ , the output control (CTL) signal becomes logic “0” at the time of logic “1” in the fourth cycle of the control fb ′ ₁ , and during this period, the data in the data buffer IC 9 is D An 8-bit parallel input is simultaneously input to the D / A converter IC 10 and output as an analog signal at the time of input to the / A converter IC 10. This output data is the DMUXI of the DMUX stage 32.
Input to C11, IC12, DMUXIC11, IC
12 are alternately driven to output analog signals in parallel, and the output of the DMUX stage 32 is input to the sample unhold circuit section 50 and reproduced by the original signal.
FIG. 7 shows an embodiment of the sample-and-hold circuit section 50, that is, an OP amplifier u1 which is a voltage follower and outputs of the OP amplifier u1 are connected to resistors R11 and R12.
It becomes an OP amplifier u2 which becomes a voltage follower by being divided by and becomes a 15-bit signal of the DMUX stage 32 and is reproduced by the original signal. In this way, the input of analog signal and digital signal is A / D converted, processed with serial data, transmitted, received, D / A converted, parallel converted and reproduced with the original signal, and its transmission channel also The control signal and the data signal are transmitted by one channel.

[0014]

As described above, according to the parallel data transmission processing circuit of the present invention, parallel data which is an analog and digital signal is converted into digital serial data,
A serial conversion unit that transmits on one channel, an oscillation and control unit that provides a control signal that controls the serial conversion unit with an oscillating force pulse of a predetermined frequency and synchronizes the serial data that is transmitted, and a channel that uses the serial conversion unit. A parallel conversion unit for converting serial data transmitted through the parallel conversion unit into parallel data, and a reset signal for synchronizing the parallel conversion unit with the serial conversion unit by the synchronization output from the oscillation and control unit. Since it consists of an oscillation and impulse generator that controls the unit and a sample and hold circuit that samples and holds the output of the parallel converter to reproduce the original signal, it processes the control signal and data on a single channel. , Digital analog signal Is improved its functionality greater adapted to process all the configuration of the overall system is very simplified peripheral circuits when custom IC of there is an effect to be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel data transmission processing circuit according to the present invention.

FIG. 2 is a circuit diagram of the transmission section of FIG.

FIG. 3 is a circuit diagram of a receiver in FIG.

FIG. 4 is an operation waveform diagram of each part of FIGS.

FIG. 5 is an operation waveform chart of each part of FIGS. 2 and 3;

FIG. 6 is an operation waveform diagram of each part of FIGS. 2 and 3;

7 is a detailed circuit diagram showing an embodiment of the sample-and-hold circuit unit in FIG.

[Explanation of symbols]

10 serial conversion unit 11 multiplexer (MUX) stage 12 analog / digital (A / D) converter end 20 oscillation and control unit 21 oscillation control stage 22 synchronization control stage 30 parallel conversion unit 31 digital / analog (D / A) converter stage 32 Dimplexer stage 40 Oscillation and impulse generation unit 41 Reset circuit stage 42 Oscillation control stage 50 Sample and hold circuit unit IC1, IC2, IC4 Multiplexer (MUX) IC3 Analog / Digital (A / D) converter IC5, IC6, IC7, IC14, IC15 Counter IC8, IC11, IC12 Demultiplexer (D
MUX) IC9 data buffer IC10 digital / analog (D / A) converter G1 NOR gate G2, G3, G4 inverter G5, G6, G7 NAND gate G8 AND gate Q1 transistor

Claims (5)

[Claims] 1. A serial converter for converting parallel data, which is an analog and digital signal, into digital serial data and transmitting it to one channel, and a control signal for controlling the serial converter with an oscillation output pulse of a predetermined frequency. An oscillation and control unit that imparts synchronization to serial data, a parallel conversion unit that converts serial data transmitted through a channel in the serial conversion unit into analog parallel data, and an output from the oscillation and control unit. An oscillation and impulse generator that provides a reset signal for synchronizing the parallel converter with the serial converter and controls the parallel converter, and the output of the parallel converter are sampled and held to reproduce the original signal. Sample and ho Parallel data transmission processing circuit including a field circuit unit. 2. The serial conversion unit comprises a multiplexer stage for converting parallel analog and digital data into serial data, and an analog / digital converter for digitally converting serial data output of the multiplexer stage. Parallel data transmission processing circuit. 3. An oscillation and control unit, an oscillation control stage for generating a control signal of a predetermined frequency for controlling the malplexer stage, and a synchronization control stage for generating a synchronization pulse by the control signal of the oscillation control stage. The parallel data transmission processing circuit according to claim 1. 4. The analog / parallel conversion unit
2. The parallel data according to claim 1, comprising a digital / analog converter stage for converting and outputting an output of serial data of the digital converter stage as an analog signal, and a demultiplexer stage for converting and outputting the output of the digital / analog converter stage as parallel data. Transmission processing circuit. 5. The oscillating and impulse generating section converts a synchronizing pulse of the synchronizing control stage into an impulse of a predetermined level to provide a reset signal, and a digital / analog stage by an output of the reset circuit stage. The parallel data transmission processing circuit according to claim 1, further comprising an oscillation control stage that resets the demultiplexer stage and generates a control signal of a predetermined frequency.