JPH03179922A - Decoder for digital signal - Google Patents

Abstract

PURPOSE:To improve the efficiency of error correction by providing a separation means to separate a digital signal to high order and low order bits and a signal synthesis means to synthesize separated signals, and performing the error correction setting the high-order bit except for the low-order bits as a target within a range where no effect is applied to vision. CONSTITUTION:The digital signal 12 with transmission speed fl in putted from a transmission line is varied to the digital signal of (l) bits with a separation circuit 11. Then, information is divided into high-order information 13 of high- order (m) bits and low-order information 16 of low-order (n) bits. The high-order information 13 out of them is inputted to an information separation circuit 14, and the low-order information 16 to a first buffer memory circuit 17, respectively. The error correction for information 19 to be error-corrected is performed at an error correction circuit 21 based on each information supplied from the information separation circuit 14, and a result is supplied to a second buffer memory circuit 22. Data is read out sequentially from the circuits 22 and 17 at a D/A conversion circuit 24, and an image signal 26 is reproduced with a frequency fs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device for correcting errors in a digital signal transmission path.

[Conventional technology]

When transmitting digital signals, bit errors may occur during the transmission process. This error causes deterioration in the image quality of, for example, a color image signal, so it is common practice for the transmitting device to add an error correction code to the image signal and transmit it. . Then, in the decoding device, errors in the image signal are corrected using this error correction code.

[Problem to be solved by the invention]

Error correction in such a decoding device has been performed on all l-bit image signals, for example, when the image signal is composed of l bits.

However, for example, when an image signal is converted to a 10-bit digital signal and transmitted, errors occurring in the lower 3 to 4 bits are outside the δ tolerance range of human visual characteristics when monitoring the screen. It is. That is, the least significant bit (L
From SB), the maximum error due to 4-bit resolution is 16 gradations, and compared to the 1024 gradations expressed by 10-bit resolution, the range of error is unrecognizable to human vision.

Therefore, a circuit for performing error correction on the lower several bits of the 1-bit image signal is needlessly added. Therefore, the circuit for error correction has become complicated. Furthermore, since the error correction code added to correct errors in the lower several bits of code is redundant, it has the disadvantage of limiting the amount of information that can be transmitted over the transmission path.

SUMMARY OF THE INVENTION An object of the present invention is to provide a decoding device that can efficiently correct errors in digital signals.

[Means to solve the problem]

The digital signal decoding device according to claim 1 comprises (]>
Separation means for separating a digital signal represented by l bits into upper m bits and lower n bits, and (11) error correction means for correcting errors in the upper m bits and soto signals separated by this separation means. and (iii) signal synthesis means for synthesizing the upper m-bit signal whose error has been corrected by the error correction means and the lower n-bit signal separated by the separation means to obtain an l-bit digital signal again. It is equipped with.

That is, the digital signal decoding apparatus of the present invention is configured to perform error correction on the upper bits excluding the lower several bits that do not affect the visual sense.

In the invention described in claim 2, error correction is performed for the upper bits and nodes of the image signal.

In the third aspect of the invention, error correction is performed using a BCH code.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows the configuration of a digital signal decoding apparatus in an embodiment of the present invention.

The digital signal decoding device shown in this figure is a separation circuit 1.
1. The separation circuit 11 converts the digital signal 12 received from the transmission path into an l-bit digital image signal. The separation circuit 11 separates the upper m-bit and soto upper information 13 from the l-bit digital image signal and supplies it to the information separation circuit 14, and also supplies the lower n-bit lower information 16 to the first buffer memory circuit 17. It is supposed to be done.

The information separation circuit 14 separates the higher-order information 13 supplied from the separation circuit 11 into a CH code 18 and error-corrected information 19 necessary for error correction added by a transmitting device (not shown), and performs error correction on these. Supplied to the circuit 21. The error correction circuit 21 corrects errors in the error-corrected information 19 based on the BCH code 18 and supplies the corrected information 19 to the second buffer memory circuit 22 . The error-corrected signal 23 of the upper m bits is error-corrected and supplied to the second buffer memory circuit 22.
is the lower order n supplied to the first buffer memory circuit 17
It is supplied to the digital-to-analog conversion circuit 24 while being synchronized with the bits.

The digital-to-analog conversion circuit 24 reproduces an analog image signal 26 from the 1-bit digital image signal consisting of the upper m bits and the lower n bits.

The digital signal decoding device includes a clock extraction circuit 27, a clock generation circuit 28, and a pulse generation circuit 29 that output clocks or pulses for synchronizing each circuit.
It is equipped with The clock extraction circuit 27 extracts the first clock 31 at the transmission speed M from the digital signal 12,
The signal is supplied to the separation circuit 11, the clock generation circuit 28, and the pulse generation circuit 29. The clock generation circuit 28 divides the first clock 31 and generates a second clock 33 having a frequency fs from the frequency information 32 separated by the separation circuit 11 to the pulse generation circuit 29 and the digital-to-analog conversion circuit 24.
supply to. Here, the frequency fs is the sampling frequency of an analog signal in a transmitting device (not shown).

In general, the frequency fj! , fs are asynchronous, the pulse generation circuit 29 monitors the frequencies fA and fs. Furthermore, the pulse generation circuit vi&29 generates control pulses for controlling the information separation circuit 14, the error correction circuit 21, the buffer memory circuit 27, and the buffer memory circuit 17, and performs all timing control.

Next, the operation of the digital signal decoding apparatus configured as described above will be explained.

Digital signal 1 with transmission speed fA input from the transmission line
2 is converted into an l-bit digital signal by the separation circuit 11. The conversion at this time is performed by the clock extraction circuit 27.
The transmission is performed at the same frequency as the transmission rate fl of the digital signal 12 based on the first clock supplied from the digital signal 12. The l-bit digital image signal converted by the separation circuit 11 is divided into upper information 13 of the upper m bits and lower information 16 of the lower n bits (m+n-j). , lower-order information 16 are input to the first buffer memory circuit 17, respectively.

The information separation circuit 14 converts the BHC code 18 and the error-corrected information 19 into the input upper m-bit upper information 13.
and outputs them to the error correction circuit 21. The error correction circuit 21 performs error correction on the error-corrected information 19 based on each piece of information supplied from the information separation circuit 14, and sends the result to the second buffer memory circuit 22.
supply to.

Next, in the digital-to-analog conversion circuit 24, the second buffer memory circuit 22 and the first buffer memory circuit 1
The data is read out sequentially from 7 and the image signal 26 is set to the frequency f.
Play with s.

In the embodiment described above, error correction is performed using a BCH code, but the invention according to claim 1 is not limited to this. For example, the transmitting side device adds a code such as a Hamming code, and thereby Error correction may also be performed.

〔Effect of the invention〕

As described above, according to the present invention, since error correction is performed only on the upper m bits of an l-bit image signal, it is possible to reduce the circuit configuration required for error correction to about 1/m. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a digital signal decoding device in an embodiment of the present invention. 11... Separation circuit, 12... Digital signal, 14... Information separation circuit, 17... First buffer memory circuit, 21...
...Error correction circuit, 22...Second buffer memory circuit, 24...
...Digital-to-analog conversion circuit.

Claims (1)

[Claims] 1. Separation means for separating a digital signal expressed in units of l bits into upper m bits and lower n bits, and error correction for errors in the signal of the upper m bits separated by this separation means. a correction means; and a signal synthesis means for synthesizing the upper m-bit signal whose error has been corrected by the error correction means and the lower n-bit signal separated by the separation means to obtain an l-bit digital signal again. A digital signal decoding device comprising: 2. The digital signal decoding device according to claim 1, wherein the l-bit digital signal is image information. 3. The digital signal decoding apparatus according to claim 1 or claim 2, wherein the error correction means performs error correction using a BCH code.