JPS63209237A - Data transmitter - Google Patents

Abstract

PURPOSE:To shorten converting time by converting a signal at every N bit, time base converting it as the signal of an L bit length, adding a bit synchronizing signal and a frame synchronizing signal and sending it while superposing the signal with the horizontal scanning period of a television video signal. CONSTITUTION:The output from a clock generating circuit 1 and the frame synchronizing signal (b) of a frame synchronizing generating circuit 2 are not processed and added to a synchronizing circuit 7 as the data as they are. The data from a sending data storing part 3 are divided into a signal at every 4-bit by a dividing circuit 4. From a memory for sending data, the data are outputted in parallel as b8-b1. At the dividing circuit 4, b8-b5 are divided as one block and b4-b1 are divided as a next block and they are outputted to a next correctable code adding part 5. By the time division, the output period is halved (transmitting speed is double.).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for transmitting error-correctable binary data using the horizontal scanning period of a television video signal. .

2. Description of the Related Art In a conventional data transmission device, an error correctable code is generated by software or the like, and the error correctable code is stored in a sending buffer memory.

Problems to be Solved by the Invention These conventional methods have the disadvantage that, for example, 8 bits are required to store 4 bits of data, and the processing speed is reduced due to the conversion time.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides an error-correctable code adding circuit, and in order to speed up processing, a time axis converter is installed and an error-correctable code is added. After converting the time axis of the data in accordance with the transmission timing, a clock for bit synchronization, a frame synchronization signal, etc. are added, and the data to be transmitted is generated.

Effect The present invention has the above-described configuration to reduce the memory for storage,
Furthermore, by adding an error-correctable code using a conversion circuit when sending out an error-correctable code, an efficient data sending device is provided.

Embodiment FIG. 1 is a block diagram showing an embodiment of a data transmission device of the present invention. In this embodiment, a case will be explained in which a correctable code is added to 4-bit data to make it 8-bit data.

In Figure 1, 1 is a clock generation circuit for bit-by-bit synchronization, 2 is a frame synchronization generation circuit for 8-bit synchronization, 3 is a storage section for sending data, and 4 is a circuit for converting 8-bit data into 4 bits. 5 is a correctable code addition unit that converts the sent data every 4 bits into data with an 8-bit correction code, and 6 is a parallel /
A time axis conversion circuit for serial conversion, 7 a synthesis circuit for synthesizing the signal converted into a serial signal after adding a clock signal, a frame synchronization signal, and a correctable code, 8 a switching timing signal generation circuit, and 9 a TV synchronization circuit. Synchronous signal generation circuit that generates signals and clocks for transmission, 10
11 represents a waveform shaping circuit, 11 represents a composite synchronizing signal, and 12 represents an output terminal.

FIG. 2 shows signals and timings of each part in order to explain the present invention in detail. In the same figure, (ia) is a pin
('b) is a frame synchronization signal for synchronization every 8 bits, (C) is an 8-bit long string output signal from the sending data storage section 3, (d) is a 4-bit synchronization signal. The signal is divided into bits, (el) is the signal converted to data with an 8-bit correction code, (f') is the parallel/serial converted signal, and (g) is the waveform-shaped signal. ing.

In FIG. 1, the output from the clock generation circuit 1 and the frame synchronization signal (b) from the frame synchronization generation circuit 2 are sent to the synthesis circuit 7 as data without being processed. The data from the sending data storage section 3 is divided into 4 parts by the dividing circuit 4.
Divide into bit-by-bit signals. As shown in FIG. 2(C), data are output in parallel from the send data memory as b8 to b1. For this reason, the WU circuit 4 divides b8 to b5 into one block and b4 to b1 as the next block, and outputs it to the next correctable code adding section 5. Due to this time division, the output period is halved (the transmission speed is doubled).

In the next correctable code adding section 5, b8 to b5 or b
The 4-bit data from 4 to b1 is converted to an 8-bit error-correctable code from d8 to d1, and the time axis conversion circuit 6 performs parallel/serial conversion at the same time as the time axis conversion.
1' to d8' are output at the same transmission speed as the clock etc. and sent to the synthesis circuit 7.

These three types of signals are switched by a signal from the timing switching signal generation circuit 8. The signal obtained in this way is
It is sent to a waveform shaping circuit 10 along with the composite synchronizing signal 11 to remove harmonic components and output from an output terminal 12. The synchronization signal generation circuit 9 generates a horizontal synchronization signal, a vertical synchronization signal, a composite synchronization signal, a clock for data transmission, etc. for the television.

In the above embodiment, the case of 8 bits has been described, but the same applies to other bit units.

Effects of the Invention As described above, according to the present invention, a signal to which an error correctable code is added can be efficiently generated with an extremely simple circuit configuration. It is possible to reduce the storage capacity of the data storage unit and at the same time shorten the conversion time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an input instruction device according to an embodiment of the present invention, and FIG. 2 is a diagram showing signals or timing of each part of the device. 1... Clock generation circuit, 2... Frame synchronization generation circuit, 3... Sending data storage section, 4.
... Division circuit, 6 ... Error correctable code addition section, 6 ... Time axis conversion circuit, 7 ...
...Synthesis circuit, 8..Switching timing signal generation circuit, 9..Synchronization signal generation circuit, 1o..Waveform shaping circuit, 11..Composite synchronization signal, 12..・・・
...Output terminal, (+L)...Clock signal, (
'b)... Frame synchronization signal, (C)...
...Data from the sending data storage section, ((1)...
...Data divided into every 4 bits, (6)...
・Data with an error correctable code added, (f)・
...Parallel/serial converted signal, (g)
・・・・・・Transmission data that has been waveform-shaped with a composite synchronization signal added.

Claims (1)

[Claims] means for generating bit synchronization, means for generating frame synchronization for synchronizing every M bits, means for dividing stored data of every M bits into blocks of every N bits, and a block of this N bit length. means for converting the data into a code including an error correctable code having a length of L bits;
It has means for temporarily storing bit length data in a buffer memory and converting the time axis, converting every N bits, converting the time axis as an L bit length signal, and adding a bit synchronization signal and a frame synchronization signal. , a data transmission device characterized in that the data transmission device transmits a television video signal superimposed on a horizontal scanning period.