JP2000269943A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device provided with a reception circuit, which is capable of suppressing the increase of manufacture cost, even at a high communication rate and meeting the requirement of a high communication rate. SOLUTION: This device is provided with an XOR 11, that generates a reception clock on the basis of serial data at a data rate F and a strobe signal, with a serial parallel converter 12 that includes a shift register 120DD that is operated synchronously with each UP edge of the received clock and a shift register 12EVEN, that is operated synchronously with each DOWN edge and converts serial data into N-bit parallel data, and with an FIFO register 13 that outputs the N-bit parallel data synchronously with a system clock of frequency F/N.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having a communication function, and more particularly to a semiconductor integrated circuit device using a DS link system as a data transmission system.

[0002]

2. Description of the Related Art Conventionally, DS (Data)
Strobe) There is a link method. The DS link method is a type of serial data transmission method, and is NRZ (Non-Return to Ze).
ro) The serial transmission data, which is a signal, and a strobe signal for receiving clock recovery are transmitted together. The strobe signal is a signal obtained by encoding the transmission data, and changes in a cycle in which the transmission data does not change.
In a changing cycle, it has a waveform that retains the previous state.
Such a DS link system is disclosed in, for example, US Pat.
No. 1,371 and the like.

FIG. 8A is a block diagram showing a conventional DS link type receiving circuit, and FIG. 8B is a signal showing the relationship between serial data (Data), a strobe signal (Strb), a reception clock and an internal clock. It is a waveform diagram.

As shown in FIGS. 8A and 8B, serial data Data Rx at a data rate of Fbps (bits per second) and a strobe signal Strb Rx are input to a receiving circuit. Strobe signal Strb Rx and serial data Dat
a Rx is an exclusive OR circuit (XOR) 111 in the receiving circuit.
Is input to The XOR 111 has a strobe signal StrbRx
By taking an exclusive OR of the data and the serial data Data Rx and detecting the match / mismatch alternately, the bit period (= F)
To generate a receiving clock that transitions. The reception clock and the serial data Data Rx are FIFO (First In First
Out) register 112. The FIFO register 112 synchronizes the serial data Data Rx with an internal clock and outputs internal clock synchronized data. The frequency of the internal clock is FHz. The internal clock synchronization data is input to the shift register 113. The shift register 113 is a serial-parallel (serial / parallel) conversion circuit including N-stage flip-flops that operate in synchronization with the rising edge of the internal clock. Shift register 1
Reference numeral 13 denotes a function of converting the input serial data into N for each F / NHz.
Output as bit parallel data DATA_RX.

FIG. 9 is a block diagram showing a conventional DS link type transmission circuit.

[0009] As shown in FIG. 9, an F / N
N-bit parallel data DATA TX updated every Hz is input. The parallel data DATA TX is input to the shift register 121 in the transmission circuit. Shift register 1
Reference numeral 21 includes an N-stage flip-flop that operates in synchronization with the rising edge of the internal clock, and outputs the input parallel data DATA TX as serial data one bit at a time for each FHz. The serial data is stored in the encoder 12
2 is input. The encoder 122 outputs serial transmission data Data Tx, encodes the serial data, and outputs a strobe signal St based on the DS link method.
Generate and output rb Tx.

[0007]

A conventional DS link receiving circuit and transmitting circuit require an internal clock having the same frequency FHz as the data rate. For this reason, when the communication speed increases, the internal clock also inevitably increases. If the internal clock becomes faster, for example, the setup time (rise time) of the flip-flop must be reduced. That is, a circuit such as a flip-flop that operates at a higher speed is required, and restrictions on circuit design become more severe. If the number of circuits operating at high speed increases and the restrictions on circuit design become severe, for example, the number of semiconductor integrated circuit devices that do not achieve desired characteristics increases, and there is a concern that manufacturing costs may increase.

Further, when a higher communication speed is required, it is expected that it will be difficult to realize a circuit that can follow the requested communication speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to suppress an increase in manufacturing cost even when a communication speed is increased, and to be able to follow a demand for a higher communication speed. It is an object of the present invention to provide a semiconductor integrated circuit device having a receiving circuit / transmitting circuit having a simple configuration.

[0010]

In order to achieve the above object, a semiconductor integrated circuit device according to a first aspect of the present invention comprises:
A reception clock generation circuit that generates a reception clock based on serial data at a data rate F and a strobe signal, a first shift register that operates in synchronization with one of an up edge and a down edge of the reception clock, and A serial-to-parallel converter for converting the serial data into N-bit parallel data, the system including at least a second shift register operating in synchronization with the other of the up edge and the down edge of the reception clock; and a system having a frequency of F / N A reception data output circuit that outputs the N-bit parallel data in synchronization with a clock.

According to the semiconductor integrated circuit device having the above configuration,
In particular, the first shift register operates in synchronization with one of the up edge and the down edge of the reception clock, and the second shift register operates in synchronization with the other of the up edge and the down edge of the reception clock.
At least. Therefore, the serial-parallel converter can be operated with the internal clock having the same frequency as the reception clock, that is, half the data rate. As described above, the serial-parallel converter can be operated with a clock having a frequency which is half the data rate. Therefore, even if the communication speed is increased, it is possible to suppress an increase in the manufacturing cost and to increase the communication speed. It becomes a configuration that can follow.

A semiconductor integrated circuit device according to a second aspect of the present invention includes a first shift register that operates in synchronization with one of an up edge and a down edge of an internal clock, and a first shift register that operates in synchronization with an up edge of the internal clock. A parallel-serial converter for converting N-bit parallel data into at least two first and second serial data, the parallel-serial converter including at least a second shift register operating in synchronization with the other of the down edges; A transmission data output circuit that selects first and second serial data according to a logical level and alternately outputs the first and second serial data, and generates a strobe signal based on the N-bit parallel data. A transmission circuit including a strobe signal generation circuit is provided.

According to the semiconductor integrated circuit device having the above configuration,
In particular, a first shift register which operates the parallel-serial converter in synchronization with one of the up edge and the down edge of the internal clock, and a second shift register which operates in synchronization with the other of the up and down edges of the internal clock
, And is configured to convert N-bit parallel data into at least two first and second serial data. In addition, there is provided a transmission data output circuit that selects the first and second serial data according to the logic level of the internal clock and outputs the first and second serial data alternately. Therefore, the data rate of the transmitted serial data can be twice the frequency of the internal clock. As described above, the data rate of the transmission serial data can be made twice as high as that of the internal clock. Therefore, even if the communication speed is increased, the increase in the manufacturing cost can be suppressed, and the demand for the increased communication speed can be followed. Becomes

Also in the semiconductor integrated circuit device provided with the receiving circuit and the transmitting circuit, it is possible to suppress an increase in manufacturing cost even if the communication speed is increased.
In addition, it is possible to follow a request for a higher communication speed.

Further, in the semiconductor integrated circuit device according to the second aspect, the strobe signal generating circuit is configured to output one of the even-numbered parallel data and the odd-numbered parallel data out of the N-bit parallel data. And a third shift register that operates in synchronization with one of an up edge and a down edge of the internal clock, and converts the inverted parallel data into inverted serial data. And a strobe signal output circuit for selecting the second serial data and the inverted serial data according to the logic level of the internal clock, and alternately outputting the second serial data and the inverted serial data. .

According to the semiconductor integrated circuit device having the above configuration,
Since the second serial data is used as the strobe signal, the circuit area of the transmission circuit can be reduced.

Further, in the semiconductor integrated circuit device according to the second aspect, the strobe signal generation circuit includes the first strobe signal generation circuit.
And an inverting circuit that outputs inverted serial data of the serial data of the second serial data and the inverted serial data according to the logic level of the internal clock, and alternates between the second serial data and the inverted serial data. And a strobe signal output circuit for outputting the signal.

According to the semiconductor integrated circuit device having the above configuration,
The strobe signal is transmitted to the second serial data and the first serial data.
Since the serial data is generated by using the inverted serial data, the circuit area of the strobe signal generation circuit can be reduced.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1A is a block diagram showing a DS link type receiving circuit according to a first embodiment of the present invention, and FIG. 1B is a block diagram showing serial data (Data).
FIG. 4 is a signal waveform diagram showing a relationship between a strobe signal (Strb), a reception clock, and a system clock.

As shown in FIGS. 1A and 1B, the receiving circuit 10 receives serial data Data Rx at a data rate of Fbps (bits per second) and a strobe signal Strb Rx. The strobe signal Strb Rx and the serial data Data Rx are supplied to an exclusive OR circuit (XOR) in the receiving circuit.
11 is input. XOR11 is a strobe signal Strb
Take the exclusive OR of Rx and serial data Data Rx,
By detecting match / mismatch alternately, the bit period (=
A receiving clock that transitions in F) is generated. The frequency of the reception clock is F / 2 Hz. The reception clock and the serial data Data Rx are transmitted to the serial-parallel converter 12.
Is input to The serial-parallel converter 12 includes a first shift register 12ODD that operates in synchronization with the rising edge of the reception clock, and a second shift register 12EVEN that operates in synchronization with the falling edge of the reception clock. The shift registers 12ODD and 12EVEN are respectively
This is a serial-parallel (serial / parallel) conversion circuit including an N / 2-stage flip-flop that operates in synchronization with the rising edge of an input clock (reception clock). FIG. 2 shows an example of the serial-parallel conversion circuit. Shift register 1
The 2ODD converts the serial data Data Rx into N / 2-bit odd-numbered parallel data, and shifts the shift register 12EVEN.
Converts the serial data Data Rx into N / 2-bit even-numbered parallel data. The parallel data of a total of N bits is input to the FIFO register 13. FIFO
The register 13 uses the reception clock of the frequency F / 2 as a write clock and the system clock of the frequency F / N as a read clock,
Outputs bit receive parallel data DATA RX.

According to the receiving circuit of the DS link system according to the first embodiment, the serial-parallel converter 12
, A first shift register 12ODD which operates in synchronization with the rising edge of the reception clock, and a second shift register 1 which operates in synchronization with the falling edge of the reception clock.
It consists of 2 EVEN. Therefore, the serial-parallel converter 12 can be operated with the reception clock having the frequency of F / 2 Hz. As described above, the serial-parallel converter 12 can be operated at a frequency F / 2 Hz which is half the data rate F. When the data rate F is the same as the conventional one, the setup time (rise time) of the flip-flop is Can be set longer than before. Also, restrictions on circuit design can be relaxed. Therefore, the production yield of the semiconductor integrated circuit device is improved, and an increase in the production cost can be suppressed.

The receiving circuit 10 according to the first embodiment
Operates at half the frequency of the data rate F,
It is possible to sufficiently comply with a request for a reduction in the data rate F, that is, a request for an increase in the communication speed.

Further, the receiving circuit 10 according to the first embodiment
Operates using a reception clock having a frequency of F / 2 Hz. Therefore, the receiving circuit 10 only needs to be supplied with the system clock of the frequency F / NHz as the operating clock. That is, there is no need to supply an internal clock having a frequency of F / 2 Hz. According to this configuration, the area of the oscillation circuit that oscillates the internal clock can be reduced, or the oscillation circuit can be omitted.
The advantage of being obtained with a smaller chip area can be obtained.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
It is a block diagram which shows the transmission circuit of the DS link system which concerns on embodiment.

As shown in FIG. 2, the transmitting circuit 20 includes N
Bit transmission parallel data DATA DX and an internal clock are input. The frequency of the internal clock is F / 2. The N-bit transmission parallel data DATA DX is input to the parallel-serial converter 21 and the strobe signal generator 22, respectively.

First, the parallel-serial converter 21 will be described. The parallel-serial converter 21 includes a first shift register 21ODD that operates in synchronization with the rising edge of the internal clock, and a second shift register 21EVEN that operates in synchronization with the falling edge of the internal clock.
Transmission parallel data DATA is stored in the shift register 21ODD.
Of the DX, odd-numbered parallel data is input. Transmission parallel data DATA DX is stored in the shift register 21EVEN.
Among them, the even-numbered parallel data is input. Each of the shift registers 21ODD and 21EVEN operates in synchronization with the rising edge of the input clock (internal clock).
This is a parallel-serial (parallel-serial) conversion circuit including a / 2 stage flip-flop. FIG. 4 shows an example of the parallel-serial conversion circuit. The shift register 21ODD
The odd-numbered parallel data is converted to odd-numbered serial data. The shift register 21EVEN converts even-numbered parallel data into even-numbered serial data. The odd-numbered and even-numbered serial data are respectively supplied to the selector 23.
Is input to The selector 23 outputs “H” of the internal clock.
The odd-numbered serial data is selected during the period, and the even-numbered serial data is selected during the “L” period of the internal clock. As a result, the even-numbered serial data and the odd-numbered serial data are alternately selected, and the transmission serial data Data Tx at the data rate F is output.

Next, the strobe signal generator 22 will be described. The strobe signal generator 22 includes an encoder 24 and a parallel-serial converter 25. The N-bit transmission parallel data DATA TX is input to the encoder 24. The encoder 24 encodes the N-bit transmission parallel data DATA TX and generates an N-bit parallel strobe signal STRB TX corresponding to the DS link system. FIG. 5 shows an example of a circuit of the encoder 24.

As shown in FIG. 5, the encoder 24 compares the logical levels of the transmission parallel data DATA TX before and after and the XNORs 26 ₀ to 26 for detecting a match / mismatch.
_N-1 and the transmission parallel data DAT
XOR 27 _{0 to} 27 _N-1 for detecting whether A TX has changed
It is composed of The outputs of the XORs 27 _{0 to} 27 _N−1 are _N- bit parallel strobe signals STRB TX (STRB TX [0] to STRB TX [N−1]) corresponding to the DS link system. The N-bit parallel strobe signal STRBTX is held by the flip-flops 28 and 29 for a period of F / NHz. The flip-flops 28 and 29 have a frequency of F / N
It operates in synchronization with the Hz system clock.

An N-bit parallel strobe signal STRB T
X is input to the parallel-serial converter 25. The parallel-serial converter 25 includes a first shift register 25OD which operates in synchronization with the rising edge of the internal clock.
D, and a second shift register 25EVEN that operates in synchronization with the down edge of the internal clock. The odd-numbered parallel strobe signal of the parallel strobe signal STRB TX is input to the shift register 25ODD, and the even-numbered parallel strobe signal is input to the shift register 25EVEN. Shift register 25ODD, 25EVEN
Are parallel / serial conversion circuits each including an N / 2-stage flip-flop that operates in synchronization with the rising edge of an input clock (internal clock).
And a parallel-serial conversion circuit as shown in FIG. The shift register 25ODD converts the odd-numbered parallel strobe signal into an odd-numbered serial strobe signal. The shift register 25EVEN converts the even-numbered parallel strobe signal into an even-numbered serial strobe signal. The odd-numbered and even-numbered serial strobe signals are respectively input to the selector 30. Selector 30
Selects an odd-numbered serial strobe signal during the "H" period of the internal clock, and selects and outputs an even-numbered serial strobe signal during the "L" period of the internal clock. As a result, the even-numbered serial strobe signal and the odd-numbered serial strobe signal are alternately selected, and the strobe signal StrbTx corresponding to the transmission serial data Data Tx is output.

According to the transmission circuit of the DS link system according to the second embodiment, the parallel-serial converter 21
Each of the shift registers 25 is composed of shift registers 21ODD and 25ODD operating in synchronization with the rising edge of the internal clock and shift registers 21EVEN and 21EVEN operating in synchronization with the falling edge of the internal clock. For this reason,
Each of the parallel-serial converters 21 and 25 can be operated with an internal clock having a frequency of F / 2 Hz.
Therefore, as in the first embodiment, when the data rate F is the same as that of the related art, the setup time (rise time) of the flip-flop can be set longer than that of the related art. Also, restrictions on circuit design can be relaxed. Therefore, the production yield of the semiconductor integrated circuit device is improved, and an increase in the production cost can be suppressed. Further, since the device operates at a frequency that is half the data rate F, it can sufficiently follow the demand for a higher communication speed.

[Third Embodiment] In the DS link system adopted in the IEEE1394 standard, initial values of serial data and a strobe signal are respectively set to "1, 0" or "0, 1" as an instruction to start transmission. Is defined by standards. In such standards,
The odd-numbered strobe signal matches the odd-numbered data,
It has been found that the even-numbered strobe signal matches the inverted value of the even-numbered data. Then, by utilizing this relationship, the circuit area of the strobe signal generator 22 was successfully reduced. Hereinafter, an example of the transmission circuit will be described as a third embodiment.

FIG. 6 is a block diagram showing a DS link transmission circuit according to a third embodiment of the present invention. In FIG. 6, portions common to FIG. 2 are denoted by common reference numerals.

As shown in FIG. 6, the third embodiment is different from the second embodiment in particular in the configuration of the strobe signal generator 22, so that the following description will focus on the strobe signal generator 22. explain.

The strobe signal generator 2 of the third embodiment
2, the odd-numbered serial data and the even-numbered parallel data of the N-bit parallel data DATA TX are input. The even-numbered parallel data is
1 is input. The inverter 31 inverts the even-numbered parallel data and outputs the even-numbered inverted parallel data. The even-numbered inverted parallel data is input to the shift register 32. Each shift register 32 is a parallel-serial conversion circuit including an N / 2-stage flip-flop that operates in synchronization with the rising edge of an input clock (internal clock). For example, the parallel-serial conversion circuit shown in FIG. It is composed of a circuit. The shift register 32 converts even-numbered inverted parallel data into even-numbered inverted serial data. The selector 33 receives the even-numbered inverted serial data and the odd-numbered serial data output from the shift register 21ODD. The selector 33 selects odd-numbered serial data in the “H” period of the internal clock,
The even-numbered inverted serial data is selected and output during the “L” period of the internal clock. As a result, even-numbered inverted serial data and odd-numbered serial data are alternately selected, and a strobe signal Strb Tx corresponding to transmission serial data Data Tx is output.

According to the transmission circuit of the DS link system according to the third embodiment, in addition to the same effects as those of the second embodiment, the strobe signal Strb using the odd-numbered serial data and the even-numbered inverted parallel data is used. By generating the TX, the shift register is set to 1 compared to the second embodiment.
And the circuit area of the transmission circuit 20 can be reduced.

The transmission is performed when the initial values of the serial data and the strobe signal are "1, 1" or "0," respectively.
When starting at 0 ", the odd-numbered strobe signal matches the odd-numbered data inversion value, and the even-numbered strobe signal matches the even-numbered data. Therefore, the initial value is" 1, 1 ". Or when the transmission is started in the state of “0, 0”, the strobe signal Strb T using the odd-numbered inverted parallel data and the even-numbered serial data;
Generate X.

[Fourth Embodiment] The fourth embodiment is another example of a transmission circuit in which the circuit area of the strobe signal generator 22 is reduced, as in the third embodiment.

FIG. 7 is a block diagram showing a DS link type transmitting circuit according to a fourth embodiment of the present invention. In FIG. 7, portions common to FIG. 2 are denoted by common reference numerals.

As shown in FIG. 7, the fourth embodiment is particularly different from the second embodiment in the configuration of the strobe signal generator 22. Therefore, the following description will focus on the strobe signal generator 22. explain.

The strobe signal generator 2 of the fourth embodiment
2, the odd-numbered serial data and the even-numbered serial data are input. The even-numbered serial data is input to the inverter 34. The inverter 34 inverts even-numbered serial data and outputs even-numbered inverted serial data. The selector 35 receives the even-numbered inverted serial data and the odd-numbered serial data. The selector 35 selects odd-numbered serial data during the “H” period of the internal clock, and selects and outputs even-numbered inverted serial data during the “L” period of the internal clock. As a result, even-numbered inverted serial data and odd-numbered serial data are alternately selected, and the strobe signal Str corresponding to the transmission serial data Data Tx is selected.
b Tx is output.

According to the transmission circuit of the DS link system according to the fourth embodiment, in addition to the same effects as in the second embodiment, the strobe signal Strb signal is generated by using the odd-numbered serial data and the even-numbered inverted serial data. By generating Tx, the number of shift registers is 2 compared to the second embodiment.
In addition, the number of shift registers can be reduced by one in comparison with the third embodiment. Therefore, the transmission circuit 2
0 circuit area can be reduced.

It should be noted that the third embodiment is advantageous over the fourth embodiment in that the parallel-serial converter 2
That is, there is no data delay between 1 and the selector 35. Therefore, the third embodiment is suitable for a case where the communication speed is very high as compared with the fourth embodiment.

The transmitting circuit 20 shown in FIG. 7 is assumed to start transmitting when the initial values of the serial data and the strobe signal are "1, 0" or "0, 1", respectively. Is the initial value “1, 1” or “0,
In the case of starting transmission at 0 ”, the strobe signal Strb TX may be generated using the odd-numbered inverted serial data and the even-numbered serial data.

Although the present invention has been described with reference to the first to fourth embodiments, the present invention is not limited to the first to fourth embodiments, and can be variously modified without departing from the spirit thereof.

For example, each of the receiving circuit 10 and the transmitting circuit 20 described in the above embodiment may be formed as a pair on one semiconductor integrated circuit device chip, or may be formed independently.

In the first to fourth embodiments, the shift register is divided into two for the even-numbered and the odd-numbered. However, the shift register can be divided into two or more. For example, when divided into four, it is possible to operate with a clock having a frequency of 1/4 of the data rate F, and when divided into eight, it is possible to operate with a frequency of 1/8 of the data rate F It is possible to operate with a clock.

[0048]

As described above, according to the present invention, even if the communication speed is increased, the increase in the manufacturing cost can be suppressed, and the receiving circuit having a configuration capable of following the demand for the increased communication speed is provided. / A semiconductor integrated circuit device having a transmission circuit can be provided.

[Brief description of the drawings]

FIG. 1A is a block diagram showing a DS link type receiving circuit according to a first embodiment of the present invention;
(B) is a signal waveform diagram showing a relationship among serial data, a strobe signal, a reception clock, and a system clock.

FIG. 2 is a circuit diagram showing an example of a circuit of a shift register (serial-parallel converter).

FIG. 3 is a block diagram showing a DS link transmission circuit according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram showing an example of a circuit of a shift register (parallel-serial converter).

FIG. 5 is a circuit diagram showing an example of a circuit of an encoder.

FIG. 6 is a block diagram showing a DS link type transmission circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a DS link transmission circuit according to a fourth embodiment of the present invention;

FIG. 8A is a block diagram showing a conventional DS link type receiving circuit, and FIG. 8B is a signal waveform diagram showing a relationship among serial data, a strobe signal, a reception clock, and an internal clock.

FIG. 9 is a block diagram showing a conventional DS link transmission circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Reception circuit, 11 ... Exclusive OR circuit (XOR), 12 ... Serial-parallel converter, 12ODD, 12EVEN ... Shift register, 13 ... FIFO register, 20 ... Transmission circuit, 21 ... Parallel-serial converter, 21ODD , 21EVEN ... shift register, 22 ... strobe signal generating circuit, 23 ... selectors, 24 ... encoder, 25 ... parallel - serial converter, 25ODD, 25EVEN ... shift register, 26 ₀ ~26 _N-1 ... inverted exclusive OR Circuit (XNO
R), 27 _{0 to} 27 _{N -1} Exclusive OR circuit (XOR), 28, 29 ... flip-flop, 30 ... selector, 31 ... inverter, 32 ... shift register, 33 ... selector, 34 ... inverter, 35 ... selector.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yoshiaki Takasaka 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Semiconductor System Technology Center (reference) 5K047 AA02 AA16 FF02 HH56 MM26 MM27 MM28

Claims (5)

[Claims] 1. A receiving clock generating circuit for generating a receiving clock based on serial data at a data rate F and a strobe signal, and a first clock operating in synchronization with one of an up edge and a down edge of the receiving clock. A serial-parallel converter for converting the serial data into N-bit parallel data, the serial-parallel converter including at least a shift register and a second shift register operating in synchronization with the other of the up edge and the down edge of the reception clock; A receiving data output circuit that outputs the N-bit parallel data in synchronization with an F / N system clock; 2. A first shift register that operates in synchronization with one of an up edge and a down edge of an internal clock, and a second shift register that operates in synchronization with the other of the up and down edges of the internal clock A parallel-serial converter for converting N-bit parallel data into at least two first and second serial data, and selecting the first and second serial data according to a logic level of the internal clock And a transmission circuit including a transmission data output circuit for alternately outputting the first and second serial data, and a strobe signal generation circuit for generating a strobe signal based on the N-bit parallel data. Semiconductor integrated circuit device. 3. The strobe signal generating circuit includes: an inverting circuit that outputs one of the even-numbered parallel data and the odd-numbered parallel data out of the N-bit parallel data; A third shift register operating in synchronization with one of the edge and the down edge;
A third parallel-serial converter for converting the inverted parallel data into inverted serial data, and selecting second serial data and inverted serial data according to a logic level of the internal clock; 3. The semiconductor integrated circuit device according to claim 2, further comprising a strobe signal output circuit that outputs inverted serial data alternately. 4. The strobe signal generating circuit outputs an inverted serial data of the first serial data, and selects a second serial data and the inverted serial data according to a logic level of the internal clock. 3. The semiconductor integrated circuit device according to claim 2, further comprising a strobe signal output circuit that alternately outputs the second serial data and the inverted serial data. 5. A receiving clock generating circuit for generating a receiving clock based on serial data at a data rate F and a strobe signal, and a first clock operating in synchronization with one of an up edge and a down edge of the receiving clock. A shift register and at least a second shift register operating in synchronization with the other of the up edge and the down edge of the reception clock.
A receiving circuit including a serial-parallel converter for converting the data into parallel data of bits, a reception data output circuit for outputting the N-bit parallel data in synchronization with a system clock having a frequency of F / N; And at least a first shift register operating in synchronization with one of a down edge and a second shift register operating in synchronization with the other of the up edge and the down edge of the internal clock. And a parallel-serial converter for converting the first and second serial data into at least two first and second serial data, and selecting the first and second serial data according to the logic level of the internal clock. A transmission data output circuit for alternately outputting data, and a switch based on the N-bit parallel data. And a transmission circuit including a strobe signal generation circuit for generating a trobe signal.