JPH07176535A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07176535A JPH07176535A JP5344075A JP34407593A JPH07176535A JP H07176535 A JPH07176535 A JP H07176535A JP 5344075 A JP5344075 A JP 5344075A JP 34407593 A JP34407593 A JP 34407593A JP H07176535 A JPH07176535 A JP H07176535A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- semiconductor device
- solder
- bump
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にフリツプチツプ実装などのバンプ方式ボンデ
イングの際に使用するバンプの形成方法に適用して好適
なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for application to a bump forming method used in bump type bonding such as flip chip mounting.
【０００２】[0002]
【従来の技術】従来、半導体の実装方法としては、バン
プ形成された回路基板上に直接バンプを介して半導体チ
ツプを実装する、いわゆるフリツプチツプ実装と呼ばれ
るものがある。2. Description of the Related Art Conventionally, as a semiconductor mounting method, there is a so-called flip chip mounting in which a semiconductor chip is directly mounted on a bump-formed circuit board via the bump.
【０００３】またバンプの材質は、はんだを使用するも
のや銅を柱として当該銅柱にはんだをめつきする方法
（特開昭56-32748号公報、特開昭61-279138 号公報、特
開平2-232928号公報）がある。Further, the material of the bump is a method using solder or a method in which copper is used as a pillar and the solder is set on the copper pillar (JP-A-56-32748, JP-A-61-279138, JP-A-61-279138). 2-232928).
【０００４】ここで図４〜図６はフリツプチツプボンデ
イング方式のための半導体装置へのバンプ形成製造工程
を示し、半導体のウエハ製造工程において用いる装置に
よつて図４（Ａ）に示すような半導体装置１のアルミニ
ウムパツド２上の自然酸化した酸化アルミニウム３を図
４（Ｂ）に示すようにアルゴンイオンによる逆スパツタ
等によつて除去し、次いで図４（Ｃ）に示すようにアル
ミニウムパツド２及びパツシベーシヨン膜４の上にウエ
ハ前面に亘つて、バリアメタルを兼ねたクロム又は銅等
の電界めつき用共通電極５をスパツタリングする。4 to 6 show a bump forming manufacturing process for a semiconductor device for the flip-chip bonding method. As shown in FIG. 4 (A), a device used in the semiconductor wafer manufacturing process is shown. The naturally oxidized aluminum oxide 3 on the aluminum pad 2 of the semiconductor device 1 is removed by reverse sputtering with argon ions as shown in FIG. 4B, and then the aluminum pad 3 is removed as shown in FIG. 4C. A common electrode 5 for electric field plating, which also functions as a barrier metal, such as chrome or copper, is sputtered on the cathode 2 and the passivation film 4 over the front surface of the wafer.
【０００５】この金属薄膜は後述する（図５（Ｂ）及び
（Ｃ））電界めつき工程において電流を供給する役割を
もつ。This metal thin film has a role of supplying an electric current in an electric field plating step which will be described later (FIGS. 5B and 5C).
【０００６】さらにその後、図５（Ａ）に示すように所
定のマスク（図示せず）を用いて写真法によつてめつき
レジスト６をパターンニングする。さらに図５（Ｂ）に
示すように銅の電界めつきにより銅バンプ７を形成し、
さらに銅パンプ７の上に図５（Ｃ）に示すように電界め
つき法によつてはんだバンプ８を形成する。その後も図
６（Ａ）に示すようにレジスト６を除去したり、図６
（Ｂ）に示すようにバリアメタル５をエツチングする等
の複雑な工程を必要とする。Thereafter, as shown in FIG. 5A, the plating resist 6 is patterned by a photographic method using a predetermined mask (not shown). Further, as shown in FIG. 5B, a copper bump 7 is formed by plating the electric field of copper,
Further, solder bumps 8 are formed on the copper bumps 7 by an electric field plating method as shown in FIG. After that, the resist 6 is removed as shown in FIG.
As shown in (B), a complicated process such as etching the barrier metal 5 is required.
【０００７】[0007]
【発明が解決しようとする課題】ところで従来の方法に
おいては、半導体のウエハ製造工程において使用するよ
うな複雑かつ大掛かりな装置を必要としており、簡単な
装置を用いてバンプを形成することが困難であつた。By the way, the conventional method requires a complicated and large-scale apparatus used in a semiconductor wafer manufacturing process, and it is difficult to form bumps using a simple apparatus. Atsuta
【０００８】また各半導体装置によつてチツプサイズ又
はパツド配置が異なることにより、半導体装置ごとに毎
回専用のマスクを作成する必要があり、この分バンプ形
成に要する期間が長期間化する問題があつた。Further, since the chip size or the pad arrangement is different depending on each semiconductor device, it is necessary to prepare a dedicated mask for each semiconductor device, which causes a problem that the period required for bump formation becomes longer. .
【０００９】さらに従来の方法においては、製造工程が
煩雑かつ長いことにより歩留りの低下を招く問題があつ
た。Further, in the conventional method, there is a problem that the production process is complicated and long and the yield is lowered.
【００１０】本発明は以上の点を考慮してなされたもの
で、マスク又は薄膜形成用の複雑かつ大掛かりな設備を
用いることなく簡単な装置によつて容易にバンプを形成
することができる半導体装置の製造方法を提案しようと
するものである。The present invention has been made in consideration of the above points, and a semiconductor device in which bumps can be easily formed by a simple device without using a complicated or large-scale equipment for forming a mask or a thin film. It is intended to propose a manufacturing method of.
【００１１】[0011]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、半導体装置１に対してバンプ２０
を形成する半導体装置の製造方法において、半導体装置
１上に銅ワイヤ１５によるボールボンデイングによつて
銅バンプ１７を形成し、銅バンプ表面に対して無電解は
んだめつきによつてはんだ１８を付着させ、銅バンプ１
７を中心に有するはんだバンプ２０を形成するようにす
る。In order to solve such a problem, according to the present invention, the bump 20 is provided to the semiconductor device 1.
In the method of manufacturing a semiconductor device, the copper bump 17 is formed on the semiconductor device 1 by ball bonding with the copper wire 15, and the solder 18 is attached to the surface of the copper bump by electroless soldering. Let copper bump 1
The solder bump 20 having 7 as the center is formed.
【００１２】また本発明においては、半導体装置の製造
方法は、半導体装置１上のアルミニウムパツド２に銅ワ
イヤ１５を直接ボールボンデイングして銅バンプ１７を
形成するようにする。Further, in the present invention, in the method of manufacturing the semiconductor device, the copper wire 15 is directly ball-bonded to the aluminum pad 2 on the semiconductor device 1 to form the copper bump 17.
【００１３】また本発明においては、はんだ１８は、置
換法によるはんだめつき工程によつて付着するようにす
る。Further, in the present invention, the solder 18 is attached by a soldering process by a substitution method.
【００１４】また本発明においては、はんだバンプ２０
は配線パターンが形成された回路基板上へ実装する前に
少なくとも１回加熱溶融するようにする。Further, in the present invention, the solder bump 20
Is heated and melted at least once before being mounted on the circuit board on which the wiring pattern is formed.
【００１５】[0015]
【作用】各半導体装置１のパツド電極配置ごとに、ボン
デイング位置をプログラム入力することによつて任意に
設定し得るワイヤボンダを使用して、ボールボンデイン
グ方式によつてアルミニウム電極２上に直接バンプ２０
を形成しているため、各半導体装置１ごとにマスクを用
意する必要がなく、また無電解めつき法を採用している
ので、従来の電解めつきに必要であつた共通電極のため
の金属薄膜を形成する必要がない。Using the wire bonder, which can arbitrarily set the bonding position for each pad electrode arrangement of each semiconductor device 1 by program input, the bumps 20 are directly formed on the aluminum electrodes 2 by the ball bonding method.
Since it is formed, it is not necessary to prepare a mask for each semiconductor device 1, and since the electroless plating method is adopted, the metal for the common electrode, which was necessary for the conventional electrolytic plating, is formed. There is no need to form a thin film.
【００１６】また、銅ワイヤ１５のボールボンデイング
は半導体装置１のアルミニウムパツド２上に直接ボンデ
イングするので、金属薄膜を形成する必要が無く、従つ
てこれらの工程に必要な複雑かつ大掛かりな製造設備が
不要である。Further, since the ball bonding of the copper wire 15 is carried out directly on the aluminum pad 2 of the semiconductor device 1, there is no need to form a metal thin film, and accordingly, the complicated and large-scale manufacturing equipment required for these steps is required. Is unnecessary.
【００１７】またさらに、はんだめつきは置換法を採用
しているので微細なピツチのバンプ形成においても、隣
接するバンプ同志が短絡することが無い状態に保持され
る。Furthermore, since the soldering method uses the substitution method, even in the formation of fine pitch bumps, the adjacent bumps are kept in a state of not being short-circuited.
【００１８】さらに、はんだめつき後配線パターンが形
成された回路基板へ実装する前に、当該めつきによつて
形成されたはんだを少なくとも１回以上溶融させるの
で、はんだの中の錫と鉛の分布がバンプ全体に亘つて均
一となるため実装後の電気抵抗値を低く抑えることがで
きる。Further, after the soldering, the solder formed by the soldering is melted at least once before being mounted on the circuit board on which the wiring pattern is formed. Since the distribution is uniform over the entire bump, the electrical resistance value after mounting can be suppressed to be low.
【００１９】[0019]
【実施例】以下図面について、本発明の一実施例を詳述
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.
【００２０】図１において３０は全体としてワイヤボン
ダを示し、ワイヤボンダ本体３５は銅ワイヤ１５を保持
したキヤピラリ１６を制御部３７からの制御データに基
づいてＸ軸、Ｙ軸及びＺ軸方向に移動し得るようになさ
れている。In FIG. 1, reference numeral 30 denotes a wire bonder as a whole, and the wire bonder main body 35 can move the capillaries 16 holding the copper wires 15 in the X-axis, Y-axis and Z-axis directions based on control data from the controller 37. It is done like this.
【００２１】制御部３７は入力装置３８に入力された全
電極パツド（アルミニウムパツド２）のＸ、Ｙ及びＺ軸
座標データＤＡＴＡ１及び銅ワイヤ１５に対するスパー
ク条件としての圧力データ及び超音波条件データＤＡＴ
Ａ２等に基づいてキヤピラリ１６を移動制御し、加熱ブ
ロツク３３上の半導体装置１に形成された各アルミニウ
ムパツド２に対して銅ワイヤ１５をボールボンデイング
する。The control unit 37 controls the X-, Y-, and Z-axis coordinate data DATA1 of all electrode pads (aluminum pad 2) input to the input device 38 and pressure data and ultrasonic condition data DAT as spark conditions for the copper wire 15.
The capillaries 16 are controlled to move based on A2 or the like, and the copper wires 15 are ball-bonded to the aluminum pads 2 formed on the semiconductor device 1 on the heating block 33.
【００２２】ここで図４〜図６との対応部分に同一符号
を付して示す図２及び図３は本発明による半導体装置の
製造方法を示し、図２（Ａ）において１は半導体装置、
２はアルミニウムパツド、３はアルミニウムパツド上に
自然形成された酸化アルミニウム、４は表面保護用のパ
ツシベーシヨン膜である。2 and 3 in which parts corresponding to those in FIGS. 4 to 6 are designated by the same reference numerals, show a method of manufacturing a semiconductor device according to the present invention. In FIG. 2A, 1 is a semiconductor device,
Reference numeral 2 is an aluminum pad, 3 is aluminum oxide naturally formed on the aluminum pad, and 4 is a passivation film for surface protection.
【００２３】ここで本実施例の製造方法では、図２
（Ｂ）のようにワイヤボンダ（図示せず）を用いて30
〔μｍ〕径の銅ワイヤ１５を用い、80〔μｍ〕径の銅ボ
ール１５Ａとなるようワイヤボンダのスパーク条件を設
定し、アルミニウムパツド２に直接ボールボンデイング
する。このとき、銅ワイヤの直下のアルミニウムパツド
２上の酸化アルミニウム３は、ボンデイングと同時に除
去され、良好な電気的接続となつた状態に保持される。Here, in the manufacturing method of this embodiment, as shown in FIG.
As shown in (B), use a wire bonder (not shown)
The copper wire 15 having a diameter of [μm] is used, the spark condition of the wire bonder is set so that the copper ball 15A having a diameter of 80 μm is set, and the ball is directly bonded to the aluminum pad 2. At this time, the aluminum oxide 3 on the aluminum pad 2 immediately below the copper wire is removed at the same time as the bonding, so that a good electrical connection is maintained.
【００２４】次いで銅ワイヤ１５をワイヤボンダ３０の
クランプ（図示せず）にはさみ銅ワイヤ１５を引き上
げ、図２（Ｃ）に示すように銅ワイヤ１５をボール部分
１５Ａから引きちぎることで、銅バンプ１７が形成され
る。なお、これらボンデイングに係わる一連の動作は全
て一般のワイヤボンダ３０で制御し得る。Next, the copper wire 15 is sandwiched between clamps (not shown) of the wire bonder 30 and the copper wire 15 is pulled up, and the copper wire 15 is torn off from the ball portion 15A as shown in FIG. It is formed. A series of operations relating to these bondings can be controlled by the general wire bonder 30.
【００２５】また、この時アルミニウムパツド２の上面
の銅ボール部以外のアルミニウムパツド上に残つた酸化
アルミニウムの部分は、続くはんだめつき工程において
もめつきされないまま残り、さらに当該酸化アルミニウ
ムは、めつき等の薬品に対しても安定であることによ
り、続くはんだめつき工程において、半導体装置自身に
ダメージを与えない状態に保持される。At this time, the aluminum oxide portion remaining on the aluminum pad other than the copper ball portion on the upper surface of the aluminum pad 2 remains unfixed in the subsequent soldering process, and the aluminum oxide is Since it is stable against chemicals such as plating, the semiconductor device itself is kept in a state of not being damaged in the subsequent soldering process.
【００２６】続いて図３（Ａ）に示すように置換法によ
る無電解はんだめつきによつてはんだ１８を10〔μｍ〕
〜20〔μｍ〕の厚みで付着させる。この時、はんだめつ
きの方法は置換法を用いているので、銅バンプの体積が
減少した分だけはんだが付着する。従つて、バンプのピ
ツチが微細な場合でも通常の電解はんだめつきを使用し
た場合に発生するような、めつき成長によるバンプ間の
短絡という問題がない。Then, as shown in FIG. 3A, the solder 18 is applied to 10 [μm] by electroless soldering by the substitution method.
Adhere to a thickness of ~ 20 [μm]. At this time, since the replacement method is used as the soldering method, the solder adheres only to the extent that the volume of the copper bump is reduced. Therefore, even if the pitch of the bumps is minute, there is no problem of short circuit between the bumps due to the plating growth which occurs when the usual electrolytic soldering is used.
【００２７】一方、当該めつき直後の状態でのはんだ１
８は、鉛と錫の原子がそれぞれ凝縮し、まばらに点在し
た状態であるため、電気抵抗値が高い状態となつてい
る。従つてその後、フラツクス（図示せず）をはんだ１
８に塗布し、所定の加熱溶融工程によつてはんだ１８を
加熱溶融し、さらに所定のフラツクス洗浄工程において
フラツクスを洗浄することにより図３（Ｂ）に示すよう
に銅を柱とするはんだバンプ２０が完成する。On the other hand, the solder 1 immediately after the plating is applied.
In No. 8, since the lead and tin atoms are condensed and scattered, the electric resistance value is high. Therefore, after that, solder the flux (not shown) 1
8 is applied, the solder 18 is heated and melted by a predetermined heating and melting step, and the flux is cleaned by a predetermined flux cleaning step, so that the solder bumps 20 having copper as pillars are formed as shown in FIG. 3B. Is completed.
【００２８】なお当該はんだ溶融の工程において上記は
んだめつき直後の鉛と錫のそれぞれの原子が凝縮し、ま
ばらに点在した状態が変化し、バンプ全体に亘つて均一
な鉛と錫の分布となることにより電気抵抗値が下がり、
電気的接続において良好な状態に保持される。In the step of melting the solder, the lead and tin atoms immediately after the soldering are condensed, and the sparsely scattered state changes, resulting in a uniform lead and tin distribution over the entire bump. And the electric resistance value decreases,
The electrical connection is kept in good condition.
【００２９】以上の方法において、はんだバンプ２０を
形成する場合、当該はんだバンプ２０を形成するアルミ
ニウムパツド２の位置をワイヤボンダ３０に対してプロ
グラム入力するといつた簡単な方法によつて所望の位置
にはんだバンプ２０を形成することができる。In the above method, when the solder bump 20 is formed, the position of the aluminum pad 2 on which the solder bump 20 is formed is programmed into the wire bonder 30 to a desired position by a simple method. The solder bump 20 can be formed.
【００３０】従つてパツド位置が異なる各半導体装置ご
とに従来手法に用いられるマスクを用意する必要がな
く、一段と容易に所望の位置にはんだバンプ２０を形成
することができる。Accordingly, it is not necessary to prepare a mask used in the conventional method for each semiconductor device having a different pad position, and the solder bump 20 can be formed at a desired position more easily.
【００３１】また銅ワイヤ１５のボール部分１５Ａは半
導体装置１のアルミニウムパツド２上に直接ボンデイン
グされることにより、金属薄膜を形成する必要が無く、
これらの工程に必要な複雑かつ大掛かりな製造設備が不
要となる。また置換法によるはんだめつきを採用するこ
とにより、微細なピツチのバンプ形成においても、隣接
するバンプ同士が短絡することを回避し得る。Since the ball portion 15A of the copper wire 15 is directly bonded onto the aluminum pad 2 of the semiconductor device 1, there is no need to form a metal thin film.
The complicated and large-scale manufacturing equipment required for these processes is unnecessary. Further, by adopting soldering by the substitution method, it is possible to avoid short-circuiting between adjacent bumps even when forming fine pitch bumps.
【００３２】またはんだめつき後、配線パターンが形成
されたはんだ１８を少なくとも１回以上加熱溶融させる
ことにより、はんだ１８の中の錫と鉛の分布がはんだバ
ンプ２０の全体に亘つて均一となるため、実装後の電気
抵抗値を低く抑えることができる。After the bending, the solder 18 having the wiring pattern formed thereon is heated and melted at least once, so that the distribution of tin and lead in the solder 18 becomes uniform over the entire solder bump 20. Therefore, the electric resistance value after mounting can be suppressed low.
【００３３】従つて以上の方法によれば、マスクや薄膜
形成を行うことなく、簡便な方法によつて半導体装置１
上に銅を柱とした、はんだバンプ２０が形成される。Therefore, according to the above method, the semiconductor device 1 can be manufactured by a simple method without forming a mask or a thin film.
Solder bumps 20 having copper as a pillar are formed thereon.
【００３４】なお上述の実施例においては、30〔μｍ〕
の銅ワイヤを使用し、80〔μｍ〕径の銅ボールバンプを
形成したが、半導体チツプのパツドピツチやパツドの広
さ等に応じて、当該銅ワイヤ１５の径やスパーク条件等
を変更し、バンプ径を適宜設定するのが良い。In the above embodiment, 30 [μm]
A copper ball bump having a diameter of 80 [μm] was formed using the copper wire of the above. The diameter of the copper wire 15 and the spark condition are changed according to the pad pitch of the semiconductor chip and the size of the pad. It is better to set the diameter appropriately.
【００３５】[0035]
【発明の効果】上述のように本発明によれば、それぞれ
の半導体装置のパツド電極配置ごとにボンデイングの位
置をプログラム入力することによつて自由に設定できる
ワイヤボンダを使用して、ボールボンデイング方法によ
つて、アルミニウム電極上に銅バンプを形成しているた
め、各半導体装置の種類ごとにマスクを毎回作成する必
要がなく、また無電解めつき法を採用しているので従来
の電解めつき時に必要であつた共通電極のための金属薄
膜を形成する必要がない。As described above, according to the present invention, the ball bonding method can be applied by using the wire bonder which can be freely set by program-inputting the bonding position for each pad electrode arrangement of each semiconductor device. Therefore, because the copper bumps are formed on the aluminum electrodes, it is not necessary to create a mask for each type of semiconductor device each time. It is not necessary to form a metal thin film for the common electrode, which is necessary.
【００３６】かくして半導体装置にワイヤボンダを使用
して銅バンプを形成し、さらに当該銅バンプを無電解は
んだめつきすることによつて銅を柱とするはんだバンプ
を形成できることにより、マスクや薄膜形成用の大掛か
りな装置を必要とすることなく、簡便な方法によつて簡
単かつ短期間でバンプを形成することができる。Thus, a copper bump can be formed on the semiconductor device by using a wire bonder, and the copper bump can be formed by soldering the copper bump with electroless solder, thereby forming a mask or a thin film. The bumps can be formed easily and in a short period of time by a simple method without the need for a large-scale device.
【図１】本発明による半導体装置へのバンプ形成工程に
用いられるワイヤボンダの構成を示す略線図である。FIG. 1 is a schematic diagram showing a configuration of a wire bonder used in a bump forming process for a semiconductor device according to the present invention.
【図２】本発明による半導体装置へのバンプ形成製造方
法の説明に供する側断面図である。FIG. 2 is a side sectional view for explaining a method for manufacturing bumps on a semiconductor device according to the present invention.
【図３】本発明による半導体装置へのバンプ形成製造方
法の説明に供する側断面図である。FIG. 3 is a side sectional view for explaining a method for manufacturing bumps on a semiconductor device according to the present invention.
【図４】従来の半導体装置へのバンプ形成製造方法の説
明に供する側断面図である。FIG. 4 is a side sectional view for explaining a conventional method for manufacturing bumps on a semiconductor device.
【図５】従来の半導体装置へのバンプ形成製造方法の説
明に供する側断面図である。FIG. 5 is a side sectional view for explaining a conventional method for manufacturing bumps on a semiconductor device.
【図６】従来の半導体装置へのバンプ形成製造方法の説
明に供する側断面図である。FIG. 6 is a side sectional view for explaining a conventional method for manufacturing bumps on a semiconductor device.
１……半導体装置、２……アルミニウムパツド、３……
酸化アルミニウム、４……表面保護用パツシベーシヨン
膜、１５……銅ワイヤ、１６……キヤピラリ、１７……
銅バンプ、１８……はんだ、２０……はんだバンプ、３
０……ワイヤボンダ。1 ... Semiconductor device, 2 ... Aluminum pad, 3 ...
Aluminum oxide, 4 …… passivation film for surface protection, 15 …… copper wire, 16 …… capillary, 17 ……
Copper bumps, 18 ... Solder, 20 ... Solder bumps, 3
0 ... Wire bonder.
Claims (4)
体装置の製造方法において、 半導体装置上に銅ワイヤによるボールボンデイングによ
つて銅バンプを形成し、 上記銅バンプ表面に対して無電解はんだめつきによつて
はんだを付着させ、上記銅バンプを中心に有するはんだ
バンプを形成することを特徴とする半導体装置の製造方
法。1. A method of manufacturing a semiconductor device in which bumps are formed on a semiconductor device, wherein copper bumps are formed on the semiconductor device by ball bonding with a copper wire, and an electroless solder is formed on the surface of the copper bumps. A method of manufacturing a semiconductor device, characterized in that solder is attached by damaging to form a solder bump having the copper bump as a center.
上のアルミニウムパツドに銅ワイヤを直接ボールボンデ
イングして上記銅バンプを形成することを特徴とする請
求項１に記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the copper bump is formed by directly ball-bonding a copper wire to an aluminum pad on the semiconductor device. Method.
工程によつて付着することを特徴とする請求項１に記載
の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the solder is attached by a soldering process using a substitution method.
れた回路基板上へ実装する前に少なくとも１回加熱溶融
することを特徴とする請求項１に記載の半導体装置の製
造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the solder bump is heated and melted at least once before being mounted on a circuit board on which a wiring pattern is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5344075A JPH07176535A (en) | 1993-12-18 | 1993-12-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5344075A JPH07176535A (en) | 1993-12-18 | 1993-12-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07176535A true JPH07176535A (en) | 1995-07-14 |
Family
ID=18366470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5344075A Pending JPH07176535A (en) | 1993-12-18 | 1993-12-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07176535A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10242148A (en) * | 1997-02-26 | 1998-09-11 | Matsushita Electric Ind Co Ltd | Method for forming solder bumps |
| WO2002003447A1 (en) * | 2000-07-04 | 2002-01-10 | Matsushita Electric Industrial Co., Ltd. | Device and method for forming bump |
| KR100648039B1 (en) * | 2004-09-13 | 2006-11-23 | 삼성전자주식회사 | method of forming solder ball and related fabrication and structure of semiconductor package using the method |
| CN111148427A (en) * | 2019-12-31 | 2020-05-12 | 无锡市同步电子制造有限公司 | Repair process of stacking/I-shaped preset solder terminal connector |
-
1993
- 1993-12-18 JP JP5344075A patent/JPH07176535A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10242148A (en) * | 1997-02-26 | 1998-09-11 | Matsushita Electric Ind Co Ltd | Method for forming solder bumps |
| WO2002003447A1 (en) * | 2000-07-04 | 2002-01-10 | Matsushita Electric Industrial Co., Ltd. | Device and method for forming bump |
| US6910613B2 (en) | 2000-07-04 | 2005-06-28 | Matsushita Electric Industrial Co., Ltd. | Device and method for forming bump |
| CN100383915C (en) * | 2000-07-04 | 2008-04-23 | 松下电器产业株式会社 | Apparatus and method for forming bump |
| KR100648039B1 (en) * | 2004-09-13 | 2006-11-23 | 삼성전자주식회사 | method of forming solder ball and related fabrication and structure of semiconductor package using the method |
| CN111148427A (en) * | 2019-12-31 | 2020-05-12 | 无锡市同步电子制造有限公司 | Repair process of stacking/I-shaped preset solder terminal connector |
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