JPH02277251A - Method and apparatus for wire bonding - Google Patents

Method and apparatus for wire bonding

Info

Publication number
JPH02277251A
JPH02277251A JP1098549A JP9854989A JPH02277251A JP H02277251 A JPH02277251 A JP H02277251A JP 1098549 A JP1098549 A JP 1098549A JP 9854989 A JP9854989 A JP 9854989A JP H02277251 A JPH02277251 A JP H02277251A
Authority
JP
Japan
Prior art keywords
bonding
wire
inner lead
coated
covered wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1098549A
Other languages
Japanese (ja)
Inventor
Hiroshi Watanabe
宏 渡辺
Susumu Okikawa
進 沖川
Hiroshi Mikino
三木野　博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1098549A priority Critical patent/JPH02277251A/en
Priority to KR1019890011636A priority patent/KR900004009A/en
Priority to US07/395,088 priority patent/US5031821A/en
Publication of JPH02277251A publication Critical patent/JPH02277251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance reliability of a bonding operation by a method wherein, when a covered wire is connected, it is held by using a fixation means provided with a contact face of a rough face with respect to an inner lead. CONSTITUTION:When a first part formed on a semiconductor chip 13 is connected to a second part on an inner lead 6 of a lead frame 11 by using a covered wire 21 to which an insulator 24 has been applied at the circumference of a metal wire 22, the covered wire is held by using a fixation means 7 provided with a contact face of a rough face with respect to an inner lead 7 when at least the covered wire 21 is bonded to the second part. As a result, it is possible to prevent a resonance, of the inner lead 6, which is caused by an ultrasonic oscillation from a bonding tool 20; accordingly, the covered film 24 of the covered wire 21 can be removed surely. Thereby, it is possible to sharply enhance bonding reliability at a wire bonding operation using the covered wire.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ワイヤボンディング技術、特に被覆ワイヤを
用いた第２ボンデイングにおけるボンディング信頼性の
向上に適用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wire bonding technology, particularly to a technology that is effective when applied to improve bonding reliability in second bonding using covered wire.

〔従来の技術〕[Conventional technology]

この種の被覆ワイヤを使用したワイヤボンディング技術
について記載されている例としては、本出願人による特
開昭６３−１８２８２９号公報がある。An example of a wire bonding technique using a coated wire of this type is disclosed in Japanese Patent Application Laid-open No. 182829/1983 by the present applicant.

上記公報に記載された技術によれば、被覆ワイヤを用い
たボンディング技術特有の問題が種々説明されている。According to the techniques described in the above-mentioned publications, various problems specific to bonding techniques using coated wires are explained.

たとえば、被覆ワイヤを用いたワイヤボンディングにお
いては、金属線の表面が絶縁樹脂で覆われた構造となっ
ているため、スプールからの供給経路において金属線を
電気的に接地（基準電位、たとえば０［Ｖ］）させるこ
とができず、ボール形成の際にアークが不十分となり所
定形状のボールが形成できない等の難点等が指摘されて
いる。For example, in wire bonding using coated wire, the surface of the metal wire is covered with an insulating resin, so the metal wire is electrically grounded (reference potential, e.g. 0[ Difficulties such as the inability to form a ball with a predetermined shape due to insufficient arcing during ball formation have been pointed out.

上記のような技術的課題を解決するために、上記公報で
はスプールに設けられた接続端子によって金属線を基準
電位に維持し第１ボンデイングの信頼性を高める技術を
開示した。In order to solve the above technical problems, the above publication discloses a technique for maintaining the metal wire at a reference potential using a connecting terminal provided on the spool to improve the reliability of the first bonding.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上記公報等に記載された技術においては、被覆
ワイヤを用いたワイヤボンディングにおける第２ボンデ
イングの接合信頼性の向上に対しては十分に配慮されて
はいなかった。However, in the techniques described in the above-mentioned publications, etc., sufficient consideration has not been given to improving the bonding reliability of the second bonding in wire bonding using coated wire.

すなわち、被覆ワイヤによる第２ボンデイングでは、何
等かの手段で金属線の周囲の被覆膜を除去して金属線の
表面を露出させ、該露出部分をインナーリード等のボン
ディングポイントに接合しなければならない。このよう
な手段としては、被覆ワイヤにおける第２ボンデイング
の箇所の被覆膜を予め火炎あるいは放電の印加等により
除去しておく方法がある。この場合には第２ボンディン
グ時に既に金属線の表面が露出状態となっているため、
通常の裸線を用いた第２ボンデイングと略同様のボンデ
ィング技術を用いることができる。That is, in the second bonding using a covered wire, the coating film around the metal wire must be removed by some means to expose the surface of the metal wire, and the exposed portion must be bonded to a bonding point such as an inner lead. No. As such a method, there is a method in which the coating film at the second bonding location on the covered wire is removed in advance by applying flame or electric discharge. In this case, the surface of the metal wire is already exposed during the second bonding, so
A bonding technique substantially similar to the second bonding using ordinary bare wires can be used.

しかし、第２ボンデイングの位置を予め正確に予測して
該当箇所の被覆膜を除去するためにはワイヤボンディン
グ装置および制御プログラムが複雑化し実用的ではなか
った。However, in order to accurately predict the position of the second bonding in advance and remove the coating film at the corresponding location, the wire bonding apparatus and control program become complicated and are not practical.

そのため、現状では予め被覆膜を除去することなく、第
２ボンデイングの段階で被覆ワイヤをインナーリード等
の表面に超音波振動等により擦り付け、この部分の被覆
膜を機械的に剥離・除去して金属線の表面を露出させな
がらボンディングポイントに接合させる方法が一般的で
ある。Therefore, at present, without removing the coating film in advance, the coated wire is rubbed against the surface of the inner lead etc. using ultrasonic vibration in the second bonding stage, and the coating film on this part is mechanically peeled off and removed. A common method is to bond the metal wire to the bonding point while exposing the surface of the metal wire.

しかし、第２ボンデイングと同時に被覆膜の除去を行う
当該技術では、下記のような課題のあることが本発明者
によって見い出された。However, the inventors have discovered that the technique in which the coating film is removed simultaneously with the second bonding has the following problems.

すなわち上記従来技術では、第２ボンディング時のイン
ナーリードの固定が不完全なために第２ボンディング部
位における被覆ワイヤの被覆膜の除去が完全に行われて
おらず、いわゆるはがれ不良等のボンディング不良が多
く発生していた。In other words, in the above-mentioned conventional technology, since the inner lead is not completely fixed during the second bonding, the coating film of the covered wire is not completely removed at the second bonding site, resulting in bonding defects such as so-called peeling defects. was occurring frequently.

本発明者はこの原因が下記の２点にあることを見い出し
た。The inventor of the present invention found that this is caused by the following two points.

第１に、被覆膜の除去が不完全となるのはボンディング
ツール底面とインナーリード面との平行性が維持できて
いない場合に多い。First, incomplete removal of the coating film often occurs when the parallelism between the bottom surface of the bonding tool and the inner lead surface cannot be maintained.

すなわち、インナーリード面に対してボンディングツー
ル底面が傾いており、これによってボンディングツール
が片あたりした状態であると、被覆膜は局所的に押し潰
されるのみで金属線から完全に剥離せずにはがれ不良等
を引き起こす。In other words, the bottom surface of the bonding tool is tilted with respect to the inner lead surface, and if the bonding tool is in a state of uneven contact, the coating film will only be crushed locally and will not be completely peeled off from the metal wire. This may cause peeling defects, etc.

第２に、上記平行性が維持できていたとしても、インナ
ーリードの固定が不十分であると、超音波振動の印加時
にインナーリードが共振してしまい、超音波発振パワー
が被覆膜に対して有効に作用せず、被覆膜の剥離が不十
分な状態となり、上記と同様にはがれ不良の要因となる
。このような現象は特にインナーリードの延設方向に対
して垂直方向に超音波振動を印加した場合にインナーリ
ードの横ぶれとして表れ、ボンディング不良を引き起こ
すことが本発明者によって見い出された。Second, even if the above parallelism is maintained, if the inner lead is not fixed sufficiently, the inner lead will resonate when ultrasonic vibration is applied, and the ultrasonic oscillation power will be applied to the coating film. This does not work effectively, resulting in insufficient peeling of the coating film, which causes poor peeling as described above. The inventors have discovered that such a phenomenon appears as lateral wobbling of the inner lead, causing bonding failure, especially when ultrasonic vibration is applied in a direction perpendicular to the direction in which the inner lead extends.

本発明の目的は、上記の点に鑑みて、被覆ワイヤを用い
たワイヤボンディングにおいて第２ボンデイングの接合
信頼性を高めることのできる技術を提供することにある
。In view of the above points, an object of the present invention is to provide a technique that can improve the bonding reliability of the second bonding in wire bonding using a covered wire.

本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、概ね次のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体チップ上に形成された第１の部位とリ
ードフレームのインナーリード上の第２の部位とを金属
線の周囲に絶縁物が被着された被覆ワイヤで結線する際
に、少なくとも被覆ワイヤの第２の部位への接合時に、
インナーリードに対して粗面の接触面を備えた固定手段
で保持するものである。That is, when connecting a first part formed on a semiconductor chip and a second part on an inner lead of a lead frame with a covered wire having an insulator coated around a metal wire, at least the covered wire is When joining to the second part of
The inner lead is held by a fixing means having a rough contact surface.

〔作用〕[Effect]

上記した手段によれば、粗面化された接触面（たとえば
ボンディングステージ面）によってインナーリードが固
定されるため、ボンディングツールからの超音波振動の
印加によるインナーリードの共振が防止されるため、特
に第２ポンデイングにおける被覆ワイヤの被覆膜の除去
が確実に行われる。According to the above means, since the inner lead is fixed by the roughened contact surface (for example, the bonding stage surface), resonance of the inner lead due to the application of ultrasonic vibration from the bonding tool is prevented. The coating film of the coated wire is reliably removed in the second pounding.

また、ボンディングステージ等の位置固定溝を設けて固
定手段によるインナーリードの固定をインナーリード面
と固定手段の接触面とが平行になるようにすることによ
って、インナーリードの横ぶれを効果的に防止できる。In addition, by providing position fixing grooves for the bonding stage, etc., and fixing the inner lead by the fixing means so that the inner lead surface and the contact surface of the fixing means are parallel, it effectively prevents the inner lead from lateral wobbling. can.

〔実施例〕〔Example〕

第１図（ａ）は本発明の一実施例であるワイヤボンディ
ング工程におけるヒートブロック、押さえ板、リードフ
レーム等の配置状態を示した説明図、第１図ら）はダイ
ヤモンド電着層の表面状態を示す拡大説明図、第２図は
本実施例の効果を従来技術と比較した説明図、第３図は
本実施例により得られる半導体装置を示す断面図、第４
図はワイヤボンディングの状態を示す断面図、第５図は
従来方法と本実施例の方法により得られた半導体装置の
熱サイクル試験結果の比較を示す説明図である。FIG. 1(a) is an explanatory diagram showing the arrangement of heat blocks, pressing plates, lead frames, etc. in the wire bonding process according to an embodiment of the present invention, and FIG. 1(a) shows the surface state of the diamond electrodeposited layer. FIG. 2 is an explanatory diagram comparing the effect of this embodiment with that of the prior art, FIG. 3 is a sectional view showing a semiconductor device obtained by this embodiment, and FIG.
The figure is a sectional view showing the state of wire bonding, and FIG. 5 is an explanatory view showing a comparison of thermal cycle test results of semiconductor devices obtained by the conventional method and the method of this embodiment.

本実施例のワイヤボンディング装置におけるボンディン
グステージ１の特徴は、第１図（ａ）に示すとおりであ
り、ボンディングステージ１の上面はヒートブロック２
により構成されており、該ヒートブロック２の表面には
バンク部３および位置固定溝４が形成されている。上記
バンク部３はタブ５の位置の固定ならびにワイヤループ
を一定の高さに位置するために設けられている。The features of the bonding stage 1 in the wire bonding apparatus of this embodiment are as shown in FIG.
A bank portion 3 and a position fixing groove 4 are formed on the surface of the heat block 2. The bank portion 3 is provided to fix the position of the tab 5 and to position the wire loop at a constant height.

また、位置固定溝４はインナーリード６の先端よりも僅
かに外方に形成され、当該位置固定溝４のエツジ４ａと
上方からの押さえ板７とによってインナーリード６が挟
持されることでインナーリード面６ａとボンディングス
テージ面１ａとの平行性が確保されるようになっている
。Further, the position fixing groove 4 is formed slightly outward from the tip of the inner lead 6, and the inner lead 6 is held between the edge 4a of the position fixing groove 4 and the presser plate 7 from above. Parallelism between the surface 6a and the bonding stage surface 1a is ensured.

上記ヒートブロック２および押さえ板７の表面にはダイ
ヤモンド電着層８が形成されている。このようなダイヤ
モンド電着層８の表面状態は第１図（ｂ）に示す通りで
ある。ダイヤモンド電着層８の形成は、まず径が１５〜
２０μｍのダイヤモンド微粒１０　（できるだけ鋭角な
粒状のものが望ましい）に対してニッケル（Ｎｉ）をコ
ーティングしたものを用意し、該コーティング済のダイ
ヤモンド微粒１０を電気泳動によってボンディングステ
ージ１　（ヒートブロック２）となるステンレス基板の
表面に吸着させる。A diamond electrodeposition layer 8 is formed on the surfaces of the heat block 2 and the pressing plate 7. The surface condition of such a diamond electrodeposited layer 8 is as shown in FIG. 1(b). The formation of the diamond electrodeposited layer 8 begins with the diamond electrodeposited layer 8 having a diameter of 15 to
Prepare 20 μm diamond particles 10 (preferably particles with as sharp an angle as possible) coated with nickel (Ni), and apply the coated diamond particles 10 to the bonding stage 1 (heat block 2) by electrophoresis. It is adsorbed onto the surface of a stainless steel substrate.

次いで、ダイヤモンド微粒ｌＯが付着された状態で上記
ステンレス基板を加熱して上記Ｎｉを溶融させて上記ダ
イヤモンド微粒１０をステンレス基板の表面に対して固
定させるものである。Next, the stainless steel substrate with the diamond fine particles 10 attached thereto is heated to melt the Ni and fix the diamond fine particles 10 to the surface of the stainless steel substrate.

なお、ダイヤモンド微粒１０の径については上記数値の
範囲外のものでもよいが、径が大きくなりすぎると径の
ばらつきにより固定状態でのインナーリード６が傾くお
それがあり、逆に径が小さいと摩擦係数が低下してイン
ナーリード６の固定が確実に行えないおそれがある。Note that the diameter of the diamond particles 10 may be outside the above numerical range, but if the diameter is too large, there is a risk that the inner lead 6 in the fixed state may tilt due to variations in the diameter, and conversely, if the diameter is small, friction may occur. There is a possibility that the coefficient may decrease and the inner lead 6 may not be securely fixed.

また、ダイヤモンド電着層８を形成する他に、ボンディ
ングステージ１　（ヒートブロック２）の表面に直接傷
を付ける等して粗面化することも考えられるが、傷を付
ける程度の粗面化では十分な固定効果は得られなかった
。In addition to forming the diamond electrodeposited layer 8, it is also possible to roughen the surface of the bonding stage 1 (heat block 2) by directly scratching it. Sufficient fixed effects were not obtained.

上記ボンディングステージ面１ａに対して供給されるリ
ードフレーム１１は中央にタブ５を有しており、その周
囲に図示しないフレーム枠より延設されたインナーリー
ド６がタブ５とは非接触の状態で延設されている。The lead frame 11 supplied to the bonding stage surface 1a has a tab 5 at the center, and inner leads 6 extending from a frame (not shown) around the tab 5 are not in contact with the tab 5. It has been extended.

このようなリードフレーム１１は、たとえばコバール、
４２７０イあるいはニッケル合金等で構成された厚さ０
．１５ｎｏｎ程度の板状部材に対してプレス加工あるい
はエツチング処理を施すことによって得られるものであ
る。Such a lead frame 11 is made of, for example, Kovar,
0 thickness made of 4270 or nickel alloy, etc.
．． It is obtained by performing press processing or etching treatment on a plate-like member of about 15non.

上記タブ５上には第４図に示すように、厚さ３０μｍ程
度に被着された銀ペースト、シリコンペーストあるいは
金箔等の接合材１２を介して半導体チップ１３が固定さ
れている。As shown in FIG. 4, a semiconductor chip 13 is fixed onto the tab 5 via a bonding material 12 such as silver paste, silicone paste, or gold foil applied to a thickness of about 30 μm.

この半導体チップ１３の上層には詳細な図示を省略する
が、フォトレジスト技術を用いた酸化・拡散工程を通じ
てマイクロプロセッサ、あるいは論理回路、記憶回路等
が形成されている。半導体チップ１３の内部における各
層の概略構成について簡単に説明すると、厚さ４００μ
ｍ程度で形成されたシリコン（Ｓｉ）からなるチップ基
板１４の上層には０．４５μｍ程度のシリコン酸化膜１
５が形成され、さらにその上層には層間絶縁膜としての
ＰＳＧ膜１６が０．３μｍ程度の厚さで形成されている
。最上層には保護膜としてのパッシベーション膜１７が
１．２μｍ程度の厚さで被着されており、その一部は開
口されて下層にふいて部分的に設けられたアルミニウム
（Ａｆ）からなる厚さ０、８μｍ程度のポンディングパ
ッド１８が露出されている。Although not shown in detail in the upper layer of this semiconductor chip 13, a microprocessor, logic circuit, memory circuit, etc. are formed through an oxidation/diffusion process using photoresist technology. To briefly explain the schematic structure of each layer inside the semiconductor chip 13, the thickness is 400 μm.
On the upper layer of the chip substrate 14 made of silicon (Si) formed with a thickness of about 0.45 μm, a silicon oxide film 1 of about 0.45 μm is formed.
A PSG film 16 having a thickness of about 0.3 μm is formed as an interlayer insulating film on top of the PSG film 5. A passivation film 17 as a protective film is deposited on the uppermost layer to a thickness of about 1.2 μm, and a portion of the passivation film 17 is opened and a thick film made of aluminum (Af) is partially provided on the lower layer. A bonding pad 18 with a diameter of about 0.8 μm is exposed.

次に、上記ボンデイシダステージ１上におけるワイヤボ
ンディング工程について説明する。Next, the wire bonding process on the bonding fern stage 1 will be explained.

まず、ボンディングステージ１のステージ面ｌａ上に、
半導体チップ１３の装着されたリードフレーム１１が供
給されると、ボンディングツール２０が所定のポンディ
ングパッド１８の直上となるように位置される。First, on the stage surface la of bonding stage 1,
When the lead frame 11 with the semiconductor chip 13 mounted thereon is supplied, the bonding tool 20 is positioned directly above a predetermined bonding pad 18 .

次に、図示しない放電トーチによりボンディングツール
２０より突出された被覆ワイヤ２１　（金属線２２）の
先端との間にアーク放電が発生され、金属線２２の先端
が加熱溶融されて球状のボンディングボール２３が形成
される。当該加熱にともなって、被覆ワイヤ２１の先端
近傍の被覆膜２４としての樹脂は被覆ワイヤ２１の上方
に次第に溶は上がり、ボンディングボール２３の周辺の
金属線２２ａ’Ｂ分が露出される。Next, an arc discharge is generated between the tip of the covered wire 21 (metal wire 22) protruding from the bonding tool 20 by a discharge torch (not shown), and the tip of the metal wire 22 is heated and melted to form a spherical bonding ball 23. is formed. With the heating, the resin as the coating film 24 near the tip of the coated wire 21 gradually melts upwards of the coated wire 21, and the portion of the metal wire 22a'B around the bonding ball 23 is exposed.

次に、ボンディングツール２０がポンディングパッド１
８に対して降下するとボンディングツール２０から突出
されたポンディングパッド２３は所定のポンディングパ
ッド１８の表面に着地する。Next, the bonding tool 20 is attached to the bonding pad 1.
8, the bonding pad 23 protruding from the bonding tool 20 lands on the surface of a predetermined bonding pad 18.

続いて、ボンディングツール２０の先端に所定の荷重が
印加されるとともに、所定周波数の超音波振動がボンデ
ィングツール２０の先端に印加される。Subsequently, a predetermined load is applied to the tip of the bonding tool 20, and ultrasonic vibrations of a predetermined frequency are applied to the tip of the bonding tool 20.

この超音波発振パワーと加熱と荷重との相乗効果によっ
て、ボンディングボール２３は上記ポンディングパッド
１８の表面に接合され、第１ポンデイングが完了する。Due to the synergistic effect of this ultrasonic oscillation power, heating, and load, the bonding ball 23 is bonded to the surface of the bonding pad 18, and the first bonding is completed.

続いて、ボンディングツール２０の上方および水平方向
への移動によって被覆ワイヤ２１の途中部分はボンディ
ングツール２０の先端から導出されながらループを描く
ように張設して、所定のインナーリード６の直上に移動
する。Next, by moving the bonding tool 20 upward and horizontally, the intermediate portion of the coated wire 21 is drawn out from the tip of the bonding tool 20 and stretched in a loop, and is moved directly above a predetermined inner lead 6. do.

次に、ボンディングツール２０の先端は被覆ワイヤ２１
を導出したままの状態で上記インナーリード６の所定位
置に着地される。ここで、再度ボンディングツール２０
に対して超音波振動が印加されると、ボンディングツー
ル２０の先端より導出された被覆ワイヤ２１の腹部はイ
ンナーリード６の表面に対して凛り付けられ、これによ
ってインナーリード６との接触部分の被覆ワイヤ２１の
被覆膜２４が剥離される。Next, the tip of the bonding tool 20 is connected to the coated wire 21.
It lands at a predetermined position on the inner lead 6 with the lead still drawn out. Here, use the bonding tool 20 again.
When ultrasonic vibration is applied to the bonding tool 20 , the abdomen of the coated wire 21 led out from the tip of the bonding tool 20 is stiffened against the surface of the inner lead 6 , thereby causing the contact portion with the inner lead 6 to become stiffer. The coating film 24 of the covered wire 21 is peeled off.

被覆膜２４が剥離された後、さらに超音波振動の印加が
継続されることによって、露出状顎とされた軸線（金属
線２２）がインナーリード６の表面に対して接合される
。このとき、超音１１振動の印加とともに図示しないヒ
ータ等の加熱源をボンディングステージ１内に内蔵し、
第２ボンディング部位の加熱を行ってもよい。さらに、
上記超音波振動は第１ボンデイングの完了後、第２ボン
デイングの位置までボンディングソール２０が移動する
までの間継続して行うようにしてもよい。このようにボ
ンディングツール２０の移動途中も超音波振動の印加を
継続することによって、ボンディングツール２０内での
被覆ワイヤ２１の曲がりクセ等を防止できるため、目詰
まりを防止できる効果もある。After the coating film 24 is peeled off, the application of ultrasonic vibration is continued, so that the exposed jaw axis (metal wire 22) is bonded to the surface of the inner lead 6. At this time, along with the application of ultrasonic 11 vibrations, a heating source such as a heater (not shown) is built into the bonding stage 1,
The second bonding site may be heated. moreover,
The ultrasonic vibration may be continued after the first bonding is completed until the bonding sole 20 moves to the second bonding position. By continuing to apply ultrasonic vibrations even during the movement of the bonding tool 20 in this way, it is possible to prevent the coated wire 21 from bending inside the bonding tool 20, thereby having the effect of preventing clogging.

本実施例では、このような第２ボンデイングにおける超
音波振動の印加時において、前述の説明のように、イン
ナーリード６は押さえ板７と押え駒との表面に各々形成
されたダイヤモンド電着層８によって確実に固定されて
いる。このため、インナーリード６の共振を防止するこ
とができ、被覆膜２４の剥離を確実に行うことができる
。In this embodiment, when the ultrasonic vibration is applied in the second bonding, the inner lead 6 is exposed to the diamond electrodeposited layer 8 formed on the surfaces of the presser plate 7 and the presser piece, respectively, as described above. is securely fixed. Therefore, resonance of the inner lead 6 can be prevented, and the coating film 24 can be reliably peeled off.

また、本実施例ではさらに位置固定溝４のエツジ４ａと
押さえ板７とによって、インナーリード６の表面がボン
ディングステージ１の表面と平行状態を維持するように
固定されているため、インナーリード６の傾き等に起因
するボンディング不良も防止される。Furthermore, in this embodiment, the surface of the inner lead 6 is fixed by the edge 4a of the position fixing groove 4 and the presser plate 7 so as to maintain a state parallel to the surface of the bonding stage 1. Bonding defects caused by inclination and the like are also prevented.

上記のようにして被覆ワイヤ２１の接合が完了した後、
ボンディングツール２０の上方において被覆ワイヤ２１
が図示しないクランパ等により挟持された状態となり、
続いてボンディングツール２０が所定量２方向に上昇さ
れると、被覆ワイヤ２１は上記ボンディング部分よりそ
の不要部分を切断されて第２ボンデイングを完了する。After the bonding of the covered wire 21 is completed as described above,
Covered wire 21 above bonding tool 20
is clamped by a clamper (not shown), etc.
Subsequently, when the bonding tool 20 is raised by a predetermined amount in two directions, the unnecessary portion of the covered wire 21 is cut off from the bonding portion to complete the second bonding.

以上に説明したボンディングサイクルを、全てのポンデ
ィングパッド１８とインナーリード６について所定回数
だけ繰り返すことによって半導体チップ１３とインナー
リード６との電気的導通が実現される。Electrical continuity between the semiconductor chip 13 and the inner leads 6 is achieved by repeating the bonding cycle described above a predetermined number of times for all bonding pads 18 and inner leads 6.

上記ワイヤボンディング工程の後、リードフレーム１１
は図示しない金型内に装着され、この金型内に溶融状態
の合成樹脂が高圧注入されることにより半導体装置２５
のパッケージ本体２６が形成される。After the wire bonding process, the lead frame 11
The semiconductor device 25 is mounted in a mold (not shown), and molten synthetic resin is injected at high pressure into the mold.
A package body 26 is formed.

次に、本実施例により得られた具体的な効果を本発明者
の実験結果によって説明する。Next, specific effects obtained by this example will be explained based on experimental results by the inventor.

第２図（ａ）は本実施例と従来技術との比較を示したも
のである。本発明者は、■従来構造のボンディングステ
ージ、■位置固定溝４を備えたボンディングステージ、
■位置固定溝４とダイヤモンド電着層８とを備えたボン
ディングステージ１の３種類のボンディングステージを
用いて第２ボンデイング側の被覆ワイヤ２１の剥がれお
よび切断率と超音波発振パワーとの関係を検査したもの
である。FIG. 2(a) shows a comparison between this embodiment and the prior art. The present inventor has proposed: (1) a bonding stage with a conventional structure; (2) a bonding stage equipped with a position fixing groove 4;
■Inspection of the relationship between peeling and cutting rate of the coated wire 21 on the second bonding side and ultrasonic oscillation power using three types of bonding stages: the bonding stage 1 equipped with the position fixing groove 4 and the diamond electrodeposited layer 8 This is what I did.

第２図ら）は第２ボンデイング側のワイヤのつぶれ幅と
超音波発振パワーとの関係、第２図（Ｃ）はワイヤの引
っ張り強度と超音波発振パワーとの関係をそれぞれ示し
たものである。2) shows the relationship between the collapse width of the wire on the second bonding side and the ultrasonic oscillation power, and FIG. 2(C) shows the relationship between the tensile strength of the wire and the ultrasonic oscillation power.

上記第２図（ｂ）からも明らかなように、超音波発振パ
ワーを大きくしていくと第２ボンデイング側のワイヤの
つぶれ幅が大きくなり、ワイヤの肉厚が薄くなるため、
同図（Ｃ）に示すように引っ張り強度が低下する。また
ワイヤボンディング時における第２ボンディング部位の
切断も発生しやすくなる。As is clear from FIG. 2(b) above, as the ultrasonic oscillation power increases, the width of the wire collapse on the second bonding side increases, and the thickness of the wire decreases.
As shown in the same figure (C), the tensile strength decreases. Furthermore, the second bonding site is more likely to be cut during wire bonding.

したがって、超音波発振パワーはできるだけ小さく設定
して第２ボンデイング側のワイヤのつぶれ幅を少なくす
ることが望ましいわけであるが、超音波発振パワーを極
端に低下させると第１図（ａ）に示すように被覆膜２４
の破壊力が逆に低下し、ボンディング後の剥がれ率が上
昇するため、超音波発振パワーは剥がれの発生しない限
界値あるいはそれよりもわずかに高い値に設定する必要
がある。Therefore, it is desirable to set the ultrasonic oscillation power as low as possible to reduce the amount of collapse of the wire on the second bonding side, but if the ultrasonic oscillation power is extremely reduced, as shown in Figure 1 (a) The coating film 24
On the contrary, the destructive force of the bonding material decreases, and the peeling rate after bonding increases. Therefore, the ultrasonic oscillation power must be set at a limit value that does not cause peeling, or a value slightly higher than that.

この点に関して、従来技術のボンディングステージ構造
（■）では、インナーリード６の共振により超音波発振
パワーが被覆膜２４の除去にとって有効に作用しないた
め、超音波発振パワーを９Ｑｂｉｔｓまで上げないと剥
がれを防止することができなかった。このため、ボンデ
ィング作業可能領域が９Ｑｂｉｔｓから切断の生じる直
前値である１２Ｑｂｉｔｓまでと狭く、この領域では同
図（Ｃ）にも示すように引っ張り強度も低い値となって
いた。Regarding this point, in the conventional bonding stage structure (■), the ultrasonic oscillation power does not work effectively for removing the coating film 24 due to the resonance of the inner lead 6, so the ultrasonic oscillation power must be increased to 9Qbits or it will peel off. could not be prevented. For this reason, the bonding workable region is narrow from 9Qbits to 12Qbits, which is the value immediately before disconnection occurs, and the tensile strength is also low in this region, as shown in FIG.

これに対して、ボンディングステージに位置固定溝４を
設けた構造（■）では、第２図（ａ）に示す特性白線の
ように、インナーリード６の固定状態が比較的安定し、
超音波発振パワーにおけるはがれ発生の限界値を８０ｂ
ｉｔＳにまで下げることが可能となった。On the other hand, in the structure (■) in which the position fixing groove 4 is provided in the bonding stage, the fixed state of the inner lead 6 is relatively stable, as shown by the characteristic white line shown in FIG. 2(a).
The limit value for peeling at ultrasonic oscillation power is 80b.
It became possible to lower it to itS.

さらに、上記位置固定溝４とともに、ダイヤモンド電着
層８を設けたボンディングステージｌの構造（■）では
、インナーリード６の固定はさらに安定し、超音波発振
パワーを５Ｑｂｉｔｓにまで下げることが可能となった
。Furthermore, with the structure of the bonding stage l (■) in which the diamond electrodeposited layer 8 is provided in addition to the position fixing groove 4, the fixation of the inner lead 6 becomes even more stable, and the ultrasonic oscillation power can be lowered to 5 Qbits. became.

このように、本実施例ではまず位置固定溝４を設けた構
造（■）とすることによりイ、ンナーリード６の固定を
安定化させることができ、さらにダイヤモンド電着層８
を設けることによって、さらに固定を安定させられる。As described above, in this embodiment, firstly, by adopting the structure (■) in which the position fixing groove 4 is provided, the fixing of the inner lead 6 can be stabilized, and furthermore, the diamond electrodeposited layer 8
By providing this, the fixation can be further stabilized.

この結果、ワイヤボンディングの作業領域が６０〜１２
０ｂｉｔｓに拡大するため、安定的なワイヤボンディン
グが実現するとともに、接合信頼性の高い半導体装置を
供給することができる。As a result, the working area for wire bonding is 60 to 12
Since the wire bonding is expanded to 0 bits, stable wire bonding can be realized and a semiconductor device with high bonding reliability can be provided.

第３図は、本実施例を通じて得られる半導体装置２５の
完成状態を示す断面図である。同図では、上記のワイヤ
ボンディング工程を結線された半導体チップ１３とリー
ドフレーム１１とが樹脂モールド法によりエポキシ樹脂
で封止されている。当該樹脂モールド工程では、図示し
ない金型内に溶融状態のエポキシ樹脂を高圧注入するた
め、被覆ワイヤ２１の流れあるいは断線等を生じる場合
があるが、本実施例によれば、上記の如く接合強度の高
いワイヤボンディングが行われているために、このよう
なワイヤ流れ、断線等は生じない。FIG. 3 is a cross-sectional view showing the completed state of the semiconductor device 25 obtained through this example. In the figure, a semiconductor chip 13 and a lead frame 11, which have been connected through the wire bonding process described above, are sealed with epoxy resin by a resin molding method. In the resin molding process, molten epoxy resin is injected at high pressure into a mold (not shown), which may cause the covered wire 21 to flow or break. However, according to this embodiment, the bonding strength is improved as described above. Since wire bonding is performed with high wire bonding, such wire drift, wire breakage, etc. do not occur.

また、被覆ワイヤ２１を用いたワイヤボンディングが実
現されているため、ワイヤ同士の接触が生じても金属線
２２を覆う被覆膜２４同士の接触となるため、電気的短
絡が防止されている。Moreover, since wire bonding is realized using the covered wire 21, even if the wires come into contact with each other, the covering films 24 covering the metal wires 22 come into contact with each other, thereby preventing electrical short circuits.

第４図は、以上のようにして得られた半導体装置２５の
熱サイクル試験結果を示す説明図であり、試験条件は同
図に示す通りである。FIG. 4 is an explanatory diagram showing the results of a thermal cycle test of the semiconductor device 25 obtained as described above, and the test conditions are as shown in the diagram.

同図によれば、ダイヤモンド電着層８を用いない従来技
術のボンディングステージ面造によってワイヤボンディ
ングを実行した場合、５００サイクル以上で第２ボンデ
イング側での断線現象が発生する。これは従来技術では
第２ボンデイングにおけるつぶれ幅が大きくなりすぎて
いるため、接合強度が熱サイクルの繰り返しにより次第
に低下し、熱応力によってついには断線に至るものであ
る。According to the figure, when wire bonding is performed by the bonding stage surface structure of the prior art without using the diamond electrodeposited layer 8, a disconnection phenomenon occurs on the second bonding side after 500 cycles or more. This is because in the prior art, the collapse width in the second bonding is too large, so that the bonding strength gradually decreases with repeated thermal cycles, and the thermal stress eventually leads to wire breakage.

一方、ダイヤモンド電着層８を備えた本実施例のボンデ
ィングツ−ル１の構造によれば、１０００サイクルを完
了した時点においても断線を生じることはなかった。On the other hand, according to the structure of the bonding tool 1 of the present example including the diamond electrodeposited layer 8, no wire breakage occurred even after 1000 cycles were completed.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。たとえば、粗面の形成方
法として接触面にダイヤモンド微粒を電気泳動で被着さ
せた場合で説明したが、ダイヤモンド微粒に限らず硬質
の粒状物を用いてもよい。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, although the method for forming the rough surface has been described in which fine diamond particles are deposited on the contact surface by electrophoresis, the method is not limited to fine diamond particles, and hard granules may be used.

また、ダイヤモンド微粒の被着方法については、実施例
に記載した電気泳動による他、例えば粘着テープにダイ
ヤモンド微粒を吸着させたものをステージ面に貼り付け
てもよい。Further, as for the method of adhering the diamond fine particles, in addition to electrophoresis as described in the examples, for example, an adhesive tape to which diamond fine particles are adsorbed may be attached to the stage surface.

以上の説明では主として本発明者によってなされた発明
をその利用分野である、いわゆる被覆ワイヤを用いたワ
イヤボンディング技術に適用した場合について説明した
が、これに限定されるものではなく、たとえば裸線の金
属線を用いたワイヤボンディング技術にも適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the field of application, which is wire bonding technology using so-called coated wires, but the present invention is not limited to this. It can also be applied to wire bonding technology using metal wires.

裸線の場合には、第２ボンディング時における被覆膜の
剥離という要請はないものの、インナーリードの共振を
防止して接合強度を高めるという必要性は高く、本発明
の適用は極めて有効となる。In the case of bare wires, although there is no requirement to peel off the coating film during the second bonding, there is a strong need to prevent inner lead resonance and increase bonding strength, and the application of the present invention is extremely effective. .

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

本発明によれば、粗面化された接触面（たとえばボンデ
ィングステージ面）によってインナーリードが固定され
るため、ボンディングツールからの超音波振動の印加に
よるインナーリードの共振が防止されるため、特に第２
ボンデイングにおける被覆ワイヤの被覆膜の除去が確実
に行われる。According to the present invention, since the inner lead is fixed by the roughened contact surface (for example, the bonding stage surface), resonance of the inner lead due to the application of ultrasonic vibration from the bonding tool is prevented. 2
Removal of the coating film of the coated wire during bonding is reliably performed.

このため、被覆ワイヤを用いたワイヤボンディングにお
ける接合信頼性を大幅に向上させることができる。Therefore, the bonding reliability in wire bonding using coated wire can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の一実施例であるワイヤボンディ
ング工程におけるヒートブロック、押さえ板、リードフ
レーム等の配置状態を示した説明図、第１図（ｂ）はダ
イヤモンド電着層の表面状態を示す拡大説明図、 第２図（ａ）〜（Ｃ）は本実施例の効果を従来技術と比
較した説明図、 第３図は本実施例により得られる半導体装置を示す断面
図、 第４図はワイヤボンディングの状態を示す断面図、 第５図は従来方法と本実施例の方法により得られた半導
体装置の熱サイクル試験結果の比較を示す説明図である
。 １・・・ボンディングステージ、１ａ・・・ボンディン
グステージ面、２・・・ヒートブロック、３・・・バン
ク部、４・・・位置固定溝、４ａ・・・エツジ、５・・
・タブ、６・・・インナーリード、６ａ・・・インナー
リード面、７・・・押さえ板、８・・・ダイヤモンド電
着層、１０・・・ダイヤモンド微粒、１１・・・リード
フレーム、１２・・・接合材、１３・・・半導体チップ
、１４・・・チップ基板、１５・・・シリコン酸化膜、
１６・・・ＰＳＧ膜、１７・・・パッシベーション膜、
１８・・・ポンディングパッド、２０・・・ボンディン
グツール、２１ ２２・・・金属線、２３・・ ル、２４・・・被覆膜、２５ ２６・・・パッケージ本体。 ・・・被覆ワイヤ、 ・ボンディングボー ・・・半導体装置、FIG. 1(a) is an explanatory diagram showing the arrangement of a heat block, a holding plate, a lead frame, etc. in a wire bonding process according to an embodiment of the present invention, and FIG. 1(b) is an explanatory diagram showing the arrangement of a heat block, a holding plate, a lead frame, etc. in a wire bonding process according to an embodiment of the present invention. 2(a) to 2(C) are explanatory diagrams comparing the effects of this embodiment with the prior art; FIG. 3 is a sectional view showing a semiconductor device obtained by this embodiment; FIG. 4 is a sectional view showing the state of wire bonding, and FIG. 5 is an explanatory diagram showing a comparison of thermal cycle test results of semiconductor devices obtained by the conventional method and the method of this embodiment. DESCRIPTION OF SYMBOLS 1... Bonding stage, 1a... Bonding stage surface, 2... Heat block, 3... Bank part, 4... Position fixing groove, 4a... Edge, 5...
・Tab, 6... Inner lead, 6a... Inner lead surface, 7... Holder plate, 8... Diamond electrodeposited layer, 10... Diamond fine particles, 11... Lead frame, 12. ... Bonding material, 13... Semiconductor chip, 14... Chip substrate, 15... Silicon oxide film,
16... PSG film, 17... Passivation film,
18... Bonding pad, 20... Bonding tool, 21 22... Metal wire, 23... Lu, 24... Covering film, 25 26... Package body. ...Coated wire, -Bonding board...Semiconductor device,

Claims (1)

【特許請求の範囲】 １、半導体チップ上に形成された第１の部位とリードフ
レームのインナーリード上の第２の部位とを金属線の周
囲に絶縁物が被着された被覆ワイヤで結線するワイヤボ
ンディング方法であって、少なくとも被覆ワイヤを第２
の部位に接合する際に、インナーリードに対して粗面の
接触面を備えた固定手段で保持することを特徴とするワ
イヤボンディング方法。 ２、上記粗面の接触面は上記固定手段の接触面上にダイ
ヤモンド粒を被着して形成されていることを特徴とする
請求項１記載のワイヤボンディング方法。 ３、半導体チップ上に形成された第１の部位とリードフ
レームのインナーリード上の第２の部位とを金属線の周
囲に絶縁物が被着された被覆ワイヤで結線するワイヤボ
ンディング方法であって、少なくとも被覆ワイヤを第２
の部位に接合する際に、インナーリードに対して粗面の
接触面を備えかつ当該インナーリード面が接触面と平行
となるように位置固定溝が形成された固定手段で保持す
ることを特徴とするワイヤボンディング方法。 ４、リードフレームの載置されるボンディングステージ
表面が粗面に形成されていることを特徴とするワイヤボ
ンディング装置。[Claims] 1. A first portion formed on a semiconductor chip and a second portion on an inner lead of a lead frame are connected by a coated wire in which an insulator is coated around a metal wire. A wire bonding method comprising: bonding at least a coated wire to a second wire bonding method;
A wire bonding method characterized in that when bonding to the inner lead, the inner lead is held by a fixing means having a rough contact surface. 2. The wire bonding method according to claim 1, wherein the rough contact surface is formed by depositing diamond grains on the contact surface of the fixing means. 3. A wire bonding method in which a first portion formed on a semiconductor chip and a second portion on an inner lead of a lead frame are connected using a coated wire having an insulator coated around a metal wire, the method comprising: , at least the coated wire is
When bonded to the inner lead, the inner lead is held by a fixing means that has a rough contact surface and has position fixing grooves formed so that the inner lead surface is parallel to the contact surface. wire bonding method. 4. A wire bonding apparatus characterized in that the surface of the bonding stage on which the lead frame is placed is formed into a rough surface.
JP1098549A 1988-08-19 1989-04-18 Method and apparatus for wire bonding Pending JPH02277251A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1098549A JPH02277251A (en) 1989-04-18 1989-04-18 Method and apparatus for wire bonding
KR1019890011636A KR900004009A (en) 1988-08-19 1989-08-16 Semiconductor integrated circuit device, manufacturing or assembling method thereof and manufacturing or assembling device used in the method
US07/395,088 US5031821A (en) 1988-08-19 1989-08-16 Semiconductor integrated circuit device, method for producing or assembling same, and producing or assembling apparatus for use in the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1098549A JPH02277251A (en) 1989-04-18 1989-04-18 Method and apparatus for wire bonding

Publications (1)

Publication Number Publication Date
JPH02277251A true JPH02277251A (en) 1990-11-13

Family

ID=14222772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1098549A Pending JPH02277251A (en) 1988-08-19 1989-04-18 Method and apparatus for wire bonding

Country Status (1)

Country Link
JP (1) JPH02277251A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0528291A2 (en) * 1991-08-08 1993-02-24 Sumitomo Electric Industries, Limited Semiconductor chip module and method for manufacturing the same
JP2007504648A (en) * 2003-08-29 2007-03-01 フリースケール セミコンダクター インコーポレイテッド Capillary used for wire bonding and wire bonding of insulated wires
JP2008211258A (en) * 2008-06-06 2008-09-11 Athlete Fa Kk Bonding device for electronic component

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0528291A2 (en) * 1991-08-08 1993-02-24 Sumitomo Electric Industries, Limited Semiconductor chip module and method for manufacturing the same
EP0528291A3 (en) * 1991-08-08 1994-05-11 Sumitomo Electric Industries Semiconductor chip module and method for manufacturing the same
US5525835A (en) * 1991-08-08 1996-06-11 Sumitomo Electric Industries, Ltd. Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element
JP2007504648A (en) * 2003-08-29 2007-03-01 フリースケール セミコンダクター インコーポレイテッド Capillary used for wire bonding and wire bonding of insulated wires
JP2008211258A (en) * 2008-06-06 2008-09-11 Athlete Fa Kk Bonding device for electronic component

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