JP2004071608A - Semiconductor device manufacturing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing apparatus that can satisfactorily bond a COF tape to the electrode pad section of a semiconductor chip without damaging the joint of the chip, and to provide a method of manufacturing the device. <P>SOLUTION: The thermal expansion stress of a polyimide tape is suppressed by making a tool into a recessed shape and minimizing the contact area of the tool and the polyimid to press only the inner lead and the electrode. Immediately after bonding, the polyimide tape is quenched by blowing cooling air upon the surface of the tape from a clamper. Since a TCP (tape carrier package) having a COF (chip on film) structure using a two-layered tape carrier is used, a stress difference is generated by the difference between the coefficients of linear expansion of the substrate of the tape and the semiconductor chip when the bonding tool is pressed against the tape from the substrate side, and the occurrence of peeling in the interface between the inner lead of the tape and the electrode pad of the chip after bonding is eliminated. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, a semiconductor device manufacturing apparatus and a manufacturing method, and particularly to a so-called TCP (Tape Carrier Package) in which a semiconductor chip and a tape carrier are connected by a TAB (Tape Automated Bonding) apparatus. It is used for manufacturing a COF (Chip On Film) structure package using a layer tape carrier.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in the field of manufacturing semiconductor devices, the pitch between bonding pads of a semiconductor chip has become narrower with the miniaturization and the increase in the number of pins, and it is becoming impossible for conventional wire bonding to respond. In such a situation, as an alternative to the connection method by wire bonding, a TCP in which a semiconductor chip is mounted using a TAB tape has been developed.
[0003]
In the case of the TAB tape, the interval between the inner leads can be formed narrower than the limit pitch at which wire bonding can be performed. Therefore, the TAB tape is advantageous in narrowing the pitch between the bonding pads and can cope at a low cost. In order to cope with the narrower pitch, the COF eliminates the through hole when mounting the semiconductor chip on the TAB tape, and forms the flying inner lead, which has conventionally been extended through the through hole, on the TAB tape to achieve a narrower pitch. Is a configuration that can be realized.
[0004]
FIG. 7 shows a main part (a cross-sectional view of equipment) of a conventional bonding apparatus used for manufacturing the above-mentioned COF package. In the conventional bonding apparatus, first, the semiconductor chip 101 is placed on the bonding stage 12, and then the position of the semiconductor chip 101 is recognized by the bonding apparatus. Next, the COF tape 102 is disposed on the semiconductor chip 101, and the inner leads 102a of the COF tape 102 are passed through the polyimide from the side opposite to the pattern surface of the COF tape 102 (substrate side). Similarly, the relative position is recognized. By pressing the bonding tool 11 against both the electrode pads 101a and the inner leads 102a from the base material side of the COF tape 102, the inner leads 102a are indirectly heated and pressed against the electrode pads 101a of the semiconductor chip 101 to perform bonding. I do. Thereafter, a highly permeable protective resin is poured between the bonded semiconductor chip 101 and the COF tape 102 to hold the bonded portion, and then the resin is thermally cured to complete the semiconductor device (not shown).
[0005]
However, in the case of the above-described conventional bonding apparatus, since the bonding tool 11 directly contacts the base material of the COF tape 102, the base material of the COF tape 102 thermally expands under the influence of the heat of the bonding tool 11, and the electrode of the semiconductor chip 101 When joining with the pad 101a, there is a problem that the joining is performed while generating a large internal stress. Further, when the semiconductor chip 101 such as a liquid crystal driver has an extremely non-uniform aspect ratio such as about 20 mm × 2 mm, the surface flatness of the bonding tool 11 and the bonding stage 12 varies, and particularly, the corner portion of the semiconductor chip 101. There was a problem that the inner lead 102a and the electrode pad 101a were peeled off after bonding due to insufficient pressing.
[0006]
FIG. 8 shows the temperature profile of this junction. The temperature of the bonding portion rises rapidly due to the heat of the bonding stage 12 at 350 ° C. to 400 ° C. and the pressure of the bonding tool 11 at the pressing side of 150 ° C. to 300 ° C. After the pressing of the bonding tool 11 is completed, both the bonding tool 11 and the bonding stage 12 are retracted from the bonding point, and the temperature of the bonding portion drops rapidly. When the COF tape 102 side is Sn-plated and the electrode pad 101a side projection is Au, an Au-Sn eutectic is formed at the time of pressing and alloying proceeds, but the temperature decreases immediately after bonding, and the eutectic has a melting point of 230. It is a liquid up to about ° C., and is very unstable around the joint with respect to external force such as thermal expansion of the COF tape 102.
[0007]
FIG. 9 is a diagram schematically showing the state of the surface flatness of the contact surface between the bonding tool 11 and the bonding stage 12. The surface of the bonding tool 11 is polished under the heating conditions at the time of bonding to adjust the flatness, and when the electrode pads 101a and the inner leads 102a on the semiconductor chip 101 are pressed, the pressing is uniformly applied within the surface of the semiconductor chip 101. Processing. When joining the conventional TCP, since the inner lead 102a is directly pressed by the bonding tool 11, the thickness of the inner lead 102a is 35 μm to 15 μm, and the deformation and the height of the electrode pad 101a are about 15 μm. As a result, if the flatness was smoothly formed from the peripheral portion to the central portion from the concave surface to the convex surface and was finished in the range from -1.0 μm to 1.0 μm from the tool peripheral portion, the joining could be performed without any problem. However, when the COF tape 102 is bonded by a semiconductor manufacturing apparatus, the bonding tool 11 is pressed against a base material of the COF tape 102, for example, a polyimide surface, so that the inner leads 102a and the electrode pads 101a of the COF tape 102 are indirectly connected. Are joined. In this case, sufficient bonding cannot be obtained unless the flatness of the bonding tool 11 in the surface of the semiconductor chip 101 is high. At this time, the flatness of the bonding tool 11 is gradually convex from the periphery to the center (FIG. 9), and the flatness of the bonding stage 12 on the bonding load receiving side is also a convex surface. The peeling may occur due to insufficient pressing of the inner lead 102a and the electrode pad 101a. This is because the stress due to thermal expansion and contraction of the COF tape 102 is the largest at the long side end of the semiconductor chip 101, and further peeling occurs due to the deterioration of the pressing assembly condition margin due to the flatness between the inner lead 102a and the electrode pad 101a. The frequency and danger may increase. Therefore, intentionally producing and using the surface flatness of the bonding tool 11 with a concave surface is implemented.
[0008]
[Problems to be solved by the invention]
As described above, in the related art, between the semiconductor chip and the COF tape, a large stress exists due to a difference in linear expansion coefficient between the respective materials, and depending on the size of the semiconductor chip and the arrangement of the electrode pads, the inner leads and the electrode pads are different. However, a problem such as peeling has occurred.
[0009]
Therefore, the present invention provides a semiconductor device manufacturing apparatus and a manufacturing method capable of favorably bonding an electrode pad portion of a semiconductor chip and a COF tape without damaging the bonding of the semiconductor chip. It is an object.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, in a semiconductor device manufacturing apparatus according to the present invention, a bonding stage on which a semiconductor chip is mounted, a COF tape mounted on the stage, and electrode pads of the semiconductor chip The portion is configured to be thermocompression-bonded with a joining tool provided from above and capable of controlling the load.
[0011]
In the semiconductor device manufacturing apparatus of the present invention, the contact area of the bonding tool with the contact surface with the COF tape is reduced, and the tool contact surface that is not directly related to the bonding of the bonding tool central portion is reduced. It is possible to suppress the heat conduction from the bonding tool to the tape, minimize the intrinsic stress after bonding the electrode pad and the inner lead due to the thermal expansion of the COF tape, and stabilize the bonding.
[0012]
In addition, a cooling device is attached to a COF tape carrier clamp jig or the like of the semiconductor device manufacturing apparatus of the present invention, and the COF tape joint is cooled immediately after bonding, thereby suppressing the thermal expansion of the COF tape. The connection reliability can be improved by speeding up the solidification of the alloy layer around the joint portion from the liquid layer formation.
[0013]
Furthermore, in the semiconductor device manufacturing apparatus of the present invention, the flatness of the contact surface of the bonding tool or the bonding stage is generally ± 1.0 μm, but depending on the combination of the respective results, the flatness of the pressing surface may vary. Is not maintained, and imbalance in pressurization occurs. Therefore, by aligning the contact surfaces of the joining jig, the in-plane uniformity of the pressure is maintained, and the joining reliability is increased.
[0014]
In addition, the COF tape pressure receiving surface and the bonding tool pressing surface are stuck on both surfaces after pressing, and when the bonding tool retreats upward after heating and pressing, stress is generated to peel the COF tape upward. At this time, the peeling force can be avoided by intentionally roughening the pressure receiving surface of the COF tape.
[0015]
ADVANTAGE OF THE INVENTION According to the manufacturing apparatus and the manufacturing method of the semiconductor device of this invention, the thermal expansion by the tool of a COF tape is suppressed, each electrode in a chip is pressed uniformly, and the tape surface can be prevented from being stuck. become.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a main part of a bonding apparatus according to an embodiment of the present invention.
[0017]
For example, this bonding apparatus has a structure in which a bonding tool 11 of the present invention and a bonding stage 12 of the present invention are arranged, a clamper 13 of the present invention for fixing a COF tape 102, and a laser unit 14 in front of the clamper. .
[0018]
FIG. 2 shows a detailed example of the bonding tool 11 of the present invention. The center 11a of the bonding pressing surface of the bonding tool 11 is depressed. The bonding tool 11 has a pressing surface at the tip made of a hard substance mainly composed of vapor phase diamond or cubic boron nitride. The base material at the tip of the tool for growing diamond or boron nitride is a semiconductor chip 101 size. Ceramics cut out based on the standard are used. As one example of manufacturing the bonding tool 11, first, a ceramic cut into an appropriate size is crushed with a hard material such as a sharp diamond to cut the ceramic center portion at a predetermined size. The depth of the depression at this time is about 30 μm to 50 μm, and the depression is made based on the thickness of the base material of the COF tape 102 to be used. The bonding pressing surface area leaves a flat portion of about 200 μm to 500 μm from the outer periphery of the bonding tool to the electrode pad 101 a and the depth size of the electrode pad 101 a. After the processing of the bonding tool base ceramic, a vapor phase diamond is grown, and the pressing surface of the bonding tool 11 is polished at a high temperature at a temperature lower than the bonding temperature condition so as to be processed by the conventional bonding tool 11, so that the center from the peripheral portion is removed. It is possible to form the bonding tool 11 having a concave surface with a gentle depression in the portion and having a size recessed from the peripheral portion by 0 μm to 2.0 μm. The bonding tool is provided with an air escape hole 11c when the tape is pressed.
[0019]
This bonding apparatus supports the COF tape 102 with the clamper 13 of the present invention. This detailed example is shown in FIG. The clamper 13 is provided with a clamper cooling pipe 13a for cooling the COF tape 102 from one or both of the COF tape 102 clamp openings 13b. High-pressure air is drawn into the clamper cooling pipe 13a, and the structure is such that high-pressure air is blown onto the bonding surface on the COF tape 102 substrate side immediately after bonding.
[0020]
Next, a specific example of the bonding stage 12 of the present invention is shown in FIG. The pressing surface at the tip of the bonding stage 12 is made of a hard substance or the like mainly composed of cubic boron nitride, and the base material of this stage is made of a low expansion alloy mainly composed of Fe. The bonding stage 12 intentionally polishes the stage pressing surface so that the central portion has a gentle convex shape with respect to the peripheral portion by performing high-temperature polishing at a higher temperature side with respect to the bonding condition. Its height is aimed at a convex state of 0 μm to 2.0 μm with respect to the periphery of the stage. Thereby, the pressing surfaces of the bonding tool 11 and the bonding stage 12 are adjusted so that they can be formed in parallel at the time of bonding. Even if either of the irregularities is the upper and lower limits of 0 μm and 2.0 μm as a result, it is within the range that the uniformity within the semiconductor chip can be ensured in pressing.
[0021]
FIG. 5 is a schematic view showing a specific example of the COF tape 102 of the present invention. A roughened area 102b is provided on the COF tape 102 while avoiding the inner leads 102a. In this embodiment, as shown in FIG. 1, a laser unit 14 for laser marking is installed between a loader section of a bonding apparatus and a tape clamp section, and immediately before bonding, the laser unit 14 straightens a line on a COF tape. And roughen the tape. FIG. 5 shows the roughened region 102b as a surface, but the same effect can be obtained by drawing several straight lines. At this time, the depth of the line drawn on the COF tape 102 by the laser is about several μm to 20 μm, and the line width is about 50 μm to 100 μm. When a straight line is drawn in the long side direction of the semiconductor chip 101, the effect can be obtained by providing about three parallel straight lines on the tape in a region avoiding the inner leads 102a. In order to increase this effect, the effect of the present invention can be further improved by forming a roughened tape region 102b in a region separated from the inner lead 102a by 100 μm or more with respect to the actual bonding tool outer peripheral size 11b by making a dent or the like. Be demonstrated.
[0022]
In the manufacturing method, the COF tape 102 whose surface of the tape has been roughened by the laser unit 14 is fixed by the clamper 13, and the inner lead 102a and the electrode pad 101a are aligned. Using a bonding tool 11 and a bonding stage 12, a tool temperature of 150 ° C. to 300 ° C., a stage temperature of 350 ° C. to 400 ° C., a bonding time of 1.0 s to 2.0 s, and a bonding load to the bonding area between the inner lead 102a and the electrode pad 101a. On the other hand, bonding is performed by heating and pressing at a unit load of 0.10 × 10 ⁻³ N / μm ^{2 to} 0.15 × 10 ⁻³ N / μm ² . After the joining, the bonding tool 11 is lowered to the standby position, and at the same time, the high-pressure air is blown from the cooling pipe 13a on the clamper to complete a series of joining steps. FIG. 6 shows the temperature profile of the joint at this time. According to the present embodiment, since the quenching is performed after the joining, the time of the liquid phase state of the eutectic is shortened as compared with the conventional slow cooling, so that the joining can be surely performed.
[0023]
【The invention's effect】
As described above in detail, according to the present invention, there is provided a semiconductor device manufacturing apparatus and a manufacturing method capable of favorably joining a semiconductor chip and a COF tape without major modification of the semiconductor device manufacturing apparatus. Can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic view (a cross-sectional view of equipment) showing a main part of a bonding apparatus according to an embodiment.
FIG. 2 is a sectional view of a tip portion of a bonding tool for explaining a manufacturing process. FIG. 3 is a schematic configuration diagram of a tape clamp jig for explaining a manufacturing process. FIG. 4 is a flatness of a bonding tool and a bonding stage. FIG. 5 is a schematic diagram illustrating a specific example of a COF tape. FIG. 6 is a schematic graph illustrating a temperature profile state of a bonding portion, illustrating a manufacturing process step. FIG. 7 is a schematic view showing a main part of a bonding apparatus showing a conventional embodiment (cross-sectional view of equipment).
FIG. 8 is a schematic graph showing a temperature process state of a bonding portion, also shown for explaining a manufacturing process step. FIG. 9 is a schematic diagram of a bonding apparatus also shown for explaining a bonding tool and a bonding stage flatness. Figure [Explanation of symbols]
Reference Signs List 11 bonding tool 11a bonding tool groove and depression 11b bonding tool outer periphery 11c bonding tool air escape hole 12 bonding stage 13 clamper 13a clamper cooling pipe 13b clamper opening 14 laser unit 101 semiconductor chip 101a electrode pad (projection)
102 Tape carrier 102a Tape carrier Inner lead 102b Tape carrier roughened area

Claims (3)

A bonding stage on which the semiconductor chip is mounted;
Placing a two-layer tape carrier above the bonding stage,
A fixing jig having a function of transporting and clamping;
The electrode part inner lead part of the two-layer tape carrier is aligned with the electrode of the semiconductor chip through the two-layer tape carrier with a bonding tool provided so as to be able to control the load, and is thermocompression-bonded to the semiconductor chip. In a semiconductor device manufacturing apparatus having a function,
The bonding tool and the bonding stage are each polished at a high temperature near the heating temperature at the time of thermocompression bonding to the contact surface of the two-layer tape carrier and the back surface of the semiconductor chip so that the surface flatness becomes flat. In order to polish the surface, the bonding tool is polished such that the central portion of the long side has a flatness in a concave state of about 0 μm to a maximum of 2.0 μm. Conversely, the bonding stage has a long side. A semiconductor device characterized in that a central portion has a flatness in a convex state of about 0 μm to a maximum of 2.0 μm, and a surface is polished so that a pressing surface where the bonding tool and the bonding stage come into contact at the time of bonding is parallel. Manufacturing equipment. The shape of the contact surface of the bonding tool pressed against the two-layer tape carrier is such that the center of the bonding tool is recessed, leaving only the periphery of the electrode portion arranged at the chip end of the semiconductor chip. 2. The apparatus for manufacturing a semiconductor device according to claim 1, wherein: After thermocompression bonding the electrode part of the semiconductor chip mounted on the bonding stage to the electrode part inner lead part of the two-layer tape carrier,
2. The apparatus according to claim 1, wherein a contact surface of the bonding tool with the double-layer tape carrier is cooled.

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