JPH07169292A - Cmos sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To eliminate clock pulse leak to a signal subjected to sample-and-hold with a simple constitution by setting so that required capacity, voltage and the like of N-type and P-type MOSFET constituting a CMOS sample-and-hold circuit satisfy a specific condition. CONSTITUTION:The sample-and-hold circuit is formed out of a N-type MOSFET 1 and a P-type MOSFET2. When setting is performed so that the ratio of capacity between gate and source CGSN of a non-saturate region of the FET1 to the sum of hold capacity CH and CGSN; CGSN/(CGSN+CH) and a ratio of capacity between a gate and a source CGSN of a non-saturation region of the FET to the product of (CGSN+CH) and a difference between voltage between a gate and a source VGSN and a threshold value voltage VTH; CGSN/(CGSN+ CH)X(VGSN-VTH) are equal to the same product of a FET 2; CGPN/(CGSP+ CH)X(VGSP-VTH), clock pulse work is canceled. Therefore, a clock pulse to a signal subjected to sample-and-hold can be sliminated with a simple constitution requiring no filter and no differential amplifier and S/N is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS sample and hold circuit which can be used for sample and hold of analog signals.

[0002]

2. Description of the Related Art A sample and hold circuit for sampling and holding an analog signal such as a video signal is required to have higher precision, high speed and high S / N as the importance of digital signal processing increases. To achieve high S / N, it is necessary to minimize the sampling or clock pulses that leak into the sampled and held signal.

A conventional CMOS sample and hold circuit will be described below with reference to FIGS. 2 and 3. FIG. 2 shows the structure of a conventional CMOS sample hold circuit, and FIG. 3 shows the operating point dependence of the gate capacitance of the MOSFET. In FIG. 2, 3 is an N-type MO
In SFET, C _GN is the gate capacitance of the N-type MOSFET 3. 4 is a P-type MOSFET, C _GP is a P-type MOSFET
This is the gate capacitance of T4, in which drains and sources are commonly connected. C _H is an N-type MOSF
Hold capacitance connected to the common source of ET3 and P-type MOSFET 4.

Φ is a gate input pulse of the N-type MOSFET 3, and / φ (/ φ represents an inverted signal of φ) is a P-type MOSF.
These are the gate input pulses of ET4, and these are pulses of the same amplitude and opposite phase. Further, the gate areas of the N-type MOSFET 3 and the P-type MOSFET 4 which form the CMOS analog switch are equal.

In FIG. 3, C _OX is a capacitance determined by the gate area and the gate oxide film thickness, that is, (dielectric constant of gate oxide film) × (gate area) ÷ (gate oxide film thickness). C _OL is the capacitance determined by the overlap area of the diffusion layer forming the source or drain and the gate and the gate oxide film thickness, that is, (dielectric constant of the gate oxide film) ×
(Overlap area of diffusion layer forming source or drain and gate) / gate oxide film thickness. C _GB , C
_GS and C _GD are a gate-substrate capacitance, a gate-source capacitance, and a gate-drain capacitance, respectively.

The operation of the conventional CMOS sample and hold circuit configured as described above will be described below. First, the concept of the conventional clock pulse leak will be described. The clock pulse leak is, as shown in [Equation 1], the sampling pulse (gate input pulse) φ applied to the gate and the MO used for the analog switch.
It is considered that it is determined by the capacitance ratio of the gate capacitance C _{G of the} SFET and the hold capacitance C _H. Further, it is considered that the gate capacitance C _{G of the} MOSFET is determined by the gate area and the gate oxide film thickness, that is, C _OX in FIG.

[0007]

[Equation 1]

Therefore, when the CMOS analog switch is constructed, the clock pulse leak represented by [Equation 1] in the N-type MOSFET 3 and the clock pulse leakage represented by [Equation 1] in the P-type MOSFET 4 have the same amplitude and opposite. If the phase, that is, the relationship of [Equation 2] is satisfied, it is considered that the clock pulse leak is canceled, and the N-type MOSFET 3 and the P-type MOSFET 4 which constitute the CMOS analog switch are considered.
Of each gate area are made equal.

[0009]

[Equation 2]

[0010]

SUMMARY OF THE INVENTION Such a conventional CM
In the OS sample hold circuit, it is considered that the gate capacitance C _G of the MOSFET is determined only by the gate oxide film thickness and the size of the MOSFET, and the MOSFE as shown in FIG.
Since the operating point dependency of the gate capacitance C _G of T was not taken into consideration, the removal of the clock pulse leak is insufficient, and in order to achieve a high S / N, it is necessary to remove the clock component. Therefore, there is a problem that a filter, a dummy sample hold circuit and a differential amplifier are also required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a CMOS sample hold circuit capable of sufficiently eliminating clock pulse leakage and achieving a high S / N ratio.

[0012]

SUMMARY OF THE INVENTION A CMOS sample and hold circuit according to the present invention comprises an analog switch composed of an N-type MOSFET and a P-type MOSFET in which drains and sources are commonly connected, and an N-type MOS.
The FET and the hold capacitor connected to the common source of the P-type MOSFET.

[0013] Then, the gate-source capacitance C _GSN and hold capacitor C _H in the non-saturation region of the N-type MOSFET sum (C _GSN + C _H) for the gate-source capacitance C _GSN of non-saturation region of N-type MOSFET Ratio C _GSN / (C _GSN
+ C _H ) and the gate-source voltage V of the N-type MOSFET
Difference between threshold voltage V _TN of _GSN and N-type MOSFET (V _GS
N- V _TN ) product [C _GSN / (C _GSN + C _H )] × (V
_GSN - _VTN ) and the sum (C) of the gate-source capacitance C _GSP and the hold capacitance C _H in the non-saturation region of the P-type MOSFET.
Ratio of gate-source capacitance C _{GSP in} non-saturation region of P-type MOSFET to G _SP + C _H C _GSP / (C _GSP + C
_H ) and the gate-source voltage V _{GSP of the} P-type MOSFET
Difference between the threshold voltage V _TP of the P-type MOSFET and the threshold voltage (V _GSP −
Product with V _TP ) [C _GSP / (C _GSP + C _H )] × (V _GSP
-V _TP ) is set equal.

[0014]

According to the structure of the present invention, by considering the operating point dependency of the gate-source capacitance of the MOSFET, the leakage of the clock component of the N-type MOSFET and the P-type M.
The leak of the clock component of the OSFET can be just canceled, and the clock component can be sufficiently removed. Therefore, it is possible to eliminate the clock pulse leak to the sampled and held signal without the need for a filter, a dummy sample and hold circuit and a differential amplifier, which is optimized for IC implementation.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows C of an embodiment of the present invention.
1 illustrates a configuration of a MOS sample hold circuit.
In FIG. 1, 1 is a gate width or a gate length [Equation 3]
Is a N-type MOSFET having a threshold voltage V _TN , and C _GSN is a gate-source capacitance in the non-saturation operation region of the N-type MOSFET 1. 2 is P of the threshold voltage V _{TP with which} the gate width or the gate length satisfies [Equation 3].
In the type MOSFET, C _GSP is the gate-source capacitance in the non-saturation operation region of the P-type MOSFET 2. C _H
Is the hold capacity. V ₃ is a hold potential, and N
It becomes the source potential of the p-type MOSFET 1 and the p-type MOSFET 2. φ is a gate input pulse of the N-type MOSFET 1 having an amplitude of V ₄ , and / φ is a gate input pulse of the P-type MOSFET 2 having an amplitude of V ₅ and a phase inverted from the gate input pulse φ.

[0016]

[Equation 3]

The CM of this embodiment constructed as described above
The operation of the OS sample hold circuit will be described below. First, the concept of clock pulse leak, which is the principle of the present invention, will be described. MOSFET used for analog switch of CMOS sample and hold circuit
Operates in the non-saturated operation region when a pulse is applied to the gate and the gate is in the ON state.

Therefore, when the gate-source capacitance is C _GS , the gate-source voltage is V _GS , the threshold voltage is V _T , and the hold capacitance is C _H in the non-saturation operation region of the MOSFET, clock pulse leakage occurs. Becomes [Equation 4].

[0019]

[Equation 4]

Therefore, when the CMOS analog switch is constructed, the clock pulse leak represented by [Formula 4] in the N-type MOSFET 1 and the clock pulse leak represented by [Formula 4] in the P-type MOSFET 2 have the same amplitude and opposite. If the phase, that is, the relationship of [Equation 5] is satisfied, the clock pulse leak is canceled.

[0021]

[Equation 5]

Note that in [ _Equation 5], V _GSN is an N-type M
The gate-to-source voltage of OSFET1 (V ₄ -V ₃₎
be equivalent to. V _GSP is the gate-source voltage of the P-type MOSFET 2 and is equal to (V ₅ −V ₃ ). C in this example
In the MOS sample hold circuit, the gate width or the gate length of each of the N-type MOSFET 1 and the P-type MOSFET 2 forming the CMOS analog switch satisfies [Equation 3], that is, [Equation 5], so that the clock pulse leak is just offset.

[0023]

According to the CMOS sample and hold circuit of the present invention, the gate of the non-saturation region of the N-type MOSFET
Sum of source capacitance C _GSN and hold capacitance C _H (C _GSN +
The ratio _{C GS N / (C GSN +} C H) and the gate-source voltage of the N-type MOSFET V _GSN and the N-type MOSFET of the threshold of C _H) capacitance between the gate and the source of the non-saturation region of the N-type MOSFET for C _GSN Difference in value voltage V _TN ( _VGSN - _VTN )
The product of the _{[C GSN / (C GS N +} C H) ] × (V _GSN -
V _TN ) and the sum of the gate-source capacitance C _GSP and the hold capacitance C _H in the non-saturation region of the P-type MOSFET (C _GSP + C
Gate of the non-saturation region of the P-type MOSFET for _H )
Source-to-source capacity C _GSP ratio C _GSP / (C _GSP + C _H ) and P
_-Source voltage V _GSP of P-type MOSFET and P-type M
Difference between the threshold voltage V _TP of OSFET (V _GSP -V _TP) product of _{[C GSP / (C GSP + C} H) ] × (V _GSP -V _TP)
Since and are set equally, it is possible to sufficiently remove the clock pulse leak to the sample-held signal without using a filter or a dummy sample-hold circuit and a differential amplifier in order to remove the clock component. High S / N
Can be realized and is optimized for IC.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a CMOS sample hold circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional CMOS sample hold circuit.

FIG. 3 is a characteristic diagram showing operating point dependency of gate capacitance of MOSFET.

[Explanation of symbols]

1 N-type MOSFET 2 P-type MOSFET C _GSN Gate-source capacitance C _GSP Gate-source capacitance C _H Hold capacitance

Claims (1)

[Claims] 1. A drain and a source are connected to each other.
N-type MOSFET and P-type MOS commonly connected to each other
An analog switch composed of an FET and the N-type MOSF
W connected to the common source of ET and P-type MOSFETs
CMOS sample and hold circuit consisting of field capacitance
Between the gate and source in the non-saturation region of the N-type MOSFET
Capacity C_GSNAnd the hold capacitance C_HSum of (C_GSN+
C_HTo the non-saturation region of the N-type MOSFET for
Capacitance between source and source C_GSNRatio C_GSN/ (C_GSN+
C_H) And the gate-source voltage of the N-type MOSFET
V_GSNAnd the threshold voltage V of the N-type MOSFET _TNDifference
(V_GSN-V_TN) And [C_GSN/ (C_GSN+ C_H)]
× (V_GSN-V_TN), And between the gate and source of the non-saturation region of the P-type MOSFET
Capacity C_GSPAnd the hold capacitance C_HSum of (C_GSP+
C_H) To the non-saturated region of the P-type MOSFET
Capacitance between source and source C_GSPRatio C_GSP/ (C_GSP+
C_H) And the gate-source voltage of the P-type MOSFET
V_GSPAnd the threshold voltage V of the P-type MOSFET _TPDifference
(V_GSP-V_TP) And [C_GSP/ (C_GSP+ C_H)]
× (V_GSP-V_TP) And are set equal
CMOS sample and hold circuit.