JPS60136405A - Source follower circuit - Google Patents

Abstract

PURPOSE:To obtain a source follower circuit where the output distortion is less and degradation of the operation speed is prevented, by superposing an input signal on the drain voltage of a source follower MOSFET to suppress the variation of the input capacity due to the input signal. CONSTITUTION:A voltage follower circuit 8 to which an output VOUT of a source follower MOSFETQ1 is inputted is provided, and this output is superposed on a drain voltage source VDD, and a drain voltage VD of the FETQ1 is made equal to VDD+VIN (VIN is the input voltage), and a length L' from a drain area 3 of the FET to the pinch-off point of a channel layer 7 is equal to {2epsilonS(VD+ VS+Vth)/qN}<1/2> (VD and VS are drain and source voltages, and Vth is the threshold voltage, and qN is electron migration, and epsilonS is a constant), and this length is independent of the input voltage VIN. Consequently, floating capacities such as an overlap capacity Cgs between the gate and the source and a capacity Cgc between the gate and the channel are constant independently of the input voltage, and thus, the operation speed and the distoration characteristic are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a source follower circuit, and more particularly to a source follower circuit using MOS transistors.

Background technology MOS) A source follower circuit using a transistor is
As shown in FIG. 1, an MO8) transistor Q1 for a source follower has an input signal VIN applied to its gate, and a transistor Q1 for a current source has a reference bias ■7□ applied to its gate.
OS transistor Q, tokaranashi, source follower output V from the common connection point of the source and drain of both transistors. The configuration is such that UT is derived.

The structure of the source follower transistor Q is shown in FIG. An insulating film 4 is deposited.

A gate electrode 5 is formed between the source and drain regions on this insulating film 4.

In the normal operating state of MO8) transistor Q for source follower, an inversion layer 7 and a depletion layer 6 are formed as shown by dotted lines in the figure.

Therefore, parasitic capacitances are present between the gate of this transistor Q and each part as shown by dotted lines. C1゜gate-source overlap capacitance', Cgcrd gate-source overlap capacitance'
Capacitance between channel (inversion layer), Cu2 is capacitance between gate and back gate (substrate bias).

C and d indicate the gate-drain overlap capacitance, respectively.

Here, we will consider each capacitance change due to the input signals ① and N. Letting L' be the distance from the drain region 3 to the pinch-off point of the channel layer 7 in FIG. 2, L' is expressed by the following equation.

L'-2εs (VD Vll (VO2Vth))
/ qN...(VD, V8 is the drain,
Source voltage, ■o8 box-to-source voltage, vth hash ledge-hold voltage, button is electron mobility, and ε8 is a constant. ■ in equation (1). 8 is vos = VIN v8 (2), so by substituting equation (2) into equation (1), L"" 2E
s(Vn VIN+VB+Vth)/qN-(3), and L' changes depending on the input signal VIN. Therefore, Cryc, C(71) varies depending on the input signal VIN. In addition, since Cgi changes depending on the gate-drain voltage V□, the depletion layer in the drain region changes and the amount of charge stored in C and d changes due to this gate-drain voltage change. Become.

In this way, in the source follower circuit of FIG. 1, depending on the changes in the input signals v and N, Crtc, Cyb and C,
As d changes, the input capacitance of the source follower circuit fluctuates as a result, which leads to deterioration of distortion characteristics and a reduction in operating speed. In particular, when the source follower circuit is used as a buffer circuit in a sample-and-hold circuit or a so-called charge redistribution type D/A (digital/analog) or A/D (analog/digital) converter, the buffer output may change due to fluctuations in input capacitance. fluctuations, causing hold errors and conversion errors.

DISCLOSURE OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and therefore, the input signal is superimposed on the drain voltage of the source follower transistor to suppress the change in input capacitance caused by the input signal, thereby increasing the output voltage. It is an object of the present invention to provide a source follower circuit that eliminates distortion and prevents a decrease in operating speed.

The source follower circuit according to the present invention is configured to superimpose an input signal to the sonisph 3-follower circuit on the drain voltage source of the source follower transistor.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of one embodiment of the present invention, in which the source follower output ■ of the source follower transistor Q is shown. T.J.T.
A voltage follower circuit 8 which receives as an input is provided, and the output of this circuit 8 is superimposed on the drain voltage source VDD.

By doing this, the source follower transistor Q
The drain voltage VD of 1 is -v, = VDD + vIN' (4). Similarly, the DC voltage drop caused by the voltage follower circuit 8 and the source follower transistor Q0 is ignored. Therefore, equation (3) follows equation (4), and L/ is constant regardless of the input signal. Since the voltage between the drain and gate of transistor Q is also constant, C and d are also constant. Therefore, it is not necessary to charge and discharge the input capacitance of the source follower circuit due to changes in the input signal VIN, and it is possible to improve the operating speed and distortion characteristics.

Of course, the input of the voltage follower circuit 8 in FIG. 3 may be the input signal VIN of the source follower circuit itself, but in this case, the voltage follower circuit 8 is configured with bipolar transistor elements, and the voltage follower circuit 8 is configured with bipolar transistor elements. This eliminates fluctuations in the input capacitance of the voltage follower circuit itself due to the input signal due to the addition of the voltage follower circuit, thereby preventing a decrease in operating speed.

FIG. 4 shows another embodiment of the present invention, in which the voltage follower circuit 8 of FIG. 3 is replaced by a P-channel transistor Qs,
A source follower circuit with Q4 is used, and the source output V of transistor Qt is connected to the gate of transistor Q8.

UT is applied, and the source output of the transistor Qa is supplied to the drain of the transistor Q□. The circuit power supply VDD is applied to the drain of the transistor Q1 via the transistor Q+, and the drain of the transistor Q1 receives the input signal
□9 will be superimposed and removed. Visit,■
7□ is the gate bias of transistor Q4.
3 is a circuit diagram of another embodiment of the present invention, in which the voltage follower circuit 8 of FIG. 3 is replaced by an N-channel transistor Q5.
．． Q6 is used as a source follower circuit, and the source follower output is connected to Pch, two-channel transistors Q7. The voltage is applied to the drain of the transistor Q1 via the resistance element Q8. Then, the circuit power supply VDD (fd) is applied to the drain of transistor Q0 via transistor Q, and the drain of transistor Q is similarly supplied with the input signal ■0, which has a weight multiplied by n. become.

Effects As described above, according to the present invention, the input capacitance of the source follower circuit remains constant without changing depending on the input signal, so that the distortion characteristics are improved and the operating speed is significantly improved. . Therefore, when this source follower circuit is used as a buffer in a circuit that handles capacitor charge, such as a sample-and-hold circuit or a charge redistribution type D/A or A/D converter, the conversion output accurately corresponds to the capacitor charge. can be obtained, so the improvement in accuracy is unrealistic.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional source follower circuit, FIG. 2 is a diagram showing the structure of a transistor for the source follower of the circuit in FIG. FIG. Explanation of the symbols of the main parts Q, ... L transistor for source follower Q, ...
...Current source transistor Qa, Q5...Voltage follower transistor 8.
...Voltage follower circuit applicant Pioneer Corporation

Claims (1)

[Claims] A source follower circuit comprising means for superimposing an input signal on the drain voltage of a source follower transistor.