JPH0612638B2 - Signal transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to signal transmission such as a sample and hold circuit provided in various signal processing systems for handling line return waveform signals having a blanking period such as video signals. More particularly, the present invention relates to a signal transmission circuit having a complementary output buffer stage.

[Background technology and its problems]

Conventionally, as a signal transmission circuit of this type, for example, the first
As shown in the figure, C-MOS (Complementary Metal Oxid)
eSemiconductor) sample and hold circuits are known.

In the conventional sample and hold circuit shown in FIG. 1,
The signal input signal 1 is connected to one end of the hold capacitor 3 via the sampling gate stage 2.

The sampling gate stage 2 includes an N channel MOS transistor 2 _N and a P channel MOS transistor 2 _P.
And are connected in parallel, and each MOS transistor 2 _N , 2
Sampling pulses φ _S , _S having opposite polarities are provided to each gate of _{P as} a pair of sampling pulse input terminals 2a,
It is designed to be supplied from 2b. The sampling gate stage 2 samples the input signal S _IN supplied from the signal source (not shown) to the signal input terminal 1 according to the sampling pulses φ _S and _S.

Further, the holding capacitor 3 having one end connected to the sampling gate stage 2 has the other end grounded,
The sampling output obtained at the sampling gate stage 2 is held.

The sample-hold output obtained at the connection point between the sampling gate stage 2 and the hold capacitor 3 is supplied to the complementary output buffer stage 5 via the level shift stage 4 and output from the signal output terminal 6. It has become.

The level shift stage 4, between the ground and the driving power input terminal 7, a first quantitative flow source 4A, a N-channel MOS transistor 4 _N diode-connected, diode-connected P-channel MOS transistor 4 _P And the second
Constant current source 4B is connected in series, the connection point of the MOS transistors 4 _N and 4 _P is connected to the connection point of the sampling gate stage 2 and the hold capacitor 3, and the N channel MOS transistor 4 _N and The connection point with the first constant current 4A is the N channel MO of the output buffer stage 5.
It is connected to the gate of the S transistor 5 _N , and the connection point between the P channel MOS transistor 4 _P and the second constant current source 4B is connected to the P channel MO of the output buffer stage 5.
It is connected to the gate of the S transistor _5P . Each of the level shift stages 4 includes a diode-connected MO.
The sample-and-hold output is level-shifted by the S transistors 4 _N and 4 _P and supplied to the gates of the MOS transistors 5 _N and 5 _P of the output buffer stage 5.

The output buffer stage 5 includes an N-channel MOS transistor 5 between the drive power input terminal 7 and ground.
It comprises an _N-and P-channel MOS transistor 5 _P are connected in series, operating as a source follower complementary outputs the sample and hold output which is level-shifted by the level shift circuit 4 described above from the signal output terminal 6.

By the way, in the conventional sample and hold circuit having the above-mentioned configuration, since the level shift stage 4 is provided with the constant current sources 4A and 4B, there is a drawback that the power consumption increases. Further, in order to operate the output buffer stage 5 correctly as a complementary source follower, the constant current sources 4 are required to operate properly.
It is necessary to exactly match the current values of A and 4B. However, it is extremely difficult to exactly match the current values, and the error causes the DC offset of the output signal S _OUT obtained at the signal output terminal 6.
Further, in the output buffer stage 5, the gate of the N-channel MOS transistor 5 _N is connected to the drive power input terminal 7 via the first constant current source 4A, and the P-channel MOS transistor 5 _N is connected.
Since the gate of the transistor 5 _P is grounded through a second constant current source 4A, there is also a disadvantage that the dynamic range is limited by the potential difference occurring in the constant current sources 4A, 4B.

[Object of the Invention]

Therefore, in view of the conventional problems as described above, the present invention operates the complementary output buffer stage correctly without using the level shift stage provided with the constant current source, and further, the drift due to the DC offset or the temperature or 1 / Provides a signal transmission circuit having a novel configuration that enables high-quality signal transmission with extremely low noise.

[Outline of Invention]

In order to achieve the above-mentioned object, a signal transmission circuit according to the present invention has a signal input terminal (1) to which an input signal (S _IN ) is supplied.
0) is connected to one end of a hold capacitor (20) via a first transmission gate stage (11) that operates according to a first gate clock (φ _s ), and the connection point is a pair of different conductivity types. Connected to the pair of signal input terminals of the output buffer stage (30) composed of the transistors (30 _P , 30 _N ) of the pair of capacitors (21, 22), and the signal output terminal of the output buffer stage (30) is connected. To the connection point of each of the capacitors (20, 21, 22) via the second transmission gate stage (12) which is connected to the signal output terminal (60) and operates according to the second gate clock (φ _BLK ). The pair of signal input terminals of the output buffer stage (30) are connected to each other through the third and fourth transmission gate stages (13, 14) which operate in conjunction with each other according to the second gate clock (φ _BLK ). A pair of controls The first transmission gate stage (11) and the second to fourth transmission gate stages (12, 13, 14) are operated at different timings. The signal input terminal (10)
The input signal (S _IN ) supplied to the output terminal is output from the signal output terminal (60) via the output buffer stage (30).

〔Example〕

An embodiment of a signal transmission circuit according to the present invention will be described below in detail with reference to the drawings.

First, with respect to the basic circuit configuration and operation of the signal transmission circuit according to the present invention, this signal transmission circuit is sampled.
The case of using as a hold circuit will be described with reference to the circuit diagram of FIG. 2 and the waveform diagram of FIG.

The signal transmission circuit according to the present invention has four transmission gate stages 11, 1 as shown in the basic circuit configuration of FIG.
2, 13, 14 and three capacitors 20, 21, 22
And a complementary output buffer stage 30.

Then, the signal input terminal 10 to which the input signal S _IN is supplied
Are connected to one end of the hold capacitor 20 via the first transmission gate stage 11. Here, to the signal input terminal 10, a video signal having a repetitive blanking period at a predetermined cycle, for example, as shown in FIG.
It is supposed to be supplied as _IN .

The first transmission gate stage 11 operates at a predetermined sampling period according to the first gate clock φ _S to sample the input signal S _IN .

The hold capacitor 20 has its other end grounded, and holds the signal level V _S of the input signal S _IN sampled by the first transmission gate stage 11.

The first transmission gate stage 11 and the hold capacitor 20
The connection point with is the N-channel MOS transistor 30 _N and the P-channel M that constitute the output buffer stage 30.
A pair of capacitors 2 is provided at each gate of the OS transistor 30 _P , that is, a pair of signal input terminals of the output buffer stage 30.
1 and 22 are connected. That is, the first
The sample-and-hold output obtained at the connection point between the transmission gate stage 11 and the hold capacitor 20 of FIG.
It is supplied to 0.

The output buffer stage 30 includes N-channel MOS transistors 30 _N and P between the driving power input terminal 40 and the ground.
It comprises a channel MOS transistor 30 _P are connected in series, which operates as a source follower complementary outputs the sample-and-hold output from the signal output terminal 60 which is supplied via the pair of capacitors 21 and 22 .

Further, in the signal transmission circuit according to the present invention, the signal output terminal 60 connected to the signal output terminal of the output buffer stage 30 is provided.
Is connected to the connection point of the pair of capacitors 21 and 22 via the second transmission gate stage 12. Also, a pair of signal input terminals of the output buffer stage 30, that is, an N-channel MOS transistor 30 _N and a P-channel M
Gates of the OS transistor 30 _P third and fourth pair of control input terminal 5 via the transmission gate stages 13 and 14 of
1, 52 are connected.

The second to fourth transmission gate stages 12, 13, 14
Is an input signal S _IN supplied to the signal input terminal 10 described above.
The second gate clocks φ _{BLK having} a cycle corresponding to the blanking period of are operated in conjunction with each other. Further, the pair of control input terminals 51 and 52 are
A DC level control signal is supplied to each input terminal 51, a potential V ₁ is applied to one input terminal 51, and the other input terminal 5 is supplied.
A potential of V ₂ is applied to ₂ .

In the signal transmission circuit having the above-described configuration, the potential V ₀ of the signal output terminal 60 is the gate potentials of the N-channel MOS transistor 30 _N and the P-channel MOS transistor 30 _P constituting the output buffer stage 30 being V _N ,
And V _P, also the voltage between the gate and source V _GSP, V _GSN
Can be shown as follows.

That is, the first transmission gate stage 11 is closed and the second transmission gate stage 11 is closed.
Or, when the fourth transmission gate stages 12, 13, 14 are opened, the potential V _{1 of one} control input terminal 51 is applied to the gate of the N-channel MOS transistor 30 _N.
Since the potential V _{2 of the} other control input terminal 52 is applied to the gate of the P-channel MOS transistor 30 _P ,
The potential V ₀ of the signal output terminal 60 is given by V ₁ −V _GSN = V ₀ V ₂ + V _GSP = V ₀ , It can be shown by the following first equation. Further, in this state, since the second transmission gate stage 12 is opened,
The potential at the connection point of the pair of capacitors 21 and 22 is equal to the potential V ₀ of the signal output terminal 60. Therefore, the second to fourth transmission gate stages 12, 13, 1
4 is opened by the second gate clock φ _BLK , one of the capacitors 21 has a gate-source voltage V of the N-channel MOS transistor 30 _N.
GSN is charged, the other capacitor 22 is charged with the gate-source voltage V _{GSP of the} P-channel MOS transistor 30 _P , and then the second to fourth transmission gate stages 12, 13, 14 are closed. The gate potentials V _N and V _P of the MOS transistors 30 _N and 30 _P are maintained at V ₁ and V ₂ , respectively.

Also, the second to fourth transmission gate stages 12, 13,
14 is closed, the first transmission gate stage 11 is operated by the first gate clock φ _S , and the signal level V _S of the input signal S _IN is sampled and held in the hold capacitor 20. , 22 at the connection point V _SH changes with each sampling operation by the first transmission gate stage 11.

The signal component v _{S at} the connection point of the capacitors 20, 21, 22 is represented by V _S = V _S −V ₀ , and the gate potential V _N of each MOS transistor 30 _N , 30 _P of the output buffer stage 30 is shown. , V _P changes according to the signal component v _S. Since the gate potential V _{N of} the N-channel MOS transistor 30 _N is set to V ₁ during the blanking period as described above, V ₀ = V _N −V _GSN = V _S ...... Second formula, that is, the input signal S supplied to the signal input terminal 10
_The potential V ₀ equal to the _IN signal level V _S is applied to the signal output terminal 6
Give to 0.

Further, the P-channel MOS transistor 30 _P operates in the same manner and the potential V ₀ of V ₀ = V _S is applied to the signal output terminal 60
Will be given to.

Therefore, at the signal output terminal 60, the sample / hold output signal S whose potential V ₀ changes according to the signal level V _S of the input signal S _IN supplied to the signal input terminal 10
You can get _OUT . That is, in this signal transmission circuit, the output buffer stage 30 is opened by opening the second to fourth transmission gate stages 12, 13 and 14 every blanking period of the input signal S _IN by the second gate clock φ _BLK . Since the gate-source voltages V _GSN and V _{GSP of the} MOS transistors 30 _N and 30 _P are held in the pair of capacitors 21 and 22, the DC offset between the input and output can be eliminated, and _{Variations in} the threshold voltages V _thN and V _thP of the MOS transistors 30 _N and 30 _P and variations due to sensitivity can be eliminated, and further,
Fluctuations of the gate-source voltages V _GSN and V _GSP of the MOS transistors 30 _N and 30 _P , that is, 1 / noise can be removed, and an extremely high-quality sample-and-hold output signal S _OUT can be obtained.

The signal transmission circuit having the basic configuration shown in FIG.
For example, it can be embodied as an integrated circuit having a C-MOS structure as shown in FIG.

In the concrete embodiment shown in FIG. 4, the pair of capacitors 21 and 22 for providing the sample and hold outputs to the pair of signal input terminals of the output buffer stage 30 are N-channel MOS transistors whose drain and source are connected, respectively. 21 _N and P-channel MOS transistor 22 _P are formed by the respective gate capacitances of the N-channel MO transistor 22 _P.
The gate of the S transistor 21 _N is connected to the gate of the N channel MOS transistor 30 _N of the output buffer stage 30, and the gate of the P channel MOS transistor 22 _P is connected to the gate of the P channel MOS transistor 30 _P of the output buffer stage 30. ing.

In addition, each of the transmission gate stages 11, 12, 13, and 14 has an N-channel MOS transistor and a P-channel M, respectively.
It is configured by arranging an OS transistor in parallel.

In the first transmission gate stage 11, the first gate clocks φ _S , _S whose levels are complementarily inverted from each other from the pair of first gate clock output terminals 71, 72 are provided in each MOS.
It operates by being supplied to each gate of the transistors 11 _N and 11 _P. Similarly, the second to fourth transmission gate stages 12, 13 and 14 similarly have second gate clocks φ _BLK and ▲ ▼ whose levels are complementarily inverted from each other from the pair of second gate clock input terminals 81 and 82. Each N
Channel MOS transistors 12 _N , 13 _N , 14 _N
Each gate and each P channel MOS transistor 1
It operates by being supplied to the respective gates of 2 _P , 13 _P and 14 _P.

In this embodiment, the hold capacitor 20
Is adapted to utilize the floating regime C ₀ at the output of the first transmission gate stage 11.

Also, the specific embodiment described above is based on the third transmission gate stage 1
3 N channel MOS transistor 13 _N and 4th transmission gate stage 14 P channel MOS transistor 14
_It is possible to omit _P and simplify it as in the other embodiment shown in FIG. In the embodiment shown in FIG. 5, the N-channel MOS transistor _21N and the P-channel MOS transistor 2 which form the pair of capacitors 21 and 22 are formed.
It is adapted to secure a large channel capacity by a depletion in 2 _P.

Here, in the above-mentioned embodiment, the C-MOS structure using the MOS transistor is used, but the signal transmission circuit according to the present invention is not limited to the above-mentioned embodiment,
It is also possible to adopt a junction field effect transistor, a bipolar transistor, or a TFT structure made of polysilicon, amorphous silicon, or the like.

Further, in the above-described embodiments, the case where the signal transmission circuit according to the present invention is used as the sample and hold circuit has been described, but the signal transmission circuit according to the present invention is not limited to the sample and hold circuit. The first gate clock φ _S is set so as to keep the first transmission gate stage 11 open during the period in which the second to fourth transmission gate stages 12, 13, 14 are closed. It can be made to function as a buffer, and the first gate clock φ _S and the second gate clock φ _{BLK can be used.}
It is also possible to perform so-called double sampling by using as sampling clocks having different sample timings.

〔The invention's effect〕

As is apparent from the above description of the embodiments, in the signal transmission circuit according to the present invention, the complementary output buffer stages are operated properly without the need for a constant current source, and DC offset, 1 / noise, etc. It is possible to carry out high-quality signal transmission while keeping it extremely small, and it is possible to sufficiently achieve the initial purpose.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a configuration of a conventional sampling and holding circuit. FIG. 2 is a circuit diagram showing a basic configuration of a signal transmission circuit according to the present invention, and FIG. 3 is a waveform diagram showing an operation state when the signal transmission circuit is operated as a sample and hold circuit. . FIG. 4 is a circuit diagram showing a concrete embodiment of the signal transmission circuit according to the present invention, and FIG. 5 is a circuit diagram showing another embodiment. 10 ... Signal input terminal 11, 12, 13, 14 ... Transmission gate stage 20, 21, 22 ... Capacitor 30 ... Output buffer stage 40 ... Driving power input terminal 51, 52 ... Control input terminal 60 ... Signal output terminals 71, 72, 81, 82 ... Gate clock input terminals

Claims (1)

[Claims] 1. A holding capacitor for a signal input terminal (10) to which an input signal (S _IN ) is supplied via a first transmission gate stage (11) which operates according to a first gate clock (φ _s ). (20) is connected to one end, and the connection point is connected to a pair of transistors (3
0 _P , 30 _N ) is connected to a pair of signal input ends of an output buffer stage (30) via a pair of capacitors (21, 22), and the signal output end of the output buffer stage (30) is a signal output terminal. A second transmission gate stage (1) connected to (60) and operating in response to a second gate clock (φ _BLK ).
2) is connected to the connection points of the capacitors (20, 21, 22), and the pair of signal input terminals of the output buffer stage (30) are connected to each other according to the second gate clock (φ _BLK ). The first and second transmission gate stages (11) and (2) are connected to a pair of control input terminals (51, 52) through interlocking third and fourth transmission gate stages (13, 14). To fourth
Of the transmission gate stages (12, 13, 14) of the output buffer stage (3) are operated at different timings to input the input signal (S _IN ) supplied to the signal input terminal (10).
0) to output from the signal output terminal (60).