JPH07161913A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07161913A
JPH07161913A JP30503693A JP30503693A JPH07161913A JP H07161913 A JPH07161913 A JP H07161913A JP 30503693 A JP30503693 A JP 30503693A JP 30503693 A JP30503693 A JP 30503693A JP H07161913 A JPH07161913 A JP H07161913A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
resin
outer lead
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30503693A
Other languages
Japanese (ja)
Inventor
Shinichi Sawamoto
進一 澤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP30503693A priority Critical patent/JPH07161913A/en
Publication of JPH07161913A publication Critical patent/JPH07161913A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the outer lead of a semiconductor device by interconnecting an outer lead adjacent to the other outer lead and an insulating body. CONSTITUTION:A semiconductor pellet 2, an inner lead 3A, a bonding wire and the like are sealed with a resin-sealed body 1A which is formed in a square- like surface. The inner lead 3A is formed in one body with an outer lead 3B. The plurality outer leads 3B are arranged along each side of the resin-sealed body 1A outside the resin-sealed body 1A. The inner lead 3A is connected with the outer lead 3B adjacent to the other outer lead 3B. Thereby, the deformation of the outer lead 3B can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に、封止体の外部にこの封止体の一辺に沿って複数本の
アウターリードが配置された半導体装置に適用して有効
な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and particularly to a technique effectively applied to a semiconductor device in which a plurality of outer leads are arranged outside a sealing body along one side of the sealing body. It is about.

【０００２】[0002]

【従来の技術】論理回路システム、記憶回路システム或
はそれらの混合回路システムが塔載された半導体ペレッ
トを樹脂封止体で封止する樹脂封止型半導体装置とし
て、例えばＱＦＰ(Ｑuad Ｆlat Ｐackage)型のパッケー
ジ構造で構成された樹脂封止型半導体装置がある。2. Description of the Related Art A resin-encapsulated semiconductor device for encapsulating a semiconductor pellet on which a logic circuit system, a memory circuit system or a mixed circuit system thereof is mounted with a resin encapsulant, for example, a QFP (Quad Flat Package). 2. Description of the Related Art There is a resin-sealed semiconductor device having a mold package structure.

【０００３】前記ＱＦＰ型の樹脂封止型半導体装置は、
例えばタブのペレット塔載面上に半導体ペレットを塔載
している。半導体ペレットの外部端子(ボンディングパ
ッド)は、ボンディングワイヤを介してインナーリード
に電気的に接続される。これらの半導体ペレット、イン
ナーリード、ボンディングワイヤ等は樹脂封止体で封止
される。The QFP type resin-sealed semiconductor device is
For example, semiconductor pellets are mounted on the pellet mounting surface of the tub. The external terminal (bonding pad) of the semiconductor pellet is electrically connected to the inner lead via a bonding wire. These semiconductor pellets, inner leads, bonding wires, etc. are sealed with a resin sealing body.

【０００４】前記インナーリードは、樹脂封止体の外部
に配置されたアウターリードと一体に形成される。アウ
ターリードは、半導体ペレット、インナーリード、ボン
ディングワイヤ等を樹脂封止体で封止した後（封止工程
後）、リードフレームから切断され、ガルウィング形状
に成形される。リードフレームは、例えばＦｅ−Ｎｉ
(例えばＮｉ含有率４２又は５０［％］)合金、Ｃｕ系合
金等で形成される。The inner leads are integrally formed with outer leads arranged outside the resin encapsulant. The outer lead is formed by sealing the semiconductor pellet, the inner lead, the bonding wire, and the like with a resin encapsulant (after the encapsulation process), and then cutting the lead frame to form a gull wing shape. The lead frame is, for example, Fe-Ni.
(For example, Ni content is 42 or 50 [%]) alloy, Cu-based alloy, or the like.

【０００５】このように構成されるＱＦＰ型の樹脂封止
型半導体装置は、例えばＣＰＵボード等の実装基板の実
装面上に塔載される。The QFP type resin-encapsulated semiconductor device thus constructed is mounted on a mounting surface of a mounting board such as a CPU board.

【０００６】[0006]

【発明が解決しようとする課題】前記ＱＦＰ型の樹脂封
止型半導体装置のアウターリードは、半導体ペレットに
塔載される回路システムの高集積化に伴う多ピン化でリ
ード幅(リードピッチ)が狭くなる傾向にあり、機械的強
度が低下している。このため、実装基板に実装する時、
搬送する時、保管する時等の取り扱い時に所定の形状に
成形したアウターリードの形状(ガルウィング形状)が外
力で変形するという問題があった。このアウターリード
の変形は、特に、アウターリードのリード幅が０．２
［ｍｍ］以下になると顕著になる。The outer leads of the QFP type resin-encapsulated semiconductor device have a large lead width (lead pitch) due to the increase in the number of pins accompanying the higher integration of the circuit system mounted on the semiconductor pellet. It tends to become narrower and the mechanical strength decreases. Therefore, when mounting on the mounting board,
There is a problem that the outer lead shape (gull wing shape) formed into a predetermined shape is deformed by an external force during handling such as transportation and storage. This deformation of the outer lead is particularly caused when the lead width of the outer lead is 0.2
It becomes remarkable when it is less than [mm].

【０００７】本発明の目的は、半導体装置のアウターリ
ードの変形を防止することが可能な技術を提供すること
にある。An object of the present invention is to provide a technique capable of preventing deformation of outer leads of a semiconductor device.

【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【０００９】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

【００１０】封止体の外部にこの封止体の一辺に沿って
複数本のアウターリードが配置された半導体装置におい
て、前記アウターリードと、隣接する他のアウターリー
ドとを絶縁体で連結する。In a semiconductor device in which a plurality of outer leads are arranged outside the sealing body along one side of the sealing body, the outer lead and another adjacent outer lead are connected by an insulator.

【００１１】[0011]

【作用】上述した手段によれば、アウターリードの機械
的強度を絶縁体の機械的強度で補強することができるの
で、半導体装置を実装基板に実装する時、搬送する時、
保管する時等の取り扱い時での外力によるアウターリー
ドの変形を防止できる。According to the above-mentioned means, the mechanical strength of the outer lead can be reinforced by the mechanical strength of the insulator. Therefore, when mounting the semiconductor device on the mounting substrate or when transporting the semiconductor device,
It is possible to prevent deformation of the outer leads due to external force during handling such as storage.

【００１２】[0012]

【実施例】以下、本発明の構成について、樹脂封止型半
導体装置に本発明を適用した一実施例とともに説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a resin-sealed semiconductor device.

【００１３】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【００１４】本発明の一実施例である樹脂封止型半導体
装置の概略構成を図１(斜視図)及び図２(図１に示すＡ
−Ａ線で切った断面図)に示す。A schematic structure of a resin-encapsulated semiconductor device according to an embodiment of the present invention is shown in FIG. 1 (perspective view) and FIG. 2 (A shown in FIG. 1).
A cross-sectional view taken along line A).

【００１５】図１及び図２に示すように、樹脂封止型半
導体装置はＱＦＰ型のパッケージ１で構成される。この
樹脂封止型半導体装置は半導体ペレット２を塔載してい
る。As shown in FIGS. 1 and 2, the resin-sealed semiconductor device is composed of a QFP type package 1. In this resin-sealed semiconductor device, semiconductor pellets 2 are mounted on a tower.

【００１６】前記半導体ペレット２は例えば平面が方形
状に形成された単結晶珪素基板で形成される。半導体ペ
レット２の主面(素子形成面)には論理回路システム、記
憶回路システム或はそれらの混合回路システムが塔載さ
れ、その主面上には方形状の各辺に沿った最外周部分に
複数の外部端子(ボンディングパッド)が配置される。The semiconductor pellet 2 is formed of, for example, a single crystal silicon substrate having a rectangular plane. A logic circuit system, a memory circuit system, or a mixed circuit system thereof is mounted on the main surface (element forming surface) of the semiconductor pellet 2, and on the main surface, the outermost peripheral portion along each side of the square is formed. A plurality of external terminals (bonding pads) are arranged.

【００１７】前記半導体ペレット２の外部端子はボンデ
ィングワイヤ４を介してインナーリード３Ａに電気的に
接続される。インナーリード３Ａは、半導体ペレット２
の外周囲の外側にその各辺に沿って複数本配置される。
ボンディングワイヤ４は例えば熱圧着に超音波振動を併
用したボンディング法によりボンディングされる。The external terminals of the semiconductor pellet 2 are electrically connected to the inner leads 3A via the bonding wires 4. The inner lead 3A is the semiconductor pellet 2
A plurality of them are arranged outside each of the outer peripheries along each side thereof.
The bonding wire 4 is bonded, for example, by a bonding method using thermocompression and ultrasonic vibration.

【００１８】前記半導体ペレット２、インナーリード３
Ａ、ボンディングワイヤ４等は例えば平面が方形状に形
成された樹脂封止体１Ａで封止される。樹脂封止体１Ａ
は、低応力化を図るため例えばフェノール系硬化剤、シ
リコーンゴム及びフィラーが添加された絶縁性のエポキ
シ系樹脂で形成され、トランスファモールド法に基づい
て成形される。The semiconductor pellet 2 and the inner lead 3
A, the bonding wire 4, and the like are sealed with a resin sealing body 1A having a rectangular plane, for example. Resin sealing body 1A
Is made of an insulating epoxy resin to which a phenolic curing agent, silicone rubber and a filler are added in order to reduce the stress, and is molded based on the transfer molding method.

【００１９】前記インナーリード３Ａはアウターリード
３Ｂと一体に形成される。アウターリード３Ｂは、樹脂
封止体１Ａの外部にこの樹脂封止体１Ａの各辺に沿って
複数本配置される。このアウターリード３Ｂは、例えば
ガルウィング形状に成形される。The inner lead 3A is formed integrally with the outer lead 3B. A plurality of outer leads 3B are arranged outside the resin sealing body 1A along each side of the resin sealing body 1A. The outer lead 3B is formed in, for example, a gull wing shape.

【００２０】前記インナーリード３Ａ及びアウターリー
ド３Ｂは、図１、図２及び図３（図１に示すＢ−Ｂ線で
切った要部断面図）に示すように、絶縁体５の主面及び
この主面と対向する裏面に形成された配線で構成され
る。配線は例えば銅(Ｃｕ)膜で形成され、絶縁体５は例
えば合成樹脂膜で形成される。絶縁体５の主面に形成さ
れたインナーリード３Ａにはボンディングワイヤ４が接
続され、絶縁体５の裏面に形成されたアウターリード３
Ｂは、実装基板の実装面に形成された電極（図示せず）
に接続される。The inner lead 3A and the outer lead 3B are, as shown in FIG. 1, FIG. 2 and FIG. 3 (a sectional view taken along the line BB shown in FIG. 1), of the main surface of the insulator 5 and The wiring is formed on the back surface facing the main surface. The wiring is formed of, for example, a copper (Cu) film, and the insulator 5 is formed of, for example, a synthetic resin film. The bonding wire 4 is connected to the inner lead 3A formed on the main surface of the insulator 5, and the outer lead 3 formed on the back surface of the insulator 5
B is an electrode (not shown) formed on the mounting surface of the mounting board.
Connected to.

【００２１】前記インナーリード３Ａは、隣接する他の
インナーリード３Ａと絶縁体５で連結され、アウターリ
ード３Ｂは隣接する他のアウターリード３Ｂと絶縁体５
で連結される。つまり、インナーリード３Ａ、アウター
リード３Ｂの夫々の機械的強度は、絶縁体５の機械的強
度で補強される。The inner lead 3A is connected to another adjacent inner lead 3A by an insulator 5, and the outer lead 3B is connected to another adjacent outer lead 3B and an insulator 5.
Are connected by. That is, the mechanical strength of each of the inner lead 3A and the outer lead 3B is reinforced by the mechanical strength of the insulator 5.

【００２２】なお、図４(要部断面図)に示すように、ア
ウターリード３Ｂを従来のようにＦｅ−Ｎｉ(例えばＮ
ｉ含有率４２又は５０［％］)合金、Ｃｕ系合金等で形
成し、このアウターリード３Ｂ間に絶縁体５を設けて、
アウターリード３Ｂと隣接する他のアウターリード３Ｂ
とを絶縁体５で連結した構成にしてもよい。As shown in FIG. 4 (a cross-sectional view of the main part), the outer lead 3B is provided with Fe--Ni (for example, N
i content 42 or 50 [%]) alloy, Cu-based alloy or the like, and the insulator 5 is provided between the outer leads 3B,
Another outer lead 3B adjacent to the outer lead 3B
It may be configured such that and are connected by the insulator 5.

【００２３】このように、樹脂封止体１Ａの外部にこの
樹脂封止体３Ｂの一辺に沿って複数本のアウターリード
３Ｂが配置されたＱＦＰ型の樹脂封止型半導体装置にお
いて、前記アウターリード３Ｂと、隣接する他のアウタ
ーリード３Ｂとを絶縁体５で連結する。この構成によ
り、アウターリード３Ｂの機械的強度を絶縁体５の機械
的強度で補強することができるので、ＱＦＰ型の樹脂封
止型半導体装置を実装基板に実装する時、搬送する時、
保管する時等の取り扱い時での外力によるアウターリー
ド３Ｂの変形を防止できる。As described above, in the QFP type resin-sealed semiconductor device in which a plurality of outer leads 3B are arranged outside the resin-sealed body 1A along one side of the resin-sealed body 3B, the outer leads are provided. 3B and another adjacent outer lead 3B are connected by an insulator 5. With this configuration, the mechanical strength of the outer lead 3B can be reinforced by the mechanical strength of the insulator 5. Therefore, when the QFP type resin-sealed semiconductor device is mounted on the mounting substrate or is transported,
It is possible to prevent the outer lead 3B from being deformed by an external force during handling such as storage.

【００２４】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【００２５】例えば、本発明は、ＴＳＯＰ(Ｔin Ｓmall
Ｏut-line Ｐackage)型の樹脂封止型半導体装置に適用
することができる。[0025] For example, the present invention is, TSOP (T in S mall
O ut-line P ackage) can be applied to a type of resin-sealed semiconductor device.

【００２６】また、本発明は、セラミックスで形成され
た封止体で半導体ペレットを気密封止するセラミック封
止型半導体装置に適用することができる。The present invention can also be applied to a ceramic-sealed semiconductor device in which a semiconductor pellet is hermetically sealed with a sealing body made of ceramics.

【００２７】[0027]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【００２８】封止体の外部にこの封止体の一辺に沿って
複数本のアウターリードが配置された半導体装置におい
て、前記アウターリードの変形を防止できる。In a semiconductor device in which a plurality of outer leads are arranged outside the sealing body along one side of the sealing body, the outer leads can be prevented from being deformed.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の一実施例であるＱＦＰ型の樹脂封止
型半導体装置の概略構成を示す斜視図。FIG. 1 is a perspective view showing a schematic configuration of a QFP type resin-sealed semiconductor device that is an embodiment of the present invention.

【図２】 図１に示すＡ−Ａ線で切った断面図。FIG. 2 is a sectional view taken along line AA shown in FIG.

【図３】 図１に示すＢ−Ｂ線で切った要部断面図。FIG. 3 is a sectional view of a main part taken along line BB shown in FIG.

【図４】 本発明の変形例を示す要部断面図。FIG. 4 is a sectional view of an essential part showing a modified example of the present invention.

【符号の説明】[Explanation of symbols]

１…ＱＦＰ型パッケージ、１Ａ…樹脂封止体、２…半導
体ペレット、３Ａ…インナーリード、３Ｂ…アウターリ
ード、４…ボンディングワイヤ、５…絶縁体。1 ... QFP type package, 1A ... Resin encapsulant, 2 ... Semiconductor pellet, 3A ... Inner lead, 3B ... Outer lead, 4 ... Bonding wire, 5 ... Insulator.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 封止体の外部にこの封止体の一辺に沿っ
て複数本のアウターリードが配置された半導体装置にお
いて、前記アウターリードと、隣接する他のアウターリ
ードとが絶縁体で連結されていることを特徴とする半導
体装置。1. In a semiconductor device in which a plurality of outer leads are arranged outside a sealing body along one side of the sealing body, the outer lead and another adjacent outer lead are connected by an insulator. A semiconductor device characterized by being provided. 【請求項２】 請求項１に記載の半導体装置において、
前記アウターリードは、絶縁体の主面及びこの主面と対
向する裏面に形成された配線で構成されていることを特
徴とする半導体装置。2. The semiconductor device according to claim 1, wherein
The semiconductor device according to claim 1, wherein the outer lead is composed of a main surface of an insulator and a wiring formed on a back surface facing the main surface. 【請求項３】 請求項１に記載の半導体装置において、
前記絶縁体はアウターリード間に設けられていることを
特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the insulator is provided between outer leads.
JP30503693A 1993-12-06 1993-12-06 Semiconductor device Pending JPH07161913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30503693A JPH07161913A (en) 1993-12-06 1993-12-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30503693A JPH07161913A (en) 1993-12-06 1993-12-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07161913A true JPH07161913A (en) 1995-06-23

Family

ID=17940333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30503693A Pending JPH07161913A (en) 1993-12-06 1993-12-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07161913A (en)

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