JPH0716012B2 - Method of manufacturing thin film transistor array device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method of manufacturing a thin film transistor array device used in an active matrix liquid crystal display or the like.

[Prior art example] In a thin film transistor array including a plurality of thin film transistors (hereinafter, referred to as TFTs), a gate wire connecting the gate electrodes of the respective TFTs, and a source wire connecting the source electrodes, There is a problem that the insulating layer at the intersection of the wirings, the overlapping portion of the gate electrode and the source electrode or the overlapping portion of the gate electrode and the drain electrode causes insulation failure.

In order to solve the above problem, it has been conventionally attempted to use Ta (tantalum) for the gate wiring, and anodize this Ta to form an insulating anodic oxide film to reduce the insulation failure. .

FIG. 3 is a sectional view showing a part of the TFT array having the above structure. In the figure, 1a is a gate electrode connected to a gate wiring (not shown), which is formed of Ta. 3a is a gate insulating layer and 3b is a protective insulating layer, both of which are formed of silicon nitride or silicon oxide. Reference numeral 5a is a source wiring and 5b is a display electrode, both of which are formed of a transparent conductive layer. 5c is a source electrode, 5d
Is a drain electrode, and both are made of the same material. Reference numeral 7 is an insulating substrate, 9 is an anodized film, and 10 is a semiconductor layer.

FIG. 4 is a sectional view showing a connection terminal portion of the gate wiring of the TFT array. In the figure, 1 is a Ta gate wiring formed of Ta, which connects the gate electrode 1a of FIG. Reference numeral 3 is an insulating layer formed of the gate insulating layer or protective insulating layer, and 4 is an opening provided in the insulating layer. Reference numeral 6 denotes a connection terminal of the gate wiring 1 connected to the gate wiring 1 through the opening 4, which is formed of a metal layer.

[Problems to be Solved] The opening 4 of the insulating layer 3 formed of a silicon nitride layer or a silicon oxide layer is obtained by etching with a buffered fluorine solution. However, when etching
A crack may occur in the Ta gate wiring 1 and film peeling or the like may occur, which significantly reduces the yield. The above phenomenon
This is because Ta is used for the gate wiring.

An object of the present invention is to provide a method of manufacturing a thin film transistor array device capable of preventing film peeling or the like by protecting the Ta gate wiring when forming an opening.

[Means for Solving the Problems] A method of manufacturing a thin film transistor array device according to the present invention includes connecting a plurality of thin film transistors, a Ta (tantalum) gate wiring connecting gate electrodes of the thin film transistors, and source electrodes of the thin film transistors. Source wiring, a display electrode connected to the drain electrode of the thin film transistor, a first conductive layer connected to an end of the Ta gate wiring and resistant to a buffer hydrofluoric acid solution, the Ta gate wiring, and An insulating layer that covers the first conductive layer and is formed using silicon nitride or silicon oxide, an opening provided in the insulating layer on the first conductive layer, and the first through the opening. Second conductive layer which is connected to the conductive layer of the above and serves as a connection terminal with an external circuit, and the insulating layer is treated with a buffered hydrofluoric acid solution. The opening is formed by etching, and the patterning process of the second conductive layer is performed simultaneously with the patterning process of the source electrode, the drain electrode, the source wiring, or the display electrode.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a Ta gate wiring, 2 is a first metal layer connected to the gate wiring 1, 3 is an insulating layer made of silicon nitride or silicon oxide, and 4 is provided on the insulating layer 3. The opening 5 is a connection terminal made of the second metal layer, and is connected to the first metal layer 2 through the opening 4, thereby connecting the external circuit and the gate wiring 1.

For the first metal layer, it is preferable to use a metal that is resistant to the buffered hydrofluoric acid solution used when forming the opening 4 and is not oxidizable. For example, Cr, Mo, W
Alternatively, these alloys can be used.

Further, it is preferable from the viewpoint of simplifying the process that the connection terminal 5 is patterned at the same time when patterning the source and drain electrodes, patterning the source wiring, or patterning the display electrode. Therefore, the connection terminal 5 has source and drain electrode materials (for example, Cr, Mo, Ti, A).
l or their alloys), source wiring material (eg Cr,
It is preferable to use Mo, Ti, Al or alloys thereof or display electrode material (for example, ITO).

As described above, in the above embodiment, the first metal layer 2
Since a metal having a resistance to the buffered hydrofluoric acid solution is used for the first metal layer, a crack does not occur in the first metal layer when the opening is formed in the insulating layer 3 by the buffered hydrofluoric acid solution.

The connecting portion between the Ta gate wiring 1 and the first metal layer 2 may be reverse to that shown in FIG. 1 as shown in FIG.

According to the present invention, the first gate connected to the end of the Ta gate line is formed.
Since the conductive layer is provided, the opening of the insulating layer is provided on the first conductive layer, and the second conductive layer connected to the first conductive layer is provided through the opening, the opening is formed. When first
It becomes possible to protect the Ta gate wiring by the conductive layer. Therefore, it is possible to prevent the Ta gate wiring agent from being affected by the etching agent or the like when forming the opening, and it is possible to significantly improve the yield.

In addition, the patterning process of the second conductive layer is performed by the source electrode,
Since it is performed at the same time as the patterning process of the drain electrode, the source wiring, or the display electrode, the manufacturing process can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view showing another embodiment, and FIG. 3 is a sectional view showing a part of a thin film transistor array. 4 and 5 are sectional views showing a conventional example. 1 ... Ta gate wiring 2 ... first metal layer (first conductive layer) 3 ... insulating layer 4 ... opening 5 ... connection terminal (second conductive layer) 5a ... source wiring 5b ... Display electrode 5c Source electrode 5d Drain electrode

Claims (1)

[Claims] 1. A Ta for connecting a plurality of thin film transistors to gate electrodes of the thin film transistors.
(Tantalum) gate wiring, source wiring connecting the source electrodes of the thin film transistor, display electrode connected to the drain electrode of the thin film transistor, and buffer hydrofluoric acid solution connected to the end of the Ta gate wiring. A first conductive layer having resistance, an insulating layer formed by using silicon nitride or silicon oxide to cover the Ta gate wiring and the first conductive layer, and the insulating layer on the first conductive layer And a second conductive layer which is connected to the first conductive layer through the opening and serves as a connection terminal with an external circuit. The insulating layer is formed by using a buffered hydrofluoric acid solution. The opening is formed by etching, and the patterning step of the second conductive layer is performed to pattern the source electrode, the drain electrode, the source wiring, or the display electrode. Method of manufacturing a thin film transistor array device, which comprises carrying out ring step and at the same time.