JPH07183539A - Manufacture of thin film transistor array device - Google Patents

Abstract

PURPOSE:To lessen manufacturing processes in number by a method wherein a connection terminal patterning process is carried out at the same time when a process wherein a source electrode, a drain electrode, and a second wiring or a display electrode are patterned is carried out. CONSTITUTION:A thin film transistor array device is possessed of a first wiring 2 which connects the gate electrodes 1a of thin film transistors together, a second wiring 5a which connects the source electrodes 5c of the thin film transistors together, and a connection terminal 5 which connects a display electrode 5b connected to the drain electrode 5d of the thin film transistor to an external circuit connected to the end of the first wiring 2. A process wherein a connection terminal 6 is patterned is carried out simultaneously with a process wherein the source electrode 5c, the drain electrode 5d, and the second wiring 5a or a display electrode 5b are patterned. By this setup, a thin film transistor array device can be lessened in number of manufacturing processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array device used for an active matrix type liquid crystal display or the like.

[0002]

2. Description of the Related Art A plurality of thin film transistors (hereinafter referred to as TFTs)
Say. ), And a gate wiring to which the gate electrodes of the respective TFTs are connected and a source wiring to which the source electrodes are connected, in the thin film transistor array, the gate wiring and the source wiring are There is a problem that the insulating layer at the intersection, the overlapping portion of the gate electrode and the source electrode or the overlapping portion of the gate electrode and the drain electrode causes poor insulation.

In order to solve the above problem, the gate wiring has T
Conventionally, an attempt has been made to reduce the above-mentioned insulation failure by using a (tantalum) and anodizing this Ta to form an insulating anodic oxide film.

FIG. 3 is a sectional view showing a part of the TFT array having the above structure. In the figure, reference numeral 1a designates a gate electrode connected to a gate wiring (not shown), T
It is formed by a. 3a is a gate insulating layer and 3b is a protective insulating layer, both of which are formed of silicon nitride or silicon oxide. 5a is source wiring, 5b
Is a display electrode, both of which are formed of a transparent conductive layer. Reference numeral 5c is a source electrode and 5d is a drain electrode, both of which are made of the same material. Reference numeral 7 is an insulating substrate, 9 is an anodic oxide film, and 10 is a semiconductor layer.

FIG. 4 is a sectional view showing the connection terminal portion of the gate wiring of the TFT array. In the figure, 1 is a Ta gate wiring formed of Ta, which is connected to the gate electrode 1a of FIG. Reference numeral 3 is an insulating layer formed by the gate insulating layer or protective insulating layer, and 4 is an opening provided in this insulating layer. Reference numeral 6 denotes a connection terminal of the gate wiring 1 which is connected to the gate wiring 1 through the opening 4 and is formed of a metal layer.

[0006]

The above-mentioned conventional thin film transistor array device requires a step for forming the connection terminal 6 and has a problem of increasing the number of manufacturing steps.

An object of the present invention is to provide a method of manufacturing a thin film transistor array device which can reduce the number of manufacturing steps.

[0008]

A method of manufacturing a thin film transistor array device according to the present invention comprises a plurality of thin film transistors, a first wiring connecting gate electrodes of the thin film transistors, and source electrodes of the thin film transistors. A second electrode for connecting to the thin film transistor, a display electrode connected to the drain electrode of the thin film transistor, and a connection terminal connected to an end of the first wiring for connection with an external circuit, It is characterized in that the patterning step of the connection terminal is performed simultaneously with the patterning step of the source electrode, the drain electrode, the second wiring or the display electrode.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is Ta gate wiring, 2
Is a first metal layer connected to the gate wiring 1, 3 is an insulating layer formed of silicon nitride or silicon oxide, 4 is an opening provided in the insulating layer 3, and 5 is a second metal layer. This is a connection terminal composed of a layer and is connected to the first metal layer 2 through the opening 4 so that the external circuit and the gate wiring 1 are connected.

For the first metal layer, it is preferable to use a metal that is resistant to the buffered hydrofluoric acid solution used when forming the opening 4 and is not oxidizable, such as Cr or Mo. , W or alloys thereof can be used.

Further, the connection terminals 5 are simultaneously patterned at the time of patterning the source and drain electrodes, at the patterning of the source wiring, or at the patterning of the display electrodes, from the viewpoint of simplifying the process. Is preferred. Therefore, the connection terminal 5 has a source and drain electrode material (for example, Cr, Mo, Ti, Al, or an alloy thereof), a source wiring material (for example, Cr, Mo, Ti, Al, or an alloy thereof) or It is preferable to use a display electrode material (for example, ITO).

As described above, in the above-described embodiment, since the first metal layer 2 is made of a metal having resistance to the buffer hydrofluoric acid solution, the buffer hydrofluoric acid solution forms an opening in the insulating layer 3. When formed, the first metal layer does not crack.

Incidentally, the Ta gate wiring 1 and the first metal layer 2
The connection portion of FIG. 2 may be the reverse of that of FIG. 1 as shown in FIG.

[0015]

According to the method of manufacturing the thin film transistor array device of the present invention, the patterning process of the connection terminals is performed simultaneously with the patterning process of the source electrode and the like, so that the manufacturing process can be reduced. Become.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing another embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a part of a thin film transistor array.

FIG. 4 is a cross-sectional view showing a conventional example.

[Explanation of symbols]

 1 ... Ta gate wiring (gate wiring, first wiring) 1a ... Gate electrode 2 ... First metal layer (end wiring, first wiring) 3 ... Insulating layer 4 ... ... Aperture 5 ... Connection terminal 5a ... Source wiring (second wiring) 5b ... Display electrode 5c ... Source electrode 5d ... Drain electrode

Claims (3)

[Claims] 1. A plurality of thin film transistors, a first wiring for connecting gate electrodes of the thin film transistor, a second wiring for connecting source electrodes of the thin film transistor, and a drain electrode of the thin film transistor. A display electrode connected to the first wiring, and a connection terminal connected to an end portion of the first wiring for connecting to an external circuit. A method of manufacturing a thin film transistor array device, which is performed simultaneously with a patterning step of the drain electrode, the second wiring or the display electrode. 2. The first wiring comprises a gate wiring connected to the gate electrode and an end wiring connected to an end of the gate wiring, and the connection terminal is the end. The thin film transistor array device manufacturing method according to claim 1, wherein the thin film transistor array device is connected to partial wiring. 3. A plurality of thin film transistors, a gate wiring for connecting gate electrodes of the thin film transistor, a source wiring for connecting source electrodes of the thin film transistor, and a drain electrode of the thin film transistor. The display electrodes connected, the end wiring connected to the end of the gate wiring, the insulation covering the gate wiring and the end wiring and forming an opening on the end wiring. A layer and a connection terminal connected to the end wiring through the opening for connecting to an external circuit, and performing a patterning step of the connection terminal to the source electrode, the drain electrode, the A method of manufacturing a thin film transistor array device, which is performed simultaneously with a patterning process of a source wiring or the display electrode.