JPH05173186A - Manufacture of thin film transistor panel - Google Patents

Abstract

PURPOSE:To generate an oxide film on the surface by executing an anodic oxidation to a gate line and a capacitor line, and also, to separate an oxidation voltage applying line forming part without short-circuiting the gate line and the capacitor line. CONSTITUTION:By short-circuiting only a gate line GL to an oxidation voltage applying line 10, and short-circuiting an end part of a capacitor line CL to the gate line GL, a voltage is applied to the gate line GL from the oxidation voltage applying line 10, and also, from this gate line GL, a voltage is applied to the capacitor line CL, as well and an anodic oxidation treatment of the gate line GL and the capacitor line CL is executed, and a gate line short circuit part of the capacitor line CL is detached and separated after at least the anodic oxidation treatment is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor panel used in an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art A thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device has the following structure.

FIG. 12 is a plan view of a conventional TFT panel. This TFT panel has a plurality of gate lines GL, a plurality of data lines DL, and a plurality of thin film transistors on a transparent substrate 1 made of glass. 2 and a plurality of pixel electrodes 6 are formed.

The thin film transistor 2 is generally of an inverted stagger structure, and the thin film transistor 2 of the inverted stagger structure has the gate line G formed on the substrate 1.
With L as a gate electrode, an i-type semiconductor layer is formed on the gate insulating film 3 that covers the gate electrode.
A source / drain electrode is formed on top of this via an n-type semiconductor layer.

The gate insulating film 3 of the thin film transistor 2
Are formed on the entire surface of the substrate 1 so as to cover the gate lines GL. This gate insulating film 3 is Si N (silicon nitride)
The pixel electrode 6 is formed on the gate insulating film 3. The pixel electrode 6 is formed of a transparent conductive film made of ITO or the like, and is connected to the source electrode of the thin film transistor 2 at one end thereof.

The thin-film transistor 2 is covered with a protective insulating film 7 made of Si and formed on the entire surface of the gate insulating film 3, and the data line DL is formed on the protective insulating film 7. Has been done. The data line DL is connected to the drain electrode of the thin film transistor 2 through a contact hole provided in the protective insulating film 7. It should be noted that the protective insulating film 7 is formed with an opening that exposes each pixel electrode 6.

Further, one ends of the gate line GL and the data line DL are led out to the outside of the display area (display area of the liquid crystal display element) A within the outline shown by the chain double-dashed line in the figure, and the gate line GL A wide gate line terminal GLa is formed at the leading end, and a wide data line terminal DLa is formed at the leading end of the data line DL.

Although some TFT panels have terminals GLa of all gate lines GL formed on the same side, the number of gate lines is increased in order to increase the resolution of the liquid crystal display element. In order to secure a space between the gate line terminals, the terminals GLa of the gate lines GL are alternately formed on the opposite side as shown in FIG. The gate line terminal GLa is exposed by forming an opening in the gate insulating film 3 and the protective insulating film 7 thereabove.

Although not shown, the thin film transistor 2 and the data line DL are formed on the surface of the TFT panel.
Overcoat insulating film is formed, and the surface is subjected to orientation treatment.

In the active matrix liquid crystal display element, the display area A is surrounded by the above-mentioned TFT panel and a counter panel (not shown) having a counter electrode (transparent electrode) formed on a transparent substrate and subjected to an alignment treatment thereon. It is manufactured by adhering it through a frame-shaped sealing material and enclosing a liquid crystal between the both panels. The substrate 1 is a plurality of TFTs.
A large-sized substrate from which a panel can be taken, and each TFT panel formed on this substrate 1 is cut along the dividing line B shown by a dashed line in the figure after its manufacture or after assembling a liquid crystal display element. By doing so, it is separated into individual TFT panels.

Further, in the active matrix liquid crystal display element, in order to reduce the fluctuation of the potential held in the pixel electrode during the non-selection period, the TFT panel is made to correspond to each pixel electrode 6 and a storage capacitor is made to correspond thereto. Is provided.

In FIG. 12, CL is a capacitor line for forming the above-mentioned storage capacitor, and this capacitor line CL is a gate line G on the substrate 1.
The same metal as L (Al, Al alloys, Ta, W, Mo, etc.)
Is formed by. The capacitor line CL is formed in parallel with the gate line GL, and the gate line GL
It faces one side edge of each pixel electrode 6 arranged along the line.

The storage capacitor is composed of the capacitor line CL, the pixel electrode 6 and the gate insulating film 3 between them. This storage capacitor is used when the pixel electrode 6 is selected (when the thin film transistor 2 is turned on).
Charge) applied to the pixel electrode 6 at
The storage capacitor holds the potential of the pixel electrode 6 during the non-selected period.

Both ends of the capacitor line CL are led out to the outside of the display area A, and the respective capacitor lines CL are commonly connected by the ground line EL at both ends thereof. The ground line EL is formed on the protective insulating film 7 in parallel with the data line DL, and is connected to the end of each capacitor line CL in the contact hole provided in the protective insulating film 7 and the gate insulating film 3. ..
This ground line EL is connected to the reference potential at its terminal ELa.

By the way, in the above TFT panel,
When the gate insulating film 3 and the protective insulating film 7 have defects such as pinholes and cracks, the gate line GL and the source / drain electrodes are short-circuited in the thin film transistor portion, the gate line GL, the capacitor line CL and the data line D are short-circuited.
An interlayer short circuit such as a short circuit between both lines at an intersection with L occurs.

Therefore, in the above TFT panel, the surfaces of the gate line GL and the capacitor line CL are oxidized to generate an oxide film, and the oxide film insulates the surfaces of the gate line GL and the capacitor line CL.
The occurrence of the interlayer short circuit is prevented.

The TFT panel having the oxide film formed on the surfaces of the gate line GL and the capacitor line CL as described above is manufactured by the following manufacturing method.

First, on the substrate 1, Al, Al-based alloy, Ta
, W, Mo and the like are formed, and the metal film is patterned to form the gate line GL and the capacitor line CL, and the oxidation voltage application line 10.
The oxidation voltage application lines 10 are formed on both sides (outside of the dividing line B) of the portion to be the TFT panel. In this case, each gate line GL is patterned into a shape in which an extension portion is formed at the outer end of the terminal GLa which is alternately formed on the opposite side, and the left and right oxidation voltage application lines 10 are alternately short-circuited in this extension portion. .. Further, each capacitor line CL is patterned to have a shape in which one end thereof is alternately extended to the opposite side, and the left and right oxidation voltage applying lines 10 are alternately short-circuited in the extended portion.

Next, a voltage is applied from the oxidation voltage application line 10 to the gate line GL and the capacitor line CL to perform anodizing treatment, and an oxide film is formed on the surfaces of the gate line GL and the capacitor line CL.

In this anodic oxidation treatment, the substrate 1 is immersed in an electrolytic solution so that the gate line GL and the capacitor line CL are opposed to a counter electrode (platinum electrode) in the electrolytic solution, and these lines GL and CL are used as anodes. , The counter electrode is used as a cathode, and a voltage is applied between both electrodes. Thus, when a voltage is applied between both electrodes in the electrolytic solution, the surfaces of the gate lines GL and the capacitor lines CL, which are the anodes, undergo a chemical conversion reaction and are oxidized, and an oxide film is formed on the surfaces of these lines GL and CL. ..

The anodizing process is performed by covering the terminal GLa of the gate line GL and the portion connecting the ground line EL of the capacitor line CL with a resist mask. By doing so, the portion covered with the resist mask is not anodized because it does not come into contact with the electrolytic solution, so that the surface of the ground line connecting portion between the gate line terminal GLa and the capacitor line CL is also conductive. You can leave it as it is.

After that, a gate insulating film 3 is formed, and an i-type semiconductor layer, an n-type semiconductor layer and source / drain electrodes are formed thereon by a known method to form the thin film transistor 2.
And the pixel electrode 6 and the data line DL.
And the ground line EL are formed to complete the TFT panel.

In this state, the gate line GL and the capacitor line CL remain short-circuited to one of the left and right oxidation voltage application lines 10 at one end thereof, but the formation portion of the oxidation voltage application line 10 is After the TFT panel is manufactured or the liquid crystal display element is assembled, the substrate 1 is cut along the dividing line B to obtain T
Since it is separated from the FT panel, the gate line GL and the capacitor line CL are separated from the oxidation voltage application line 10 at this time.

[0024]

However, in the above-mentioned conventional method for manufacturing a TFT panel, both the gate line GL and the capacitor line CL are short-circuited to the same oxidation voltage application line 10, and therefore, after the TFT panel is manufactured. When the substrate 1 is broken along the dividing line B to separate the oxidation voltage application line forming portion, the gate line GL and the capacitor line CL may be short-circuited at the broken end of the substrate.

This is because the gate line GL and the capacitor line CL are formed when the substrate 1 is broken along the dividing line B.
This is because a whisker-like overhang can be formed at the broken end of the wire. Since this overhang occurs due to the metal film inside the oxide film being stretched, both lines GL and CL contact each other or one of the lines The overhang contacts the broken end face of the other line, and the gate line GL and the capacitor line CL are short-circuited.

According to the present invention, the gate line and the capacitor line are anodized to form an oxide film on the surface thereof, but the oxidation voltage application line forming portion is separated without short-circuiting the gate line and the capacitor line. Then, it aims at providing the manufacturing method of the TFT panel which can improve a manufacturing yield.

[0027]

According to a method of manufacturing a TFT panel of the present invention, a gate line, a capacitor line, and an oxidation voltage application line are provided on a substrate, and one end of the gate line is provided as the oxidation voltage application line. Forming a short circuit and shorting the end of the capacitor line to the gate line; applying a voltage from the oxidation voltage applying line to the gate line and applying a voltage from the gate line to the capacitor line And performing anodization to form an oxide film on the surfaces of the gate lines and the capacitor lines, forming the thin film transistor, the pixel electrode, the data line, and the ground line, At least the gate line short circuit portion of the capacitor line after performing the anodizing treatment Those characterized the step of disconnecting separation, in that it consists of.

[0028]

In this manufacturing method, only the gate line is short-circuited to the oxidation voltage application line, and the capacitor line is short-circuited at its end to the gate line, thereby applying a voltage from the oxidation voltage application line to the gate line and The gate line and the capacitor line are anodized by applying a voltage from the line to the capacitor line, and the gate line short-circuited portion of the capacitor line is at least anodized and then separated and separated. Only the gate line is broken when the oxidation voltage application line forming portion is separated by breaking along the disconnection line. Therefore, the whisker-shaped overhang can be formed only on the gate line, and since the end of the capacitor line is not exposed at the broken end of the substrate, the gate line and the capacitor line are short-circuited at the broken end of the substrate. There is no.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In addition, in FIGS.
Components corresponding to those of the conventional TFT panel shown in are denoted by the same reference numerals, and description of the same parts as those of the conventional TFT panel will be omitted.

In this embodiment, the TFT is manufactured by the following steps.
Manufacture panels.

[Step 1] First, as shown in FIG. 1, Al, Al based alloy, Ta, W,
A metal film made of Mo or the like is formed, and this metal film is patterned to form a plurality of gate lines GL having terminals GLa alternately formed on opposite sides and a plurality of capacitor lines CL.
And an oxidation voltage applying line 10 are formed. The oxidation voltage application line 10 has the same T-type as the conventional manufacturing method.
It is formed on both sides (outside of the dividing line B) of the portion to be the FT panel.

In this case, each gate line GL is patterned into a shape in which an extension portion extending to the outside of the dividing line B is formed at the outer end of the terminal GLa, and the left and right oxidation voltage applying lines 10 are alternately formed in this extension portion. Keep short circuited.

Each end of each capacitor line CL is connected to the side edge of the display area A and the gate line terminal GL.
The portion between a and a is patterned into a shape short-circuited to the gate line GL. In this embodiment, between the one side edge of the display area A and each gate line terminal GLa arranged on this side, and between the other side edge of the display area A and each gate line terminal GLa arranged on this side. In between, a short circuit 11 is formed which is orthogonal to the gate line GL and the capacitor line CL (the gate line GL is made of the metal film).
And formed integrally with the capacitor line CL), and both ends of each capacitor line CL are short-circuited to each gate line GL via this short circuit path 11.

[Step 2] Next, a voltage is applied from the oxidation voltage application line 10 to the gate line GL, and a voltage is also applied from the gate line GL to the capacitor line CL to carry out anodizing treatment. And an oxide film is formed on the surface of the capacitor line CL.

The above anodic oxidation treatment is performed as follows. First, as shown in FIG. 2 and FIG. 3A, the terminal GLa of the gate line GL, the connection portion of the ground line EL connected to both ends of the capacitor line CL in the subsequent process, and the short circuit 11 are formed. A resist mask 21 is formed on the capacitor line short-circuited portion so as to cover these portions.

Next, the substrate 1 is dipped in an electrolytic solution so that the gate line GL, the capacitor line CL and the short-circuit path 11 thereof face the counter electrode (platinum electrode) in the electrolytic solution, and these lines GL, CL and The short circuit 11 is used as an anode and the counter electrode is used as a cathode, and an oxidation voltage is applied between the both electrodes. The oxidation voltage is applied to the ends of the left and right oxidation voltage application lines 10 via a clip-type connector or the like. When a voltage is applied to the left and right oxidation voltage application lines 10 in this way, a voltage is applied from the oxidation voltage application line 10 to each gate line GL, and further, from these gate lines GL to each capacitor line CL via the short circuit 11. Is also applied.

When a voltage is applied between the two electrodes in the electrolytic solution, the surfaces of the gate line GL and the capacitor line CL, which are the anodes, and their short-circuit paths 11 undergo a chemical conversion reaction to be oxidized, and these surfaces are exposed. As shown in FIG. 3B, an oxide film a is formed. At this time, the surface of the portion of the oxidation voltage application line 10 immersed in the electrolytic solution is also oxidized. The oxide film a is formed on the resist mask 21.
Resist mask 2 that is generated only on the part not covered with
1 (portion not touching the electrolytic solution), that is, the gate line terminal GLa and the capacitor line CL
The ground line connection part of and the capacitor line short circuit part of the short-circuit path 11 are left with their surfaces also in a conductive state.

[Step 3] Next, as shown in FIG. 4, the short-circuited portion of each capacitor line CL with the gate line GL (capacitor line short-circuited portion of the short-circuit path 11 in this embodiment) is separated and separated.

The short-circuit portion of the capacitor line CL is separated from the gate line GL by separating the short-circuit portion from the resist mask 21 formed during the anodic oxidation process, and then the capacitor of the short-circuit path 11 is formed, as shown in FIGS. By forming a resist mask 22 that covers other portions except the line short-circuited portion, and in this state, a region of the capacitor line short-circuited portion of the short-circuit path 11 whose surface is not oxidized is removed by etching. To do. Since the etching of this region can be performed using the capacitor line CL outside this region and the oxide film a on the surface of the short circuit 11 as an etching mask, the shape accuracy of the resist mask 22 may be somewhat rough.

[Step 4] Next, as shown in FIG. 7, the thin film transistor 2, the pixel electrode 6, and the data line DL.
And a ground line EL commonly connecting the respective capacitor lines CL at both ends thereof to complete a TFT panel.

FIG. 8 is a sectional view of a thin film transistor and a pixel electrode portion of the completed TFT panel, FIG. 9 and FIG.
Reference numeral 0 is a cross-sectional view of the capacitor line common connection portion of the completed TFT panel.

The thin film transistor 2 has an inverted stagger structure, and the thin film transistor 2 has the gate line GL formed on the substrate 1 as a gate electrode, and the gate insulating film 3, the i-type semiconductor layer 4, and the n layer on the gate line GL. Type semiconductor layer 5
The source and drain electrodes S and D are formed.

This thin film transistor 2 is composed of a gate insulating film 3 made of SiN and a-Si (amorphous silicon) on a substrate 1 whose gate lines GL and capacitor lines CL are formed and whose surfaces are anodized. An i-type semiconductor layer 4, an n-type semiconductor layer 5 made of n-type impurity-doped a-Si, and a source / drain metal film made of Cr, Al-based alloy or the like are sequentially formed, and these are formed as a transistor element. After patterning to the outer shape of the region, the source / drain metal film is separated at the portion corresponding to the channel region of the i-type semiconductor layer 4 to form the source / drain electrodes S and D, and the n-type semiconductor layer 5 is formed.
Then, the portion between the source and drain electrodes S and D is removed to manufacture.

On the other hand, the pixel electrode 6 is formed by forming a transparent conductive film such as ITO on the gate insulating film (transparent film) 3 and patterning the transparent conductive film. One end of the pixel electrode 6 is the source electrode S of the thin film transistor 2.
It is connected to the source electrode S by being formed overlying. Further, the pixel electrode 6 is formed with the edge portion on the other end side facing the capacitor line CL, and a storage capacitor is formed in this portion.

On the thin film transistor 2,
A protective insulating film 7 made of Si N is formed. An opening for exposing the pixel electrode 6 and a contact hole for exposing the data line connecting portion of the drain electrode D are formed in the protective insulating film 7, and the protective insulating film 7 and the gate insulating film 3 thereunder are further formed. Then, a contact hole for exposing the ground line connecting portion of the capacitor line CL and an opening for exposing the gate line terminal GLa are formed.

The data line DL and the ground line EL commonly connecting the capacitor lines CL are formed on the protective insulating film 7, and the data line DL is formed in the contact hole formed in the protective insulating film 7 at the drain. Electrode D
And the ground line EL is connected to each capacitor line CL through a contact hole formed in the protective insulating film 7 and the gate insulating film 3.

The data line DL and the ground line EL
Is formed at the same time by forming a metal film of Al or an Al-based alloy on the protective insulating film 7 and patterning the metal film. In this case, since the surface of the ground line connecting portion of the capacitor line CL is not oxidized, the ground line EL can be conductively connected to the capacitor line CL in the contact hole.

In the TFT panel manufactured as described above, each gate line GL remains short-circuited to one of the left and right oxidation voltage applying lines 10 at the end portion on the terminal forming side. After manufacturing or after assembling the liquid crystal display element, the substrate 1 is broken along the dividing line B,
The gate line GL can be separated into individual lines by separating the formation portion of the oxidation voltage application line 10 from the TFT panel.

That is, in the method of manufacturing the TFT panel, only the gate line GL is short-circuited to the oxidation voltage application line 10 and the end of the capacitor line CL is short-circuited to the gate line GL. A voltage is applied to the gate line GL and a voltage is also applied from the gate line GL to the capacitor line CL to perform anodizing treatment of the gate line GL and the capacitor line CL. Only the gate line GL is broken when the oxidation voltage application line forming portion is separated after manufacturing or after assembling the liquid crystal display element.

For this reason, the whiskers of the broken end of the line can be extended only to the gate line GL, and the end of the capacitor line CL is not exposed at the broken end of the substrate 1. Therefore, the broken end of the substrate 1 is not exposed. At, the gate line GL and the capacitor line CL will not be short-circuited.
In addition, the gate line short circuit portion of the capacitor line CL is
After the anodic oxidation treatment, it is cut and separated.

Therefore, according to this manufacturing method, the gate line GL and the capacitor line CL are anodized to form an oxide film on the surface thereof, but the gate line GL and the capacitor line CL are short-circuited. Instead, the oxidation voltage application line forming portion can be separated to improve the manufacturing yield.

In the above embodiment, the gate line GL is used.
The anodic oxidation treatment of the capacitor line CL is performed by a method of causing a chemical conversion reaction in an electrolytic solution, but the anodic oxidation treatment may be performed by plasma oxidation that causes a chemical conversion reaction in a gas atmosphere.

Further, in the above embodiment, before the step of forming the thin film transistor 2 is started (before the formation of the gate insulating film 3 etc.).
Further, the gate line short-circuited portion of the capacitor line CL (capacitor line short-circuited portion of the short-circuit path 11 in the above-mentioned embodiment) is separated and separated, but at least the anodization treatment is performed for the separation of the gate line short-circuited portion. It may be performed at any time later.

FIG. 11 shows another embodiment of the present invention. In this embodiment, the gate line short-circuit portion of the capacitor line CL is cut and separated when the data line DL and the ground line EL commonly connecting the capacitor lines CL are formed. This separation is performed as follows. To do.

First, as shown in FIG. 11A, after forming a protective insulating film 7, the capacitor line short-circuited portion of the short-circuit path 11 is exposed on the protective insulating film 7 and the gate insulating film 3 thereunder. The opening is formed. This opening has a protective insulating film 7
Then, the gate insulating film 3 and the contact hole exposing the data line connecting portion of the drain electrode D and the contact hole exposing the ground line connecting portion of the capacitor line CL are formed at the same time.

Next, as shown in FIG. 11B, after forming a metal film 30 serving as the data line DL and the ground line EL on the protective insulating film 7, the metal film 30 is patterned to form the data. When forming the line DL and the ground line EL, the short circuit 1 is formed together with the metal film 30 in the opening.
The capacitor line short circuit part of 1 is etched and removed,
As shown in FIG. 11C, the gate line short circuit portion of the capacitor line CL is separated and separated.

According to this embodiment, since the gate line short-circuited portion of the capacitor line CL can be separated and separated by using the forming process of the data line DL and the ground line EL, the TFT panel can be efficiently manufactured.

Further, in the above embodiment, the capacitor line CL is separated and separated at the short-circuit portion with the short-circuit path 11. However, the separation of the capacitor line CL from the gate line GL is performed by the gate-line short-circuit portion of the short-circuit path 11. It is also possible to separate the part between the capacitor line and the capacitor line short-circuit portion or to remove the entire short-circuit path 11.

[0059]

According to the method of manufacturing a TFT panel of the present invention, only the gate line is short-circuited to the oxidation voltage application line and the end of the capacitor line is short-circuited to the gate line, so that the oxidation voltage application line is changed to the gate line. A voltage is applied and a voltage is also applied from this gate line to the capacitor line to anodize the gate line and the capacitor line, and the gate line short circuit portion of the capacitor line is cut and separated at least after the anodizing process. Therefore, only the gate line is broken when the substrate is broken along the dividing line to separate the oxidation voltage application line forming portion. Therefore, the beard-like overhang can be done only on the gate line,
Further, since the end of the capacitor line is not exposed at the broken end of the substrate, the gate line and the capacitor line are not short-circuited at the broken end of the substrate.

Therefore, according to the present invention, although the gate line and the capacitor line are anodized to form an oxide film on the surface thereof, the oxidation voltage application line is not short-circuited between the gate line and the capacitor line. By separating the formation part, the manufacturing yield of the TFT panel can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a state where gate lines and capacitor lines are formed on a substrate showing an embodiment of the present invention.

FIG. 2 is a partial plan view showing a method of anodizing a gate line and a capacitor line.

3 is a sectional view taken along line III-III in FIG. 2 showing a state before anodizing and a state after anodizing.

FIG. 4 is a plan view showing a state in which a gate line short circuit portion of a capacitor line is separated and separated.

FIG. 5 is a partial plan view showing a method of separating and separating a gate line short circuit portion of a capacitor line.

6 is a sectional view taken along line VI-VI of FIG.

FIG. 7 is a plan view of the completed TFT panel.

FIG. 8 is a cross-sectional view of a thin film transistor and a pixel electrode portion of a TFT panel.

FIG. 9 is a cross-sectional view of a capacitor line common connection portion of a TFT panel.

10 is a cross-sectional view taken along line XX of FIG.

FIG. 11 is a process diagram for separating a gate line short circuit portion of a capacitor line according to another embodiment of the present invention.

FIG. 12 is a plan view of a conventional TFT panel.

[Explanation of symbols]

1 ... Substrate, 2 ... Thin film transistor, GL ... Gate line, CL ... Capacitor line, a ... Oxide film, 3 ... Gate insulating film, 4 ... i-type semiconductor layer, 5 ... N-type semiconductor layer, S ... Source electrode, D ... Drain electrode, DL ... Data line, 6
... Pixel electrode, 7 ... Protective insulating film, 10 ... Oxidation voltage application line, 11 ... Short circuit path, EL ... Ground line, A ... Display area,
B ... Broken line.

Claims (1)

[Claims] 1. A transparent substrate having a plurality of gate lines alternately formed on opposite sides, a plurality of data lines, a plurality of thin film transistors, a plurality of pixel electrodes, and the pixel electrodes. A method of manufacturing a thin film transistor panel, comprising: a plurality of capacitor lines that form a storage capacitor; and a ground line that commonly connects the capacitor lines, wherein the gate line, the capacitor line, and an oxidation voltage are provided on the substrate. And a step of forming an applied line by short-circuiting one end of the gate line to the oxidation voltage application line and short-circuiting an end of the capacitor line to the gate line, and from the oxidation voltage application line to the gate line. A voltage is applied to this capacitor line as well as a voltage from this gate line to the anode. Process for forming an oxide film on the surface of the gate line and the capacitor line, forming the thin film transistor, the pixel electrode, the data line, and the ground line, at least the anode A method of manufacturing a thin film transistor panel, which comprises a step of separating and separating a gate line short circuit portion of the capacitor line after performing an oxidation process.