JPH0715911B2 - High frequency transistor manufacturing method - Google Patents
High frequency transistor manufacturing methodInfo
- Publication number
- JPH0715911B2 JPH0715911B2 JP59108078A JP10807884A JPH0715911B2 JP H0715911 B2 JPH0715911 B2 JP H0715911B2 JP 59108078 A JP59108078 A JP 59108078A JP 10807884 A JP10807884 A JP 10807884A JP H0715911 B2 JPH0715911 B2 JP H0715911B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- emitter
- protective film
- electrode
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title description 8
- 230000001681 protective effect Effects 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は、高周波トランジスタの製造方法に関し、より
詳しくは、ベース電極オーミックコンタクト部とエミッ
タ領域との間隔を短縮することで高周波特性を改善する
高周波トランジスタの製造方法。TECHNICAL FIELD The present invention relates to a method of manufacturing a high frequency transistor, and more particularly, to improving high frequency characteristics by shortening a distance between an ohmic contact portion of a base electrode and an emitter region. Method for manufacturing high frequency transistor.
（ロ）従来技術及びその課題 高周波トランジスタの高周波特性の改善策として、ベー
ス面積の縮小化及びベース電極オーミックコンタクト部
とエミッタ領域との間隔を短縮するなどの方法があり、
これらの方法によると必然的に、ベース電極とエミッタ
電極との間隔を短縮する必要がある。(B) Prior art and its problems As a measure for improving the high-frequency characteristics of a high-frequency transistor, there are methods such as reducing the base area and shortening the distance between the base electrode ohmic contact portion and the emitter region.
According to these methods, it is necessary to shorten the distance between the base electrode and the emitter electrode.
従来の方法のように、アルミニウムなどの導電層を形成
した後、フォトエッチングにより各電極を形成しようと
しても、前記ベース電極とエミッタ電極との間隔を短縮
するようにエッチングすると、この両電極を完全に絶縁
分離することが技術的に困難であるため、電極間ショー
トを引き起こす原因となる。その結果、製品としての歩
留り及び信頼性の低下を招くことになるという問題を生
じる。Even if each electrode is formed by photo-etching after forming a conductive layer such as aluminum as in the conventional method, if both electrodes are completely removed by etching so as to shorten the interval between the base electrode and the emitter electrode. It is technically difficult to insulate and separate the electrodes, which causes a short circuit between the electrodes. As a result, there arises a problem that yield and reliability of the product are deteriorated.
そのため、エッチングする際、前記両電極の間隔を予め
完全に絶縁分離できる範囲に設定しておかねばならない
ので、必然的に高周波特性の低下を招いていた。Therefore, during etching, the distance between the two electrodes must be set in advance so that they can be completely insulated and separated, which inevitably leads to deterioration of high-frequency characteristics.
本発明は、特別なマスク合わせ精度を必要とせず、更に
厳密なエッチング精度を必要とせずにベース電極オーミ
ックコンタクト部とエミッタ領域との距離を短縮すべく
ベース電極とエミッタ電極とを近接した状態で容易に絶
縁分離し、高い高周波特性を有する高周波トランジスタ
の製造方法を提供することを目的とする。The present invention does not require special mask alignment accuracy, and does not require strict etching accuracy, so that the base electrode and the emitter electrode are close to each other in order to shorten the distance between the base electrode ohmic contact portion and the emitter region. It is an object of the present invention to provide a method for manufacturing a high frequency transistor which is easily insulated and separated and has high frequency characteristics.
（ハ）課題を解決するための手段 本発明は、半導体基板にベース領域とエミッタ領域を拡
散形成する工程と、 この半導体基板表面にシリコン酸化膜を成長形成させた
後、前記ベース領域とエミッタ領域との境界を覆うよう
に上記酸化膜を残しつつベース及びエミッタコンタクト
ホールを同時に開孔する工程と、 前記シリコン酸化膜及び前記ベース及びエミッタコンタ
クトホールの上に第一の導電層を被着する工程と、 この第一の導電層と選択エッチング可能な特性を有する
保護膜を前記第一の導電層の表面に形成する工程と、 前記ベース又はエミッタコンタクトホールの上にそれよ
り大きい面積のレジストパターンを前記保護膜の表面に
形成し、このレジストをマスクとして前記保護膜を選択
エッチングする工程と、 前記選択エッチングされた保護膜をマスクとし、この保
護膜がオーバハング状態となるように、かつ半導体基板
表面部分を露出させるように第一の導電層を選択エッチ
ングして、ベース又はエミッタ電極を形成する工程と、 ベース又はエミッタ電極が形成された半導体基板表面
に、上記エッチングした保護膜をマスクとして第二の導
電層を被着することによりエミッタ又はベース電極を形
成する工程とを具備したことを特徴とする高周波トラン
ジスタの製造方法に係る。(C) Means for Solving the Problem The present invention is directed to a step of diffusing and forming a base region and an emitter region in a semiconductor substrate, and a step of growing a silicon oxide film on the surface of the semiconductor substrate and then forming the base region and the emitter region. A step of simultaneously forming a base and an emitter contact hole while leaving the oxide film so as to cover the boundary with the step of depositing a first conductive layer on the silicon oxide film and the base and the emitter contact hole. A step of forming a protective film having a property capable of being selectively etched with the first conductive layer on the surface of the first conductive layer, and forming a resist pattern having a larger area on the base or emitter contact hole. Forming on the surface of the protective film, selectively etching the protective film using the resist as a mask, and the selective etching Using the protective film formed as a mask, the first conductive layer is selectively etched so that the protective film is in an overhang state and the semiconductor substrate surface portion is exposed, and a base or emitter electrode is formed, And a step of forming an emitter or base electrode by depositing a second conductive layer on the surface of the semiconductor substrate on which the base or emitter electrode is formed, using the above-mentioned etched protective film as a mask. The present invention relates to a method for manufacturing a transistor.
（ニ）発明の作用 本発明では、高周波トランジスタの製造において、ベー
ス電極とエミッタ電極とを別工程において形成し、かつ
先に形成した電極上にそれと選択エッチング可能な特性
を有する保護膜を設けベース又はエミッタ電極と保護膜
との選択エッチングを行ってその電極のオーバハング状
態を得られるから、ベース電極とエミッタ電極とを近接
した状態で良好な絶縁性を保たせ分離することができ
る。(D) Effect of the Invention In the present invention, in the manufacture of a high-frequency transistor, a base electrode and an emitter electrode are formed in separate steps, and a protective film having a property capable of being selectively etched with the base electrode is formed on the electrode formed in advance. Alternatively, since the emitter electrode and the protective film are selectively etched to obtain an overhang state of the electrode, the base electrode and the emitter electrode can be separated in the state of being close to each other while maintaining good insulation.
（ホ）実施例 第１図は、本発明に係る高周波トランジスタの製造方法
の実施例を略示した断面説明図である。(E) Example FIG. 1 is a schematic sectional view showing an example of a method for manufacturing a high-frequency transistor according to the present invention.
（ａ）半導体基板10をベース11、エミッタ12を拡散する
と共にシリコン酸化膜20を成長させる。(A) The semiconductor substrate 10 is diffused into the base 11 and the emitter 12, and the silicon oxide film 20 is grown.
（ｂ）前記シリコン酸化膜の表面にレジスト50を塗布し
た後、ベース11及びエミッタ12のコンタクトホールを形
成する部分に相当する前記レジスト50をベース−エミッ
タ領域の境界を覆うように最小限の幅でパターニング
し、マスクとして前記シリコン酸化膜を選択エッチング
することにより、ベース11及びエミッタ12のコンタクト
ホールを同時に形成する。(B) After the resist 50 is applied to the surface of the silicon oxide film, the resist 50 corresponding to the portion where the contact holes of the base 11 and the emitter 12 are formed has a minimum width to cover the base-emitter region boundary. Then, the silicon oxide film is selectively etched as a mask to form contact holes for the base 11 and the emitter 12 at the same time.
（ｃ）前記レジスト50を除去した後、シリコン酸化膜20
及び前記ベース11及びエミッタ12のコンタクトホールの
上にアルミニウム等の第一の導電層30を蒸着する。次に
この表面に前記第一の導電層30と選択エッチング可能な
特性を有する、例えば窒化シリコン膜、二酸化シリコン
膜等からなる保護膜40をCVD法等により気相成長させ
る。(C) After removing the resist 50, the silicon oxide film 20
And, a first conductive layer 30 made of aluminum or the like is deposited on the contact holes of the base 11 and the emitter 12. Then, a protective film 40, which is made of, for example, a silicon nitride film, a silicon dioxide film, or the like, which has the property of being selectively etched with the first conductive layer 30, is vapor-phase grown on this surface by a CVD method or the like.
（ｄ）前記保護膜40の表面に新たなレジスト51を塗布し
て、前記ベースコンタクトホール上にそれより大きい面
積となるように前記レジスト51をパターニングする。(D) A new resist 51 is applied on the surface of the protective film 40, and the resist 51 is patterned so as to have a larger area on the base contact hole.
（ｅ）前記レジスト51をマスクとして保護膜40を選択エ
ッチングする。保護膜40はエミッタ上にd1の距離を開孔
している（第１図（Ｆ）参照）。次に前記保護膜40をマ
スクとして、この保護膜40がオーバハング状態となるよ
うに、かつ半導体基板10の表面部分を露出させるように
前記第一の導電層30を選択エッチングすることにより、
ベース電極30aを形成すると共にエミッタ12のコンタク
トホールを開孔する。(E) The protective film 40 is selectively etched using the resist 51 as a mask. The protective film 40 has an opening d1 on the emitter (see FIG. 1 (F)). Next, by using the protective film 40 as a mask, by selectively etching the first conductive layer 30 such that the protective film 40 is in an overhang state and the surface portion of the semiconductor substrate 10 is exposed,
The base electrode 30a is formed and the contact hole of the emitter 12 is opened.
（ｆ）前記レジスト51を除去した半導体基板表面に、上
記エッチングした保護膜40をマスクとして第二の導電層
60を蒸着することにより、エミッタ電極60aを形成す
る。このとき前記保護膜40のオーバハングによりベース
電極30aとエミッタ電極60aとはd2分（第１図（ｆ）参
照）絶縁分離されている。(F) A second conductive layer is formed on the surface of the semiconductor substrate from which the resist 51 has been removed, using the etched protective film 40 as a mask.
The emitter electrode 60a is formed by depositing 60. At this time, the base electrode 30a and the emitter electrode 60a are insulated and separated by d2 (see FIG. 1 (f)) due to the overhang of the protective film 40.
尚、上述の実施例において、コンタクトホールの形成は
前述の方法に限定されず、前記（ｃ）の工程以前にベー
ス11及びエミッタ12の両コンタクトホールが開孔できる
方法であればよい。Incidentally, in the above-mentioned embodiment, the formation of the contact holes is not limited to the above-mentioned method, and any method can be used as long as both the contact holes of the base 11 and the emitter 12 can be opened before the step (c).
また、上述の実施例では、まずベース電極30aを形成し
た後、エミッタ電極60aを形成しているが、その逆であ
ってもよい。Further, in the above-described embodiment, the base electrode 30a is first formed, and then the emitter electrode 60a is formed, but the reverse may be possible.
更に、上述した実施例では、第一及び第二の導電層にア
ルミニウムを使用しているが、本発明においては、これ
に限定されず、例えば多結晶シリコン等であってもよ
い。Furthermore, although aluminum is used for the first and second conductive layers in the above-described embodiments, the present invention is not limited to this and may be, for example, polycrystalline silicon.
（ヘ）発明の効果 本発明によれば、ベース電極とエミッタ電極のうちいず
れか一方を形成した後、もう一方を形成するときに、先
に形成した電極上にそれと選択エッチング可能な特性を
示す物質を保護膜として用いて後の電極を形成するの
で、ベース電極とエミッタ電極とを近接状態で絶縁分離
を容易に且つ良好に成し得ることができる。(F) Effect of the Invention According to the present invention, when one of the base electrode and the emitter electrode is formed and then the other is formed, a property capable of being selectively etched with the electrode formed earlier is exhibited. Since the later electrode is formed by using the substance as the protective film, it is possible to easily and satisfactorily perform the insulation separation in the state where the base electrode and the emitter electrode are close to each other.
従って、ベース電極オーミックコンタクト部とエミッタ
領域間の距離を短縮しベース拡がり抵抗の減少を図るこ
とができ、更にベース面積の縮小化が可能となる結果、
接合容量を減少させることができ、トランジスタの高周
波特性を向上させることができる。Therefore, the distance between the base electrode ohmic contact portion and the emitter region can be shortened, the base spreading resistance can be reduced, and the base area can be further reduced.
The junction capacitance can be reduced, and the high frequency characteristics of the transistor can be improved.
第１図は、本発明の製造方法の実施例を略示した断面説
明図である。 10……半導体基板、11……ベース、12……エミッタ、20
……シリコン酸化膜、30……第一の導電層、30a……ベ
ース電極、40……保護膜、50,51……レジスト、60……
第二の導電層、60a……エミッタ電極FIG. 1 is a sectional explanatory view schematically showing an embodiment of the manufacturing method of the present invention. 10 …… Semiconductor substrate, 11 …… Base, 12 …… Emitter, 20
...... Silicon oxide film, 30 …… first conductive layer, 30a …… base electrode, 40 …… protective film, 50,51 …… resist, 60 ……
Second conductive layer, 60a ... Emitter electrode
Claims (1)
拡散形成する工程と、 この半導体基板表面にシリコン酸化膜を成長形成させた
後、前記ベース領域とエミッタ領域との境界を覆うよう
に上記酸化膜を残しつつベース及びエミッタコンタクト
ホールを同時に開孔する工程と、 前記シリコン酸化膜及び前記ベース及びエミッタコンタ
クトホールの上に第一の導電層を被着する工程と、 この第一の導電層と選択エッチング可能な特性を有する
保護膜を前記第一の導電層の表面に形成する工程と、 前記ベース又はエミッタコンタクトホールの上にそれよ
り大きい面積のレジストパターンを前記保護膜の表面に
形成し、このレジストをマスクとして前記保護膜を選択
エッチングする工程と、 前記選択エッチングされた保護膜をマスクとし、この保
護膜がオーバハング状態になるように、かつ半導体基板
表面部分を露出させるように第一の導電層を選択エッチ
ングして、ベース又はエミッタ電極を形成する工程と、 ベース又はエミッタ電極が形成された半導体基板表面
に、上記エッチングした保護膜をマスクとして第二の導
電層を被着することによりエミッタ又はベース電極を形
成する工程とを具備したことを特徴とする高周波トラン
ジスタの製造方法。1. A step of diffusing and forming a base region and an emitter region in a semiconductor substrate, a step of growing a silicon oxide film on the surface of the semiconductor substrate, and then performing the oxidation so as to cover a boundary between the base region and the emitter region. A step of simultaneously opening a base and an emitter contact hole while leaving a film; a step of depositing a first conductive layer on the silicon oxide film and the base and emitter contact hole; and Forming a protective film having a property capable of selective etching on the surface of the first conductive layer, and forming a resist pattern having a larger area on the surface of the base or emitter contact hole on the surface of the protective film, A step of selectively etching the protective film using the resist as a mask; and a step of using the selectively etched protective film as a mask. Forming a base or emitter electrode by selectively etching the first conductive layer so that the protective film is in an overhang state and exposing the surface portion of the semiconductor substrate; and a semiconductor having the base or emitter electrode formed And a step of forming a second conductive layer on the surface of the substrate by using the etched protective film as a mask to form an emitter or base electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59108078A JPH0715911B2 (en) | 1984-05-28 | 1984-05-28 | High frequency transistor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59108078A JPH0715911B2 (en) | 1984-05-28 | 1984-05-28 | High frequency transistor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60251627A JPS60251627A (en) | 1985-12-12 |
| JPH0715911B2 true JPH0715911B2 (en) | 1995-02-22 |
Family
ID=14475312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59108078A Expired - Fee Related JPH0715911B2 (en) | 1984-05-28 | 1984-05-28 | High frequency transistor manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0715911B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4067724A (en) * | 1975-09-13 | 1978-01-10 | Bayer Aktiengesellschaft | N-(1,2,4-Triazin-5-on-4-yl)-glycines and herbicidal compositions |
| JPS5429987A (en) * | 1977-08-10 | 1979-03-06 | Hitachi Ltd | Forming method of selective vapor-deposition film |
-
1984
- 1984-05-28 JP JP59108078A patent/JPH0715911B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60251627A (en) | 1985-12-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |