JPH0715889B2 - 多結晶性／単結晶性シリコン界面における界面酸化物のコントロール法及びそれから導かれる装置 - Google Patents

多結晶性／単結晶性シリコン界面における界面酸化物のコントロール法及びそれから導かれる装置

Info

Publication number
JPH0715889B2
JPH0715889B2 JP4103410A JP10341092A JPH0715889B2 JP H0715889 B2 JPH0715889 B2 JP H0715889B2 JP 4103410 A JP4103410 A JP 4103410A JP 10341092 A JP10341092 A JP 10341092A JP H0715889 B2 JPH0715889 B2 JP H0715889B2
Authority
JP
Japan
Prior art keywords
substrate
silicon
polycrystalline
interface
single crystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4103410A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05129206A (ja
Inventor
ロバート・キンバル・クツク
ロナルド・ウイリアム・ネツパー
スボドー・ケーシヤブ・クルカルニ
ラツセル・チヤールズ・ランジユ
ポール・アンドルー・ロンスハイム
セシヤドリ・スツバナ
マーヌ・ジヤムナダス・テジユワニ
ボブ・ホン・ユン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH05129206A publication Critical patent/JPH05129206A/ja
Publication of JPH0715889B2 publication Critical patent/JPH0715889B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6508—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H10P32/1412—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only through the applied layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/017—Clean surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
JP4103410A 1991-06-05 1992-04-23 多結晶性／単結晶性シリコン界面における界面酸化物のコントロール法及びそれから導かれる装置 Expired - Lifetime JPH0715889B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/710,498 US5194397A (en) 1991-06-05 1991-06-05 Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface
US710498 1991-06-05

Publications (2)

Publication Number Publication Date
JPH05129206A JPH05129206A (ja) 1993-05-25
JPH0715889B2 true JPH0715889B2 (ja) 1995-02-22

Family

ID=24854290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4103410A Expired - Lifetime JPH0715889B2 (ja) 1991-06-05 1992-04-23 多結晶性／単結晶性シリコン界面における界面酸化物のコントロール法及びそれから導かれる装置

Country Status (3)

Country Link
US (1) US5194397A (https=)
EP (1) EP0519854A2 (https=)
JP (1) JPH0715889B2 (https=)

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JP2892170B2 (ja) * 1990-07-20 1999-05-17 株式会社東芝 熱処理成膜方法
US5420050A (en) * 1993-12-20 1995-05-30 United Technologies Corporation Method of enhancing the current gain of bipolar junction transistors
JP2705592B2 (ja) * 1994-10-14 1998-01-28 日本電気株式会社 半導体装置の製造方法
EP0712151A1 (de) * 1994-11-11 1996-05-15 Siemens Aktiengesellschaft Verfahren zur Einstellung der Stromverstärkung von Polyemitter-Bipolartransistoren
US5489553A (en) * 1995-05-25 1996-02-06 Industrial Technology Research Institute HF vapor surface treatment for the 03 teos gap filling deposition
JP3545503B2 (ja) * 1995-08-11 2004-07-21 株式会社日立製作所 半導体集積回路装置の製造方法
US5913103A (en) * 1997-05-13 1999-06-15 Integrated Device Technology, Inc. Method of detecting metal contaminants in a wet chemical using enhanced semiconductor growth phenomena
US7030038B1 (en) * 1997-07-31 2006-04-18 Texas Instruments Incorporated Low temperature method for forming a thin, uniform oxide
KR100379136B1 (ko) * 1998-10-02 2003-04-08 인터내셔널 비지네스 머신즈 코포레이션 반도체 소자 형성 방법과 반도체 소자
US6194736B1 (en) 1998-12-17 2001-02-27 International Business Machines Corporation Quantum conductive recrystallization barrier layers
US6429101B1 (en) 1999-01-29 2002-08-06 International Business Machines Corporation Method of forming thermally stable polycrystal to single crystal electrical contact structure
US6259129B1 (en) 1999-04-20 2001-07-10 International Business Machines Corporation Strap with intrinsically conductive barrier
US6236077B1 (en) 1999-04-20 2001-05-22 International Business Machines Corporation Trench electrode with intermediate conductive barrier layer
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
TW468212B (en) * 1999-10-25 2001-12-11 Motorola Inc Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6392257B1 (en) * 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
KR20030011083A (ko) 2000-05-31 2003-02-06 모토로라 인코포레이티드 반도체 디바이스 및 이를 제조하기 위한 방법
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6590236B1 (en) 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
WO2002009187A2 (en) * 2000-07-24 2002-01-31 Motorola, Inc. Heterojunction tunneling diodes and process for fabricating same
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6559471B2 (en) 2000-12-08 2003-05-06 Motorola, Inc. Quantum well infrared photodetector and method for fabricating same
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US20020096683A1 (en) * 2001-01-19 2002-07-25 Motorola, Inc. Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US20040132317A1 (en) * 2001-03-10 2004-07-08 Per Morgen Method for oxidation of silicon substrate
WO2002082551A1 (en) 2001-04-02 2002-10-17 Motorola, Inc. A semiconductor structure exhibiting reduced leakage current
US6459104B1 (en) * 2001-05-10 2002-10-01 Newport Fab Method for fabricating lateral PNP heterojunction bipolar transistor and related structure
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6992321B2 (en) 2001-07-13 2006-01-31 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials
US20030010992A1 (en) * 2001-07-16 2003-01-16 Motorola, Inc. Semiconductor structure and method for implementing cross-point switch functionality
US6531740B2 (en) 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
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US6855992B2 (en) * 2001-07-24 2005-02-15 Motorola Inc. Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
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US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US20030036217A1 (en) * 2001-08-16 2003-02-20 Motorola, Inc. Microcavity semiconductor laser coupled to a waveguide
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US6916717B2 (en) 2002-05-03 2005-07-12 Motorola, Inc. Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate
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Also Published As

Publication number Publication date
JPH05129206A (ja) 1993-05-25
EP0519854A2 (en) 1992-12-23
EP0519854A3 (https=) 1994-02-16
US5194397A (en) 1993-03-16

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