JPH07147207A - Manufacture of chip resistor - Google Patents

Manufacture of chip resistor

Info

Publication number
JPH07147207A
JPH07147207A JP5293070A JP29307093A JPH07147207A JP H07147207 A JPH07147207 A JP H07147207A JP 5293070 A JP5293070 A JP 5293070A JP 29307093 A JP29307093 A JP 29307093A JP H07147207 A JPH07147207 A JP H07147207A
Authority
JP
Japan
Prior art keywords
layer
electrode layer
film upper
thin film
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5293070A
Other languages
Japanese (ja)
Inventor
Hideo Kobayashi
英雄 小林
Hiroyuki Yamada
博之 山田
Seiji Tsuda
清二 津田
Akio Fukuoka
章夫 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5293070A priority Critical patent/JPH07147207A/en
Publication of JPH07147207A publication Critical patent/JPH07147207A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent imperfect contact between a measuring terminal and an upper electrode layer at the time of resistance value correction, by forming a secondary thick film upper electrode layer on a primary thin film upper electrode layer so as not to overlap a resistor. CONSTITUTION:An electrode paste composed of metal organic matter whose main component is Au is screen-printed on both sides of each individual segment type part formed on the surface of an insulating substrate 1, and a primary thin film upper electrode layer 3 is formed by baking. A resistance layer 4 is formed on a part of the primary thin film electrode layer 3 so as to overlap there, and a precoat glass layer 5 is formed so as to completely cover the resistance layer 4. A secondary thick film electrode layer 6 is formed by screen- printing Ag based paste on the primary thin film upper electrode layer 3 and baking it. At the time of resistance correction, a measuring terminal comes into contact with the secondary thick film upper electrode layer 6, so that imperfect contact can be prevented without being affected by surface roughness of the insulating substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、一般的に電子回路に用
いられるチップ抵抗器の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a method of manufacturing a chip resistor used in electronic circuits.

【0002】[0002]

【従来の技術】近年、ハイブリッドICの小形・軽量・
薄形化が進むにつれ、電子部品の高密度実装化、省資源
化、信頼性の向上等をねらった新製品開発が進んできて
いる。電子部品の一つとしてのチップ抵抗器において
も、従来にも増して小形で高精度であり、しかも低コス
トのものが需要者側から広く要望されてきている。
2. Description of the Related Art In recent years, hybrid ICs are small and lightweight.
As the products have become thinner, new products have been developed aiming at high-density mounting of electronic parts, resource saving, and improvement of reliability. Even in the case of a chip resistor as one of electronic components, there is a widespread demand from consumers for a smaller and more accurate chip resistor than ever before and at a low cost.

【0003】以下、従来のチップ抵抗器の製造方法の一
例を図3の工程図に基づいて説明する。
An example of a conventional method of manufacturing a chip resistor will be described below with reference to the process chart of FIG.

【0004】すなわち、まず、工程aにおいて高純度の
アルミナ基板等からなる耐熱性の絶縁基板21の受け入
れを行う。この絶縁基板21には短冊状及び個片状に分
割するための分割溝22が形成されている。次に、工程
bで絶縁基板21上の各個片状部の両側部にAu系の上
面電極層23を形成する。そして工程cにおいてこの上
面電極層23の一部に重なるように抵抗体層24を形成
する。次に、工程dでこの抵抗体層24の抵抗値を所定
の値に修正するために、レーザートリミング法等によっ
て抵抗体層24にトリミング溝25を形成する抵抗値修
正の工程を実行する。
That is, first, in step a, a heat-resistant insulating substrate 21 made of a high-purity alumina substrate or the like is received. Dividing grooves 22 for dividing the insulating substrate 21 into strips and individual pieces are formed. Next, in step b, the Au-based upper surface electrode layer 23 is formed on both sides of each individual piece on the insulating substrate 21. Then, in step c, the resistor layer 24 is formed so as to partially overlap the upper surface electrode layer 23. Next, in step d, in order to correct the resistance value of the resistor layer 24 to a predetermined value, a resistance value correcting step of forming the trimming groove 25 in the resistor layer 24 by a laser trimming method or the like is executed.

【0005】次に、工程eでは工程dで形成した抵抗体
層24を保護するために、その表面にオーバーコート用
のガラス層26を形成する。次の工程fは絶縁基板21
を短冊状基板21aに分割する一次基板分割工程であ
り、この工程は次の工程gにて短冊状基板21aの端面
に端面電極層27を形成するための準備工程である。
Next, in step e, a glass layer 26 for overcoating is formed on the surface of the resistor layer 24 in order to protect the resistor layer 24 formed in step d. The next step f is the insulating substrate 21.
Is a primary substrate dividing step of dividing the strip-shaped substrate 21a into a strip-shaped substrate 21a. This step is a preparatory step for forming the end face electrode layer 27 on the end face of the strip-shaped substrate 21a in the next step g.

【0006】また次の工程hは短冊状基板21aを個片
状基板21bに分割する二次基板分割工程であり、次工
程iで露出している電極面をめっきを施す準備工程とな
るもので、工程iにおいてはんだ付け時の信頼性の確保
のための電極めっき層28を電極面に形成するように
し、これらの工程a〜iによってチップ抵抗器を形成し
ていた。
The next step h is a step of dividing the strip-shaped substrate 21a into individual substrates 21b, which is a preparatory step for plating the electrode surface exposed in the next step i. In the step i, the electrode plating layer 28 for ensuring reliability during soldering is formed on the electrode surface, and the chip resistor is formed by the steps a to i.

【0007】[0007]

【発明が解決しようとする課題】しかし、従来のチップ
抵抗器は抵抗温度係数を±50ppm/℃以内とするた
め、一般的に上面電極層23にAu系のペーストを使用
するが、厚膜のAuは高価なため生産コストの増大につ
ながるものであった。このために、上面電極層23にA
u系の金属有機物ペースト(レジネートペースト)を使
用すれば、薄膜による上面電極層が形成でき、安価にチ
ップ抵抗器を製造することはできる。しかしながら、上
面電極層が薄膜のために工程dの抵抗値修正工程におい
て、絶縁基板21の表面粗さの影響を受けやすくなり、
測定端子との接触不良を生じて抵抗値不良が多発すると
いう課題を有していた。
However, since the conventional chip resistor has a temperature coefficient of resistance within ± 50 ppm / ° C., Au-based paste is generally used for the upper electrode layer 23. Since Au is expensive, it leads to an increase in production cost. For this reason, the upper electrode layer 23 has A
If the u-based metal organic paste (resinate paste) is used, the upper surface electrode layer made of a thin film can be formed, and the chip resistor can be manufactured at low cost. However, since the upper surface electrode layer is a thin film, it becomes easy to be affected by the surface roughness of the insulating substrate 21 in the resistance value correcting step of step d,
There has been a problem that a poor contact with the measurement terminal occurs and a defective resistance value frequently occurs.

【0008】本発明は上記課題を解決するもので、上面
電極層に厚膜のAuペーストを使用した場合と同等の優
れた信頼性を有し、しかも抵抗値修正工程において測定
端子との接触不良をなくすことで、抵抗値不良による歩
留悪化を低減させ、安価にチップ抵抗器を提供できるよ
うにすることを目的としている。
The present invention solves the above problems and has the same excellent reliability as that when a thick Au paste is used for the upper electrode layer, and also has a poor contact with the measurement terminal in the resistance correction step. It is an object of the present invention to reduce the yield deterioration due to defective resistance and to provide a chip resistor at low cost by eliminating the above.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明のチップ抵抗器の製造方法は、表裏面の少なく
とも一方に互いに相対するように設けた縦方向及び横方
向の分割溝を有する絶縁基板の表面上に、Au系の金属
有機物からなる電極材料を印刷し焼成して一対の第一次
薄膜上面電極層を形成する工程と、この一対の第一次薄
膜上面電極層に重なるように抵抗体層を形成する工程
と、この抵抗体層に掛からないようにし、かつ前記第一
次薄膜上面電極層上に一対の第二次厚膜上面電極層を形
成する工程と、前記抵抗体層の抵抗値を修正する工程
と、この抵抗体層を完全に覆うようにオーバーコートガ
ラス層を形成する工程と、前記絶縁基板に端面電極層を
形成するために前記絶縁基板を一次分割する工程と、こ
の一次分割した基板の端面部に電極層の形成を行う工程
と、電極用めっき層を形成するために前記一次分割した
基板を個片に二次分割する工程と、二次分割後露出した
電極部にめっき層を形成する工程とを備えたものであ
る。
In order to achieve the above object, a method of manufacturing a chip resistor according to the present invention has vertical and horizontal dividing grooves provided on at least one of front and back surfaces so as to face each other. A step of printing an electrode material made of an Au-based metal organic material on the surface of the insulating substrate and baking the electrode material to form a pair of primary thin film upper surface electrode layers, and a step of overlapping the pair of primary thin film upper surface electrode layers. A resistor layer on the first thin film upper electrode layer, and a step of forming a pair of secondary thick film upper electrode layers on the primary thin film upper electrode layer so as not to cover the resistor layer; A step of correcting the resistance value of the layer, a step of forming an overcoat glass layer so as to completely cover the resistor layer, and a step of primarily dividing the insulating substrate to form an end face electrode layer on the insulating substrate. And of this primary divided board The step of forming an electrode layer on the surface portion, the step of subdividing the primary divided substrate into pieces to form the electrode plating layer, and the step of forming a plating layer on the exposed electrode portion after the secondary division And a process.

【0010】[0010]

【作用】上記した構成により、第一次薄膜上面電極層に
は金属有機物ペーストを使用しているので材料コストを
下げることができるとともに、第一次薄膜上面電極層の
上に第二次厚膜上面電極層として厚膜電極層を抵抗体に
掛からないように重ねて形成しているので、抵抗値を修
正する工程において測定端子がこの第二次厚膜上面電極
層と接触するため、薄膜上面電極層のみ形成した場合と
は異なり、基板の表面粗さの影響を受けず、測定端子結
合時の接触不良による抵抗値不良を低減できる。
With the above structure, since the metal organic paste is used for the primary thin film upper surface electrode layer, the material cost can be reduced, and at the same time, the secondary thick film is formed on the primary thin film upper surface electrode layer. Since the thick film electrode layer is formed as the upper surface electrode layer so as not to overlap the resistor, the measuring terminal contacts with this secondary thick film upper surface electrode layer in the process of correcting the resistance value, so the thin film upper surface Unlike the case where only the electrode layer is formed, it is not affected by the surface roughness of the substrate, and the resistance value failure due to the contact failure at the time of connecting the measurement terminals can be reduced.

【0011】[0011]

【実施例】以下、本発明の一実施例について、図1,図
2を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0012】図1はチップ抵抗器の製造方法の一例を示
す工程図で、図2はその工程によって製造した製品の断
面図である。図において、Aは受け入れ工程であり、ま
ず、工程Aで耐熱性及び絶縁性に優れた例えばアルミナ
96からなる絶縁基板1を受け入れる。この絶縁基板1
の表裏面には、絶縁基板1を短冊状及び個片状に分割で
きるように、両面に互いに相対するように設けた縦方向
及び横方向の分割溝2がグリーンシート時の金型成形等
によって形成されている。
FIG. 1 is a process diagram showing an example of a method of manufacturing a chip resistor, and FIG. 2 is a sectional view of a product manufactured by the process. In the figure, A is a receiving step. First, in step A, the insulating substrate 1 made of, for example, alumina 96 having excellent heat resistance and insulating properties is received. This insulating substrate 1
On the front and back surfaces of the insulating substrate 1, vertical and horizontal dividing grooves 2 are provided so as to face each other so that the insulating substrate 1 can be divided into strips and individual pieces by die molding at the time of green sheet or the like. Has been formed.

【0013】次に、工程Bでは、絶縁基板1の表面に形
成した各個片状部の両側部にAuを主成分とした金属有
機物からなる電極ペーストをスクリーン印刷し、かつベ
ルト式連続焼成炉によって850℃の温度で、ピーク時
間6分、IN−OUT(保持)時間45分のプロファイ
ル(設定条件)によって焼成して第一次薄膜上面電極層
3を形成する。
Next, in step B, an electrode paste made of a metal organic compound containing Au as a main component is screen-printed on both sides of each individual piece formed on the surface of the insulating substrate 1, and the belt type continuous firing furnace is used. The primary thin film upper surface electrode layer 3 is formed by baking at a temperature of 850 ° C. according to a profile (setting conditions) with a peak time of 6 minutes and an IN-OUT (holding) time of 45 minutes.

【0014】次に、工程Cでは、第一次薄膜上面電極層
3の一部に重なるようにRuO2系からなる抵抗ペース
トをスクリーン印刷し、かつベルト式連続焼成炉によっ
て850℃の温度で、ピーク時間6分、IN−OUT時
間45分のプロファイルにより焼成して抵抗体層4を各
個片部に形成する。
Next, in step C, a RuO 2 -based resistance paste is screen-printed so as to overlap a part of the primary thin film upper surface electrode layer 3, and the temperature is set to 850 ° C. in a belt type continuous firing furnace. The resistor layer 4 is formed on each individual part by firing according to a profile with a peak time of 6 minutes and an IN-OUT time of 45 minutes.

【0015】次に、工程Dでは、工程Cで形成した抵抗
体層4を保護し、後工程でのレーザートリミング性を向
上させるために、抵抗体層4を完全に覆うようにプリコ
ート用のガラスペーストをスクリーン印刷し、かつベル
ト式連続焼成炉によって600℃の温度で、ピーク時間
6分、IN−OUT時間45分のプロファイルにより焼
成してプリコートガラス層5を形成する。
Next, in step D, in order to protect the resistor layer 4 formed in step C and to improve the laser trimming property in the subsequent step, the glass for precoating should cover the resistor layer 4 completely. The paste is screen-printed and baked in a belt-type continuous baking furnace at a temperature of 600 ° C. according to a profile with a peak time of 6 minutes and an IN-OUT time of 45 minutes to form a precoated glass layer 5.

【0016】次に、工程Eでは、後工程Fの抵抗値修正
工程において測定端子結合時の接触不良による抵抗値不
良をなくすために、第一次薄膜上面電極層3の上に55
0〜650℃の軟化点を有するAg系のペーストをスク
リーン印刷し、かつベルト式連続焼成炉によって600
℃の温度で、ピーク時間6分、IN−OUT時間45分
のプロファイルにより焼成して第二次厚膜上面電極層6
を形成する。そして、抵抗体層4の抵抗値を所定の値に
修正するために、レーザー光によって抵抗体層4にトリ
ミング溝7を形成する抵抗値修正の工程Fを実行する。
Next, in the step E, 55 is formed on the primary thin film upper surface electrode layer 3 in order to eliminate the resistance value failure due to the contact failure at the time of connecting the measuring terminals in the resistance value correcting step of the subsequent step F.
An Ag-based paste having a softening point of 0 to 650 ° C. is screen-printed, and a belt-type continuous firing furnace is used to 600
The secondary thick film upper surface electrode layer 6 is baked at a temperature of ℃ at a peak time of 6 minutes and an IN-OUT time of 45 minutes.
To form. Then, in order to correct the resistance value of the resistor layer 4 to a predetermined value, a resistance value correction step F of forming the trimming groove 7 in the resistor layer 4 by laser light is executed.

【0017】次に、工程Gで前工程までに得た抵抗体層
4の保護のために、プリコートガラス層5を完全に覆う
ようにオーバーコート用のガラスペーストをスクリーン
印刷し、かつベルト式連続焼成炉によって600℃の温
度で、ピーク時間6分、IN−OUT時間45分のプロ
ファイルにより焼成してオーバーコートガラス層8を形
成する。
Next, in order to protect the resistor layer 4 obtained in the previous step in step G, a glass paste for overcoating is screen-printed so as to completely cover the precoat glass layer 5, and the belt type continuous coating is carried out. The overcoat glass layer 8 is formed by firing in a firing furnace at a temperature of 600 ° C. with a profile having a peak time of 6 minutes and an IN-OUT time of 45 minutes.

【0018】次の工程Hは絶縁基板1を短冊状に分割し
て短冊状基板1aを得る基板一次分割工程であり、この
工程Hは次工程Iで端面電極層9を形成するための準備
工程となり、端面電極を露出させる工程である。
The next step H is a substrate primary dividing step in which the insulating substrate 1 is divided into strips to obtain strip-shaped substrates 1a. This step H is a preparatory step for forming the end face electrode layer 9 in the next step I. This is a step of exposing the end face electrodes.

【0019】工程Iでは、短冊状基板1aの側面に、第
二次厚膜上面電極層6の一部と重なるように厚膜のAg
ペーストをローラーによって塗布し、かつベルト式連続
焼成炉によって600℃の温度で、ピーク時間6分、I
N−OUT時間45分のプロファイルにて焼成して端面
電極層9を形成する。
In step I, the thick film Ag is formed on the side surface of the strip-shaped substrate 1a so as to overlap a part of the secondary thick film upper surface electrode layer 6.
The paste is applied by rollers and in a belt-type continuous firing furnace at a temperature of 600 ° C. for a peak time of 6 minutes, I
The end face electrode layer 9 is formed by firing in a profile of N-OUT time 45 minutes.

【0020】次に、端面電極層9にめっきを施すための
準備工程として、端面電極層9が形成済みとなった短冊
状基板1aを、個片状基板1bに分割する基板二次分割
の工程Jを実行する。
Next, as a preparatory step for plating the end face electrode layer 9, the strip-shaped substrate 1a on which the end face electrode layer 9 has been formed is divided into individual substrate 1b, which is a step of subdividing the substrate. Run J.

【0021】そして最後に、露出している第二次厚膜上
面電極層6と端面電極層9のはんだ付け時の電極喰われ
(消失)の防止及びはんだ付け時の信頼性の確保のた
め、電解めっきによってNi,Sn−Pbのめっき層1
0を形成する工程Kを実行する。
Finally, in order to prevent electrode erosion (disappearance) during soldering of the exposed secondary thick film upper surface electrode layer 6 and end face electrode layer 9 and to secure reliability during soldering, Ni, Sn-Pb plating layer 1 by electrolytic plating
Step K of forming 0 is performed.

【0022】以上の工程A〜Kの実行により、図2に示
すようなチップ抵抗器11を試作した。
By carrying out the above steps A to K, a chip resistor 11 as shown in FIG. 2 was prototyped.

【0023】このように本発明のチップ抵抗器の製造方
法により、抵抗値修正工程における測定端子結合時の接
触不良による抵抗値不良率を、上面電極層に金属有機物
ペーストを使用した従来のチップ抵抗器の10%からほ
ぼ0%にまで低減させることができた。
As described above, according to the method of manufacturing a chip resistor of the present invention, the resistance value failure rate due to contact failure at the time of connecting the measuring terminals in the resistance value correcting step is determined by the conventional chip resistance using the metal organic paste for the upper surface electrode layer. It was possible to reduce from 10% of the container to almost 0%.

【0024】なお、本発明の実施例では、抵抗体層4を
保護するためにプリコート用ガラスペーストを印刷・焼
成する工程Dを加えているが、この工程Dを削除しても
よい。
In the embodiment of the present invention, the step D of printing and firing the precoat glass paste is added to protect the resistor layer 4, but this step D may be omitted.

【0025】[0025]

【発明の効果】以上の説明から明らかなように本発明の
チップ抵抗器の製造方法によれば、次のような効果が得
られる。 (1) Au系の金属有機物ペーストを焼成して、第一
次薄膜上面電極層を形成するので、重なり合った抵抗膜
層との間の反応拡散を低減させることができ、厚膜Au
系ペーストを上面電極層に使用した従来のチップ抵抗器
と同等の特性を有するチップ抵抗器を安価に提供でき
る。 (2) プリコートガラス層と端面電極層に囲まれた第
一次薄膜上面電極層の全面を厚膜Agペーストによる第
二次厚膜上面電極層で被覆すれば、抵抗値修正工程にお
いて測定端子がこの第二次厚膜上面電極層と接触するた
め、絶縁基板の表面粗さの影響を受けず、測定端子結合
時の接触不良による抵抗値不良をなくすることができ
る。また、第二次厚膜上面電極層を形成するために導電
性樹脂ペーストを使用する場合も考えられるが、その場
合よりも厚膜グレーズペーストを使用して高温(600
℃)で形成することにより、上面電極強度を強くするこ
とができる。
As is apparent from the above description, according to the method of manufacturing the chip resistor of the present invention, the following effects can be obtained. (1) Since the Au-based metal organic paste is fired to form the primary thin film upper surface electrode layer, it is possible to reduce reaction diffusion between the resistive film layer and the thick resistive film.
It is possible to inexpensively provide a chip resistor having characteristics equivalent to those of a conventional chip resistor using the system paste for the upper surface electrode layer. (2) If the entire surface of the primary thin film upper surface electrode layer surrounded by the pre-coated glass layer and the end surface electrode layer is covered with the secondary thick film upper surface electrode layer of the thick film Ag paste, the measurement terminals will become Since the second thick film upper surface electrode layer is brought into contact with the second thick film upper surface electrode layer, the resistance value is not affected by the surface roughness of the insulating substrate and the resistance value failure due to the contact failure at the time of connecting the measurement terminals can be eliminated. In addition, a case where a conductive resin paste is used to form the second thick film upper surface electrode layer may be considered, but a thick film glaze paste is used at a high temperature (600
The surface electrode strength can be increased by forming the upper electrode.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のチップ抵抗器の製造方法を
示す工程図
FIG. 1 is a process diagram showing a method of manufacturing a chip resistor according to an embodiment of the present invention.

【図2】同製造方法で得たチップ抵抗器の断面図FIG. 2 is a sectional view of a chip resistor obtained by the same manufacturing method.

【図3】従来のチップ抵抗器の製造方法を示す工程図FIG. 3 is a process diagram showing a conventional method for manufacturing a chip resistor.

【符号の説明】[Explanation of symbols]

1 絶縁基板 1b 個片状基板(個片) 2 分割溝 3 第一次薄膜上面電極層 4 抵抗体層 6 第二次厚膜上面電極層 8 オーバーコートガラス層 9 端面電極層 10 めっき層 11 チップ抵抗器 DESCRIPTION OF SYMBOLS 1 Insulating substrate 1b Piece-shaped substrate (piece) 2 Dividing groove 3 Primary thin film upper surface electrode layer 4 Resistor layer 6 Secondary thick film upper surface electrode layer 8 Overcoat glass layer 9 End surface electrode layer 10 Plating layer 11 Chip Resistor

フロントページの続き (72)発明者 福岡 章夫 大阪府門真市大字門真1006番地 松下電器 産業株式会社内Front page continuation (72) Inventor Akio Fukuoka, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 表裏面の少なくとも一方に互いに相対す
るように設けた縦方向及び横方向の分割溝を有する絶縁
基板の表面上に、Au系の金属有機物からなる電極材料
を印刷し焼成して一対の第一次薄膜上面電極層を形成す
る工程と、この一対の第一次薄膜上面電極層に重なるよ
うに抵抗体層を形成する工程と、この抵抗体層に掛から
ないようにし、かつ前記第一次薄膜上面電極層上に一対
の第二次厚膜上面電極層を形成する工程と、前記抵抗体
層の抵抗値を修正する工程と、この抵抗体層を完全に覆
うようにオーバーコートガラス層を形成する工程と、前
記絶縁基板に端面電極層を形成するために前記絶縁基板
を一次分割する工程と、この一次分割した基板の端面部
に電極層の形成を行う工程と、電極用めっき層を形成す
るために前記一次分割した基板を個片に二次分割する工
程と、二次分割後露出した電極部にめっき層を形成する
工程とを備えたことを特徴とするチップ抵抗器の製造方
法。
1. An electrode material made of an Au-based metal organic material is printed and baked on the surface of an insulating substrate having vertical and horizontal dividing grooves provided on at least one of the front and back surfaces so as to face each other. A step of forming a pair of primary thin film upper surface electrode layers, a step of forming a resistor layer so as to overlap with the pair of primary thin film upper surface electrode layers, and so as not to hang over the resistor layer, and Forming a pair of secondary thick film upper surface electrode layers on the primary thin film upper surface electrode layer, modifying the resistance value of the resistor layer, and overcoating so as to completely cover the resistor layer. A step of forming a glass layer, a step of primary dividing the insulating substrate to form an end surface electrode layer on the insulating substrate, a step of forming an electrode layer on an end surface portion of the primary divided substrate, and an electrode In order to form the plating layer 2. A method of manufacturing a chip resistor, comprising: a step of secondarily dividing the divided substrate into individual pieces; and a step of forming a plating layer on an electrode portion exposed after the second division.
【請求項2】 第二次厚膜上面電極層は、550〜65
0℃の軟化点を有するAg系の厚膜グレーズペーストを
印刷・焼成して形成することを特徴とする請求項1記載
のチップ抵抗器の製造方法。
2. The secondary thick film upper surface electrode layer comprises 550 to 65.
2. The method for manufacturing a chip resistor according to claim 1, wherein the thick film glaze paste of Ag type having a softening point of 0 [deg.] C. is formed by printing and firing.
JP5293070A 1993-11-24 1993-11-24 Manufacture of chip resistor Pending JPH07147207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5293070A JPH07147207A (en) 1993-11-24 1993-11-24 Manufacture of chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5293070A JPH07147207A (en) 1993-11-24 1993-11-24 Manufacture of chip resistor

Publications (1)

Publication Number Publication Date
JPH07147207A true JPH07147207A (en) 1995-06-06

Family

ID=17790066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5293070A Pending JPH07147207A (en) 1993-11-24 1993-11-24 Manufacture of chip resistor

Country Status (1)

Country Link
JP (1) JPH07147207A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030052196A (en) * 2001-12-20 2003-06-26 삼성전기주식회사 Thin film chip resistor and method of fabricating the same
US7103965B2 (en) 2002-01-17 2006-09-12 Rohm Co., Ltd. Method of making chip resistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030052196A (en) * 2001-12-20 2003-06-26 삼성전기주식회사 Thin film chip resistor and method of fabricating the same
US7103965B2 (en) 2002-01-17 2006-09-12 Rohm Co., Ltd. Method of making chip resistor
US7352273B2 (en) 2002-01-17 2008-04-01 Rohm Co., Ltd. Chip resistor

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