JPH07130802A - Manufacture of semiconductor wafer, and semiconductor tester - Google Patents

Abstract

PURPOSE:To improve the throughput in semiconductor testing by increasing the number of chips to be tested for electric characteristics at the same time. CONSTITUTION:A semiconductor tester is used for the probe inspection of chips on a wafer. An input probe card 10 supplies the input signal into a semiconductor wafer 50. An output probe card 20 transmits the output signal into a tester. The input probe card 10 is mounted on a probe card stage 30. A wafer is mounted on a wafer stage 40. The apparatus is constituted of these parts. The input signal is supplied into input pads 51 through the input probe card 10. The signal is further supplied into all chips 60 from the input pads 51. Then, the probe inspection is performed. The result is outputted into the tester through the output probe card 20. The number of the simultaneous measurement of the chips can be improved by this probe-card dividing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor inspection apparatus, and more particularly to a technique effectively applied to a technique for simultaneously measuring a plurality of chips in an inspection of electric characteristics of chips on the semiconductor wafer.

[0002]

2. Description of the Related Art For example, in a process of inspecting electrical characteristics of a semiconductor wafer (hereinafter abbreviated as a wafer) (hereinafter referred to as probe inspection), in order to simultaneously measure each chip on a wafer, a probe card The number of probe needles is also increased to perform probe inspection. Further, the probe card has a mixture of input probe needles for processing input signals and output probe needles for processing output signals.

Therefore, the probe density on the probe card has increased, and it has become technically difficult to manufacture the probe card. With the current probe card manufacturing technology,
It is said that the limit is to measure 8 chips at the same time.

[0004]

However, in the above-mentioned conventional technique, the input probe needle for processing the input signal and the output probe needle for processing the output signal are connected to one probe card. As a result, the probe density of the probe card increases, while the number of chips that can be simultaneously measured by the tester does not increase, so that the semiconductor inspection process has a low throughput.

As a background for this, the number of chips that can be measured simultaneously is 1.
The number of probe needles provided on the probe card also increases in proportion to the increase in the number of chips that can be simultaneously measured, from 2, to 4, 4 and 8 in sequence.

For this reason, on the probe card,
When the probe density increases and the number of chips that can be simultaneously measured is larger than this, it is technically difficult to manufacture a probe card, and the problem is that the number of simultaneous measurements is becoming the limit due to the high density of probe needles. is there.

Further, when the number of chips to be simultaneously measured increases, the number of probe needles arranged on one probe card increases, and the probe needles have a high density, so that there is a problem that the alignment accuracy with the wafer deteriorates.

Therefore, an object of the present invention is to provide a semiconductor inspection apparatus which improves the throughput of the semiconductor inspection process by increasing the number of simultaneous chip probe inspections.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, a method of manufacturing a wafer according to a first aspect is a wafer in which a plurality of chips are provided, each of which has an in-chip input pad for an input signal and an in-chip output pad for an output signal. The common input signals supplied to the in-chip input pads of a plurality of chips are short-circuited and gathered at one or several places in the empty area of the wafer, and the input pad is provided at the tip thereof.

Further, in the method of manufacturing a wafer according to the second aspect, the insulating layer is provided so that the signal lines of the signals common to the plurality of chips or the signal lines of the power supply do not cross the dicing lines between the plurality of chips. The three-dimensional wiring is provided by sandwiching the two.

The semiconductor inspection apparatus according to claim 3 is
A semiconductor inspection device for inspecting the electrical characteristics of a wafer using a probe card in which conductive probe needles are arranged. The probe card is brought into contact with an input pad that supplies an input signal to a plurality of chips. , Input system signal probe card fixed at a predetermined position on the wafer and contact with the in-chip output pads of a plurality of chips to separate the predetermined range on the wafer into a movable output system signal probe card To do.

[0014]

According to the above-described semiconductor inspection apparatus, on-wafer input pads on the chip for common input signals of the respective chips are short-circuited through the dicing lines outside the chips, and collected at one or several places in the empty area on the wafer. An input pad is added to the tip.

Therefore, by supplying a test signal to a plurality of chips from the input pads gathered at one place or at several places, all the chips short-circuited thereto can be
A test signal can be supplied.

Further, in order to increase the number of chips to be simultaneously measured, it is necessary to measure a large number of output signals of each chip at the same time. To this end, it is necessary to increase the number of probe needles for the output signals of the probe card. The system signal probe card and the output system signal probe card are divided into a conventional probe card that is movable on the wafer, a movable output system signal probe card, and another fixed input system signal probe card. The number of chips that can be simultaneously measured can be increased by separating the chips.

As a result, the number of probe needles per probe card is reduced, and the probe density of the probe card, which is an obstacle to the simultaneous measurement of a large number of chips, can be reduced as compared with the conventional technique.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 (a) and 1 (b) are a plan view and a sectional view showing a semiconductor inspection apparatus according to an embodiment of the present invention, FIG. 2 is an enlarged partial plan view showing a wafer in this embodiment, and FIG. It is an expanded partial sectional view showing a wafer in the present example.

First, the structure of the semiconductor inspection apparatus of this embodiment will be described with reference to FIGS. 1 (a) and 1 (b).

The semiconductor inspection apparatus of this embodiment is, for example, a semiconductor inspection apparatus for inspecting chips on a wafer, and an input probe card (input system signal probe card) for supplying an input signal from a tester to the wafer. 10
And an output probe card (output system signal probe card) for transmitting the output signal from the chip to the tester 2
0, a probe card stage 30 on which the input probe card 10 is mounted, and a wafer stage 40 on which a wafer is mounted.

The input probe card 10 is connected to the input pad 51 of the semiconductor wafer 50 via the input probe needle 11, and is also connected to a tester (not shown) which supplies an input signal. The input probe card 10 is fixed on the semiconductor wafer 50 and short-circuited by a test signal supplied from the input pad 51 to the shorted chip 6
All 0s are in the operation (testing) state.

The output probe card 20 includes a chip 60.
Is connected to the in-chip output pad 61 via the output probe needle 21, and is also connected to a tester that determines the output signal from the chip 60. Like the conventional probe card, it can be moved on the semiconductor wafer 50, and a plurality of chips 60 on the semiconductor wafer 50 are measured one by one.

As shown in FIG. 2, the semiconductor wafer 50 is provided with the input pads 51 at several places in the empty area, and the input pads 62 in the chip are short-circuited by the aluminum wiring 70,
By supplying an input signal (address, write enable, out enable, other clock, power supply, etc.) for testing from the input pad 51 to all the chips 60, a plurality of chips 60 can be simultaneously measured.

Since the input pads 51 are concentrated at one or several places in the empty area of the semiconductor wafer 50, it is not necessary to attach the input pads 51 to each chip 60.

The aluminum wiring 70 on the semiconductor wafer 50 is
Scribe line between chips 60 (dicing line)
The width is 50 to 100 μm, and the width is made to be 1 to 2 μm, so that the aluminum wirings 70 do not interfere with each other when scribing in the scribing process. Further, the aluminum wirings 70 can intersect with each other by three-dimensionally sandwiching an oxide film (insulating layer) 80 or the like for insulation as shown in FIG.

Next, the operation of this embodiment will be described.

First, the operator operates the wafer stage 4
The input probe card 10 is aligned with the semiconductor wafer 50 mounted on the semiconductor wafer 50, and the input probe needle 11 is brought into contact with the input pad 51 of the semiconductor wafer 50 to fix the input probe card 10.

Next, the operator aligns the output probe card 20 with the plurality of chips 60 to be measured on the semiconductor wafer 50, and outputs the output probe needles 21 to the in-chip outputs of the plurality of chips 60. Pad 61
To contact.

Then, the input signal is transmitted to all the chips 60 on the semiconductor wafer 50 through the input probe card 10 and the input probe needle 11, and these chips 6 are transmitted.
The probe test of 0 is performed, the resulting output signals are transmitted from the plurality of chips 60 to be measured to the tester via the output probe needles 21 and the output probe card 20, and the quality of the chips 60 is determined. .

In this case, the transmission of the input signal becomes slower as the distance from the input pad 51 increases, but by adding a delay circuit to the chips 60 close to each other, the difference in transmission speed between the chips 60 can be minimized.

Further, the operator moves the output probe card 20 to another plurality of chips 60 on the semiconductor wafer 50, changes the chip 60 to be measured, and repeats the probe inspection.

Therefore, according to the semiconductor inspection apparatus of this embodiment, the probe card is divided into the input probe card 10 and the output probe card 20, and the input probe card 1 is used.
By fixing 0 and making the output probe card 20 movable on the semiconductor wafer 50, it is possible to separate the conventional probe needle 11 for input and the probe needle 21 for output that were present on the same probe card. Further, the number of simultaneous measurements of the chip 60 on the semiconductor wafer 50 by the tester can be increased, and the throughput of the semiconductor inspection process can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). In the probe inspection process for a chip on a wafer, which is one of the semiconductor inspection processes, by dividing the probe card into an input system signal probe card and an output system signal probe card, The number of chips simultaneously measured by the tester can be increased, and the throughput of the semiconductor inspection process can be improved.

(2). Even if the number of probe needles arranged on one probe card increases due to an increase in the number of chips that can be simultaneously measured, the density is not higher than in the conventional case, and the measurement accuracy in probe inspection is improved. Can be improved.

(3). In the probe inspection step, the throughput of the tester, which is an external measuring instrument, can be improved by improving the number of chips that can be simultaneously measured.

(4). On the wafer, common input signals of a plurality of chips are short-circuited and gathered at one place or several places, and an input pad is provided at the tip thereof, so that a probe needle of a probe card for input system signals is provided. It is possible to reduce the number of the probe cards, and it is possible to prevent high density of the probe card.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view showing a semiconductor inspection device according to an embodiment of the present invention.

FIG. 2 is an enlarged partial plan view showing a wafer in this embodiment.

FIG. 3 is an enlarged partial sectional view showing a wafer in this embodiment.

[Explanation of symbols]

10 input probe card (input system signal probe card) 11 input probe needle 20 output probe card (output system signal probe card) 21 output probe needle 30 probe card stage 40 wafer stage 50 semiconductor wafer 51 input Pad 60 Chip 61 In-chip output pad 62 In-chip input pad 70 Aluminum wiring 80 Oxide film (insulating layer)

Claims (3)

[Claims] 1. A semiconductor wafer having a plurality of chips formed with an in-chip input pad for an input signal and an in-chip output pad for an output signal, the inside of the chip of the plurality of chips being formed. A method for manufacturing a semiconductor wafer, characterized in that a common input signal supplied to an input pad is short-circuited, gathered at one or several places in an empty region of the semiconductor wafer, and an input pad is provided at the tip thereof. 2. A signal line of a signal or a power supply common to the plurality of chips is three-dimensionally arranged by sandwiching an insulating layer so that the wiring does not intersect with a dicing line between the plurality of chips. Wiring is carried out.
A method for manufacturing a semiconductor wafer as described above. 3. A semiconductor inspection apparatus for inspecting the electrical characteristics of the semiconductor wafer according to claim 1 or 2 by using a probe card in which conductive probe needles are arranged,
An input-system signal probe card fixed to a predetermined position on the semiconductor wafer by bringing the probe card into contact with the input pad that supplies an input signal to the plurality of chips, and the chips in the plurality of chips. A semiconductor inspection apparatus, characterized in that it contacts an inner output pad and separates a predetermined range on the semiconductor wafer into a movable output system signal probe card.