JPH07118650B2 - Field effect transistor circuit - Google Patents

Description

Detailed Description of the Invention

The present invention relates to field effect transistor circuits.

[0002]

2. Description of the Related Art A conventional bidirectional current output type digital-analog (DA) converter that utilizes the characteristics of the saturation region of a MOSFET as a weight current source is about 200 mW especially at a low voltage of about 2.5V. In order to directly drive the speaker with the output of, the channel width of the weight current source MOSFET and the current characteristic switching MOSFET whose impedance changes must be four times or more than that at the time of driving 5V,
When this D-A converter is incorporated in an LSI, the ratio of the D-A converter in the LSI is large and the cost is 5V.
There is a drawback that it is significantly higher than the case where a D-A converter using a power source is incorporated. Further, there is a drawback that the linear distortion becomes significantly worse than that at the time of operating at 5V.

[0003]

Particularly, in the related art, since the switching transistor connected to the current source whose impedance changes, is controlled to be opened and closed only by the ON / OFF signal for switch control, the switching transistor and the current source are not connected to each other. It was not possible to make a constant voltage ratio at the connection point of. Therefore, there is a drawback that the transistor forming the current source can be used only in a saturated state and the distortion factor of the current source transistor increases.

[0004]

The field effect transistor circuit of the present invention comprises a first terminal which requires a constant voltage and an operating current.
A source connected between the second terminal to which the pressure is applied
Field effect transistor having drain current path and control
A first input terminal for receiving a signal, connected to the first terminal
Of the second input terminal and the field effect transistor
A gate circuit that has an output terminal connected to the gate
When the control signal is at the first logic level, the second
Specified at the output terminal regardless of the voltage level of the input terminal
Voltage is generated to turn off the field effect transistor.
And when the control signal is at the second logic level, the second
Generates a voltage at the output terminal according to the voltage at the input terminal of
A transistor that forms a negative feedback loop for the transistor.
And a control circuit, wherein the control signal is the second logic level.
At that time, a constant voltage is applied to the second terminal by the negative feedback loop.
It is what gets pressure.

[0005]

FIG. 1 shows an embodiment of the present invention, in which Q ₁ , Q ₂ , Q
₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ , and Q ₈ are enhancement-type MOSFETs, and Q ₁ , Q ₂ , Q ₃ , and Q ₄ are weight data inputs D ₁ and D of the DA converter, respectively. ₂ , D ₃ , D
₄ is input to the gate electrode, each source is connected to one end of the power supply, and drains are connected in parallel. Q ₁ , Q ₂ , Q ₃ , and Q ₄ are D ₁ , D ₂ , and D, respectively.
_3, ON in _{D 4} is '1', to OFF with '0'. 1 is Q
MOSFET group composed of ₁ , Q ₂ , Q ₃ and Q ₄ , S
Is a code input, 2 and 3 are NOR gates, 4 is an inverter, 6 is the other end of the power supply, 7 and 8 are the output terminals of the DA converter, 5 is a load represented by a speaker, 9 is Q ₁ , MOSFET group 1 composed of Q ₂ , Q ₃ and Q ₄
Is the drain output of. Q ₂ , Q ₃ , and Q ₄ are weighted with a channel width / channel length of 2 times, 4 times, and 8 times with respect to Q ₁ . The drain output 9 of the MOSFET group 1 is N
The sign input S for determining the current characteristic, which is connected to the inputs of the OR gates 2 and 3, has a gate electrode of Q ₈ , an inverter 4,
It is connected to an input of the OR gate 3, the output of NOR gate 2 to the gate electrode of Q5, the output of the NOR gate 3 to the gate electrode of Q _6, the output of Inbata 4 is connected to the gate electrode of Q _7. The source electrode and the drain electrode of Q ₅ are connected to 9 and 8. The source of Q ₅ is connected to 9, and the drain is connected to 7. The drain of Q ₇ is connected to the other end 6 of the power supply, and the source is connected to 8. The drain of Q ₈ is connected to the other end 6 of the power supply, and the source is connected to 7.

[0006] Q ₆ is ON when the S signal is "1", since the inverter 4 becomes "0", Q ₇ is OFF, NOR3 is Q ₆ since become "0" is turned OFF.

Reference numeral 10 shown in FIG. 2 (a) is a characteristic diagram showing the output voltage with respect to the input voltage of NOR2 or NOR3. Since the output from the inverter 4 is "0",
The output voltage of NOR2 depends on the input voltage from 9,
The 10 characteristics of (a) are shown. Forming a negative feedback loop NOR2 and _{Q 5.} When D ₁ , D ₂ , D ₃ and D ₄ are respectively “1”, “0”, “0” and “0”, Q1 is ON and Q
₂ , Q ₃ , and Q ₄ are turned off, and 11 shown in FIG.
The drain-ground voltage current I1 flows for _{Q 1} on the characteristic becomes VII, the output voltage of the NOR2 are shown in FIG. 2 (a)
It becomes V ₀₁ shown by. Since the gate voltage of Q ₅ becomes _{V 01} characteristic of _{Q 5} is a characteristic shown in 14 of FIG. 2 (b). Equilibrium occurs at the intersection of 11 and 14, and I
₁ flows _{Q 1} through _{Q 5, 5,} Q ₅ than 6. That is, the speaker 5 has a current I _{1 in} the direction from the terminal 7 to the terminal 8.
Flows. Q ₅ is OFF when the S signal is "0", the output of the inverter 4 becomes '1' _{Q 7} is ON, NOR2
Output becomes '0' and Q ₅ turns off. NOR3's
Characteristics are characteristics shown in 10 of FIG. 2 (a), the same operation as NOR2 when S signal is "1", to form a negative feedback loop NOR3 and Q _6, from the other end 6 of the power supply , Q
A current of I ₁ flows through Q ₁ , through 7, 5, and Q ₆ . That is, the current I ₁ is applied to the speaker 5 in the direction from the terminal 8 to the terminal 7.
Flowing.

[0008] 12 in FIG. 2 (b) shall be at current characteristic flowing to _{Q 4} when the D4 is "1" shows the 8 times the current characteristics 11. Characteristic 13 is D ₁ , D ₂ , D ₃ , D ₄
When all are '1', Q ₁ , Q ₂ , Q ₃ , and Q ₄ are all ON
It is assumed that the current that flows from 9 to the ground is shown by the characteristic obtained by summing the currents that are flowing during the operation, and that the current is 15 times the characteristic 11. Characteristic 15 shows a current characteristic flowing in Q ₅ when the S signal is “1”, and Q when the S signal is “0”.
₆ shows the characteristics of the current flowing in No. ₆ . When the S signal is "1", when _{the Q 1} is _{ON, Q 2, Q 3,} Q 4 is changed together in the state ON, the lower the impedance to ground from 9, V drain-ground voltage from _{V 11} since descends ₁₂ in the direction of the output voltage of the NOR2 rises from _{V 01} in the direction of the _{V 02,} the gate voltage of _{Q 5} rises to _{V 02} from _{V 01,} current characteristics of _{Q 5} is 2 ( Change from 14 in b) to 15. And the current I _{2 at} the intersection of 13 and 15
Flows from the other end 6 of the power supply through Q ₈ , 5, and Q ₅ . The potential of 9 at that time is V _12, which is a voltage slightly lower than V ₁₁ , and the NOR gate 2 and Q ₅ operate as a constant voltage circuit. Therefore, although I ₂ is a current slightly smaller than 15 I ₁ , it is almost 15 I ₁ .
Therefore, the current which is digital-analog converted by the weight input signal flows through the load 5 of the D / A converter represented by the speaker. Similarly, when the S signal is “0”, the NOR gate 3 and Q ₆ operate as a constant voltage circuit, and the current I _{2 at} the intersection of 13 and 15 flows from the other end 6 of the power supply through Q ₇ , 5, and Q _6. . The conventional current output type D / A converter is shown in FIG.
The MOSFETs corresponding to Q ₁ , Q ₂ , Q ₃ , and Q ₄ are used by utilizing the characteristics of the saturation region. Therefore, the gate voltage VG of the weighting transistors Q1 to Q4 is
Is smaller than the drain voltage VD of the parallel connection point 9 (VG
≤VD + VT). Otherwise, the transistors Q1 to Q4 shift to the non-saturation region operation, so that an accurate output cannot be obtained and the distortion rate becomes large. However, if the gate voltage VG is made lower than the drain voltage VD in order to reduce the distortion rate, the drain current flowing through each of the transistors Q1 to Q4 becomes small. For this reason, in the US, the size of the transistor is increased to secure the current supply capability, but the transistor area is increased by that amount, which is disadvantageous for the LSI.

On the other hand, the present invention uses the transistor Q1.
By operating Q4 in the non-saturation region, a large drain current is obtained with a small transistor size, and the drive capability is improved. However, here, the transistors Q1 to Q4
Is operated in the non-saturation region, the impedance of the transistors Q1 to Q4 changes when the drain voltage of the parallel connection point 9 is not made constant. Therefore, in the present invention, in order to make the potential of the parallel connection point 9 a constant voltage, this is negatively fed back to the gates of the transistors Q5 and Q6 via the gate circuits 2 and 3. Note that Q ₅ , Q ₆ , Q ₇ , and Q ₈ may be non-doped 1G FETs having a threshold voltage of around 0V.

[0010]

As described above, the switching transistors Q5 and Q6 are opened / closed using the gate circuits 2 and 3, and the gate circuits 2 and 3 are connected to the common connection point 9 of the current source transistors Q1 to Q4. Since the potential is fed back, the common connection point 9 can have a constant voltage ratio. As a result, the current source transistor can be operated in a specific saturation state, and the distortion rate can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

2A is a diagram showing an inverter characteristic, and FIG. 2B is an M diagram.
The current characteristic diagram of OSFET.

[Explanation of symbols]

Q ₁ , Q ₂ , Q ₃ , Q ₄ enhancement type 1GF
ET Q ₅ , Q ₆ , Q ₇ , Q ₈ 1GFET 4 Inverter 2, 3 NOR gate 1 MOSFET group 5 External load (speaker) D ₁ , D ₂ , D ₃ , D ₄ Weighted input signal S Code input 6 Other than power supply End 7,8 D / A converter output terminal 9 Drain electrode of MOSFET group 10 Inverter characteristics of NOR gates 2 and 3, 11, 12, 13, 14, 15 Current characteristics of MOSFET.

Claims (1)

[Claims] 1. A first terminal for which a constant voltage is required and an operating current.
A source connected between the second terminal to which the pressure is applied
Field effect transistor having drain current path and control
A first input terminal for receiving a signal, connected to the first terminal
Of the second input terminal and the field effect transistor
A gate circuit that has an output terminal connected to the gate
When the control signal is at the first logic level, the second
Specified at the output terminal regardless of the voltage level of the input terminal
Voltage is generated to turn off the field effect transistor.
And when the control signal is at the second logic level, the second
Generates a voltage at the output terminal according to the voltage at the input terminal of
Field effect Negative feedback loop for the transistor
And a gate circuit for controlling the control signal according to the second theory.
At the logic level, the negative feedback loop causes the second end to
Field effect transistor characterized by obtaining a constant voltage in the child
Star circuit.