JPH0342529B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bidirectional current output type digital-to-analog (DA) converter.

Conventional bidirectional current output type digital-to-analog (D-A) converters, which utilize the characteristics of the MOSFET's saturation region as a weighted current source, can directly connect speakers with an output of about 200 mW at a low voltage of about 2.5 V. To drive, set the channel width of the weight current source MOSFET and current polarity switching MOSFET to 5V.
It must be at least 4 times as large as when driving, and this D
-When incorporating an A converter into an LSI, the D-A converter occupies a large proportion of the LSI, resulting in a cost of 5V.
There was a drawback that the cost was significantly increased compared to the case where a D-A converter using a power supply was incorporated. Also, linearity distortion
There was a drawback that it was much worse than when operating at 5V.

The aim of the invention is to eliminate the above-mentioned drawbacks and to
It is an object of the present invention to provide a D-A converter that can directly drive a speaker at low voltage and obtain a large output with a small distortion factor.

The present invention is a weight current source that is turned ON or OFF by a weight input signal, and each is connected in parallel.
a MOSFET group, gate means having first and second inverter (inversion) characteristics to which the drain outputs of the MOSFET group and polarity switching signals of mutually opposite phases are input; the drains of the MOSFET group and D-A;
first and second terminals connected in parallel between the first and second output terminals of the converter, respectively;
MOSFET, the gate electrodes of the first and second MOSFETs are connected to the outputs of the first and second gate means, respectively, and the first gate means and the first MOSFET are connected to the outputs of the second gate means and the second MOSFET. 2 of
The drain of the MOSFET group is
By keeping the voltage between the source and source stable, the weighted current source MOSFET allows a current to flow stably even in the face of load fluctuations, and the third and fourth
The MOSFET is characterized in that the drains and sources of the third and fourth MOSFETs are connected to one end of the current and to the first and second output terminals of the DA converter, respectively.

FIG. 1 shows an embodiment of the present invention, in which Q ₁ , Q ₂ , Q ₃ ,
Q ₄ , Q ₅ , Q ₆ , Q ₇ , Q ₈ are enhancement types
Q ₁ , Q ₂ , Q ₃ , Q ₄ each have D-
Weight data inputs D ₁ , D ₂ , D ₃ , D ₄ of the A converter are input to the gate electrodes, each source is connected to one end of the power supply, and the drains are connected in parallel. Q ₁ , Q ₂ , Q ₃ , Q ₄ are D ₁ , respectively
When D ₂ , D ₃ , and D ₄ are "1", they are turned on, and when they are "0", they are turned off.
1 is a MOSFET group consisting of Q ₁ , Q ₂ , Q ₃ , Q ₄ ,
S is the sign input, 2 and 3 are NOR gates, 4 is the inverter, 6 is the other end of the power supply, 7 and 8 are each D
- The output terminal of the A converter, 5 is the load represented by the speaker, and 9 is composed of Q ₁ , Q ₂ , Q ₃ , and Q ₄
This is the drain output of MOSFET group 1. Q ₂ , Q ₃ ,
Q ₄ has channel width/channel length of 2 compared to Q ₁ .
The weights are given as 2x, 4x, and 8x. MOSFET
The drain output 1 of group 1 is connected to the inputs of NOR gates 2 and 3, and the sign input S determines the current polarity.
is connected to the gate electrode of _Q8 , inverter 4, and the input of NORB gate 3, and the output of NOR gate 2 is
The output of NOR gate 3 is connected to the gate electrode of Q ₅ , the output of NOR gate 3 is connected to the gate electrode of Q ₆ , and the output of inverter 4 is connected to the gate electrode of Q ₇ . The source electrode of Q ₅ is 9
The drain electrode is connected to 8. The source of Q ₆ is connected to 9 and the drain to 7.
The drain of Q ₇ is connected to the other end 6 of the power supply, and the source is connected to 8. The drain of Q ₈ is the other end of the power supply 6
, the source is connected to 7.

When the S signal is “1”, _Q8 is ON and inverter 4
becomes "0", so Q ₇ is OFF, and NOR3 becomes "0", so Q ₆ becomes OFF.

10 shown in Figure 2 a is NOR2 or
FIG. 3 is a characteristic diagram showing the output voltage with respect to the input voltage of NOR3. Since the output from inverter 4 is "0", the output voltage of NORP 2 depends on the input voltage from 9 and exhibits the characteristic of 10 in FIG. 2a.
NOR2 and _Q5 form a negative feedback loop. _D1 ,
D ₂ , D ₃ , D ₄ are “1”, “0”, “0”, “0” respectively
When , Q ₁ is ON, Q ₂ , Q ₃ , and Q ₄ are OFF, and a current of I ₁ on the 11 characteristics shown in Figure 2b flows, and QB ₁
The drain-to-ground voltage of NOR2 becomes V _I1 , and the output voltage of NOR2 becomes V _O1 as shown by a in FIG. _Q5
Since the gate voltage of is V _O1 , the characteristics of Q ₅ are shown in Figure 2.
This is the feature shown in 14 of b'. An equilibrium state occurs at the intersection of 11 and 14, and since I ₁ is 6, Q ₈ , 5,
Flows through _Q5 to _Q1 . In other words, current I ₁ flows through the speaker 5 in the direction from the terminal 7 to the terminal 8 . S
When the signal is "0", _Q8 is OFF, the output of inverter 4 is "1", so _Q7 is ON, the output of NOR2 is "0", and _Q5 is OFF. The characteristics of NOR3 are shown in 10 in Figure 2a, and it operates in the same way as NOR2 when the S signal is “1”.
and _Q6 form a negative feedback loop, and a current of _I1 flows from _the other end 6 of the power supply to Q1 through _Q7 , 5, and _Q6 .
In other words, current I ₁ flows through the speaker 5 from the terminal 8 to the terminal 7 .

Reference numeral 12 in FIG. 2b is the current characteristic flowing through _Q4 when _D4 is "1", and it is assumed that the current is 8 times that of characteristic 11. Characteristic 13 is the sum of the currents that flow when Q ₁ , Q ₂ , Q ₃ , and Q ₄ are all ON when D ₁ , D ₂ , D ₃ , and D ₄ are all “1,” and the current flows from 9 to ground. It is assumed that the current that flows is 15 times that of characteristic 11. Characteristic 15 shows the characteristics of the current flowing through Q5 when the S signal is " ₁ ", and the characteristics of the current flowing through _Q6 when the S signal is "0". When the S signal is “1”, Q ₁ is ON, Q ₂ , Q ₃ , Q ₄
When both change to the ON state, the impedance from 9 to ground decreases, and the drain-to-ground voltage increases.
Since the output voltage of NOR2 decreases from V ₁₁ to V _I2 , the output voltage of NOR2 increases from V _O1 to V _O2 , and the gate voltage of Q ₅ increases from V _O1 to V _O2 , so the current characteristics of Q ₅ changes from 14 to 15 in FIG. 2b. A current I ₂ at the intersection of 13 and 15 flows from the other end 6 of the power supply through Q ₅ , 5 and Q ₅ . At that time, the voltage at 9 is V _I2 , which is slightly lower than V _I1 , and operates as a constant voltage circuit with NOR gate 2 and _Q5 . Therefore, _I2 is approximately _15I2 , although the current is slightly smaller than _15I1 . Therefore, the current converted from digital to analog based on the weighted input signal flows to the load 5 of the D/A converter represented by the speaker. When the S signal is "1", the NOR gate 3 and _Q6 similarly operate as a constant voltage circuit, and the current _I2 at the intersection of 13 and 15 flows from the other end 6 of the power supply through _Q7 , 5, and _Q6 . . The conventional current output type D/A converter is Q ₁ , Q ₂ , Q ₃ , Q ₄ in Figure 1.
This method uses a MOSFET equivalent to , taking advantage of its characteristics in the saturation region. Therefore, the gate voltage VG of the weighting transistors Q1 to Q4 is smaller than the drain voltage VD of the parallel connection point 9 (VG≦VD
+VT). Otherwise, the transistors Q1 to Q4 will shift to non-saturation region operation, which will prevent accurate output from being obtained and increase the distortion rate. However, if the gate voltage VG is made lower than the drain voltage VD in an attempt to reduce the distortion factor, the drain current flowing through each transistor Q1 to Q4 becomes small, and the speaker 5
If you drive it enough, you will not be able to do it. For this reason, the conventional approach was to increase the size of the transistor to ensure drive capability, but this increased the area of the transistor, which was disadvantageous for LSI implementation.

In contrast, the present invention provides transistors Q1 to Q4
The device operates in the non-saturation region, obtains a large drain current with a small transistor size, and improves drive capability. However, since transistors Q1 to Q4 are operated in the non-saturation region,
Unless the drain voltage at the parallel connection point 9 is made constant, it will be affected by impedance fluctuations that occur when transistors Q1 to Q4 are switched. Therefore, in the present invention, in order to make the potential at the parallel connection point 9 a constant voltage, this is negatively fed back to the gates of the transistors Q5 and Q6 via the gate circuits 2 and 3. As a result, according to the present invention, a large output current can be obtained with a small transistor size, and a D-A converter with a low distortion factor can be obtained.

Furthermore, according to the present invention, means for making the parallel connection point constant voltage (NOR gates 2, 3, Q5, Q6)
Of these, transistors Q5 and Q6 also serve as part of the output switching transistors, achieving constant voltage with a small number of elements, and since no extra elements are required, the voltage drop is small and the speaker can be driven at low voltage. It is possible. Also, for the same output power
Since the channel width of the MOSFET can be reduced, the area occupied on the chip is reduced, which has the great effect of lowering costs. This effect is particularly great when operating at low voltage. Also, Q ₅ , Q ₆ , Q ₇ , and Q ₈ are non-dove type with threshold voltage near 0V.
An IGFET may also be used.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2a is a diagram showing inverter characteristics, and FIG. 2b is a MOSFET current characteristic diagram. Q ₁ , Q ₂ , Q ₃ , Q ₄ ...Enhancement type
IGFET, Q ₅ , Q ₆ , Q ₇ , Q ₈ ...IGFET, 4...
Inverter, 2, 3...NOR gate, 1...
MOSFET group, 5...external load (speaker),
D ₁ , D ₂ , D ₃ , D ₄ ... Weight signal input, S ... Sign input, 6 ... Other end of power supply, 7, 8 ... D/A converter output terminal, 9 ... Drain electrode of MOSFET group , 10... Inverter characteristics of NOR gates 2 and 3, 11, 12, 13, 14, 15...
MOSFET current characteristics.

Claims (1)

[Claims] 1 Channel length/channel width is weighted, multiple MOSFETs connected in parallel, and each
means for applying a weighted digital signal to the gates of the MOSFETs; and a first means connected between the parallel connection point of the MOSFETs and the first output terminal
a second MOSFET for switching connected between the MOSFET and the power supply and the second output terminal;
a third MOSFET for switching connected between the power supply and the first output terminal; a fourth MOSFET connected between the second output terminal and the parallel connection point; a signal input terminal,
the second MOSFET depending on the value of the code signal;
means for exclusively controlling opening and closing of the MOSFET and the third MOSFET; a first input terminal is supplied with the code signal, a second input terminal is connected to the parallel connection point, and an output terminal is connected to the It is connected to the gate terminal of MOSFET No. 4 so that when the code signal is at one level, the potential at the parallel connection point becomes a constant voltage, and when the code signal is at the other level, the potential at the parallel connection point becomes a constant voltage. The fourth MOSFET is turned off so that the fourth MOSFET is turned off.
a first gate circuit that controls the gate potential of the MOSFET; a first input terminal is supplied with an inverted output of the code signal; a second input terminal is connected to the parallel connection point; and an output terminal is connected to the parallel connection point; 1 MOSFET
is connected to the gate terminal of the first MOSFET, so that when the code signal is at one level, the first MOSFET is turned off, and when the code signal is at the other level, the potential at the parallel connection point is A second MOSFET that controls the gate potential of the first MOSFET to maintain a constant voltage.
A current output type D-A converter, comprising a gate circuit, and an analog output corresponding to a digital input value of the digital signal is generated at the first output terminal and the second output terminal. .