JPH07111299A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH07111299A JPH07111299A JP5257106A JP25710693A JPH07111299A JP H07111299 A JPH07111299 A JP H07111299A JP 5257106 A JP5257106 A JP 5257106A JP 25710693 A JP25710693 A JP 25710693A JP H07111299 A JPH07111299 A JP H07111299A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- sealing layer
- circuit chip
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、回路基板上に複数の半
導体集積回路チップ等を固定してなる混成集積回路に係
り、詳しくは、複数の接続端子を有する配線パターンを
備えた回路基板と、その上に固定される複数の半導体集
積回路チップと、これら半導体集積回路チップと接続端
子との間を電気的に接続するボンディングワイヤとを具
備する混成集積回路の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit in which a plurality of semiconductor integrated circuit chips and the like are fixed on a circuit board, and more specifically, a circuit board provided with a wiring pattern having a plurality of connection terminals. The present invention relates to an improvement of a hybrid integrated circuit including a plurality of semiconductor integrated circuit chips fixed thereon and a bonding wire for electrically connecting the semiconductor integrated circuit chip and the connection terminal.
【０００２】[0002]
【従来の技術】混成集積回路は、複数の接続端子を有す
る配線パターンを備えた回路基板上に、複数の半導体集
積回路チップと、これら半導体集積回路チップと接続端
子との間を電気的に接続するボンディングワイヤとを配
設し、更に、半導体集積回路チップの表面やボンディン
グワイヤの接続を保護する等のため、例えば特開昭５９
−２００４４２号公報に開示されているゲル状シリコー
ン樹脂とゴム状シリコーン樹脂とにより、半導体集積回
路チップやボンディングワイヤを被覆封止して形成され
る。2. Description of the Related Art A hybrid integrated circuit has a plurality of semiconductor integrated circuit chips and a plurality of semiconductor integrated circuit chips and the connection terminals electrically connected to each other on a circuit board having a wiring pattern having a plurality of connection terminals. And a bonding wire for protecting the surface of the semiconductor integrated circuit chip and the connection of the bonding wire.
It is formed by covering and sealing a semiconductor integrated circuit chip and a bonding wire with a gel-like silicone resin and a rubber-like silicone resin disclosed in Japanese Patent Publication No. 2004442.
【０００３】その為、混成集積回路は、半導体集積回路
チップを一つずつ回路基板上に搭載し、それをプリント
基板等の上に配置するのに比べ大幅に小型化が可能であ
り、それだけ半導体集積回路チップ間の容量ひいては信
号の遅延をする少なくすることができる。また、複合し
た機能を有する一つの大きい半導体集積回路チップを開
発するのではなく、それぞれの機能ごとに半導体集積回
路チップを開発し、また、場合によっては既存の半導体
集積回路チップを使用するので、開発が容易であり、そ
れだけ開発期間を短縮することができる。Therefore, the hybrid integrated circuit can be significantly downsized as compared with mounting the semiconductor integrated circuit chips one by one on a circuit board and arranging them on a printed circuit board or the like. It is possible to reduce the capacitance between the integrated circuit chips and thus the delay of the signal. Further, instead of developing one large semiconductor integrated circuit chip having a composite function, a semiconductor integrated circuit chip is developed for each function, and in some cases, an existing semiconductor integrated circuit chip is used, Development is easy and the development period can be shortened accordingly.
【０００４】しかしながら、回路基板上に複数の半導体
集積回路チップを近接に配置してそれらの搭載密度を向
上させた場合、隣合う半導体集積回路チップ間にノイズ
や静電誘導等が発生し、半導体集積回路チップが誤動作
する事があった。However, when a plurality of semiconductor integrated circuit chips are arranged close to each other on the circuit board to improve their mounting density, noise and electrostatic induction are generated between the adjacent semiconductor integrated circuit chips, and the semiconductor integrated circuit chips are adjacent to each other. The integrated circuit chip sometimes malfunctioned.
【０００５】そこで、そのような複数の半導体集積回路
チップ間のノイズや静電誘導等の発生を防止するものと
して、特開昭５６−７０６５６号公報の半導体集積回路
チップや特開昭６０−１４８１５８号公報の混成集積回
路が開示されている。Therefore, in order to prevent such noise and electrostatic induction between a plurality of semiconductor integrated circuit chips, a semiconductor integrated circuit chip disclosed in JP-A-56-70656 and JP-A-60-148158 is disclosed. The hybrid integrated circuit of the publication is disclosed.
【０００６】特開昭５６−７０６５６号公報には、金属
配線層上にパシベーション膜及び遮へい膜を配置し、こ
れにより静電気の帯電を防止し高い遮へい効果が得られ
る半導体集積回路チップ（半導体集積回路装置）が開示
されている。Japanese Unexamined Patent Publication No. 56-70656 discloses a semiconductor integrated circuit chip (semiconductor integrated circuit) in which a passivation film and a shielding film are arranged on a metal wiring layer to prevent static electricity from charging and to obtain a high shielding effect. Apparatus) is disclosed.
【０００７】しかしながら、この半導体集積回路チップ
を形成するためには、パシベーション膜の上に遮へい膜
を配置するための装置が必要であり、また、この半導体
集積回路チップを形成する工程はパシベーション膜のみ
を有する半導体集積回路チップのものと異なり複雑であ
る。更に、遮へい効果を半導体集積回路チップ自体に持
たせるため、遮へいが必要な半導体集積回路チップは全
て新たに形成しなければならず、混成集積回路に使用で
きる半導体集積回路チップの選択の幅が狭くなってしま
い、開発が容易でそれだけ開発期間を短縮することがで
きるという混成集積回路の利点を損なうことになってし
まう。However, in order to form this semiconductor integrated circuit chip, a device for arranging a shielding film on the passivation film is required, and the step of forming this semiconductor integrated circuit chip is performed only by the passivation film. It is complicated unlike a semiconductor integrated circuit chip having Further, since the semiconductor integrated circuit chip itself has a shielding effect, all the semiconductor integrated circuit chips that need shielding must be newly formed, and the selection range of the semiconductor integrated circuit chips that can be used in the hybrid integrated circuit is narrow. As a result, the advantage of the hybrid integrated circuit that the development is easy and the development period can be shortened accordingly is lost.
【０００８】特開昭６０−１４８１５８号公報には、回
路基板上に複数の半導体集積回路チップを搭載し、少な
くとも一つの半導体集積回路チップの周囲に導体ランド
を設け、前記半導体集積回路チップの上を覆う金属キャ
ップを取り付け、複数の半導体集積回路チップ間のノイ
ズ等を防止する混成集積回路が開示されている。In Japanese Patent Laid-Open No. 60-148158, a plurality of semiconductor integrated circuit chips are mounted on a circuit board, and a conductor land is provided around at least one semiconductor integrated circuit chip. There is disclosed a hybrid integrated circuit in which a metal cap covering the above is attached to prevent noise and the like between a plurality of semiconductor integrated circuit chips.
【０００９】しかしながら、この方法では、むき出しの
ボンディングワイヤと金属キャップとの接触を防止する
ために、金属キャップを余裕を持った大きさに形成する
と共に精度良く位置決めして固定する必要があり、半導
体集積回路チップの搭載密度を上げることができず、ま
た、金属キャップの位置決めをするため製造工程が複雑
になる。また、金属からなる金属キャップは不透明であ
るから、ボンディングワイヤの状態を目視検査すること
ができない。その為、小型でそれだけ半導体集積回路チ
ップ間の容量を少なくすることができるという混成集積
回路の利点を損なうことになってしまう。However, in this method, in order to prevent contact between the exposed bonding wire and the metal cap, it is necessary to form the metal cap with a sufficient size and to position and fix it with high precision. It is not possible to increase the mounting density of the integrated circuit chips, and the positioning of the metal cap complicates the manufacturing process. Moreover, since the metal cap made of metal is opaque, the state of the bonding wire cannot be visually inspected. Therefore, the advantage of the hybrid integrated circuit, which is small in size and can reduce the capacitance between the semiconductor integrated circuit chips, is lost.
【００１０】[0010]
【発明が解決しようとする課題】そこで、本発明者ら
は、このような従来の混成集積回路における問題点に鑑
み、既存の半導体集積回路チップをそのまま搭載でき、
隣合う複数の半導体集積回路チップの間を近接に配置し
て小型化でき、しかも、ノイズや静電誘導等により誤動
作しない混成集積回路を開発すべく鋭意研究を重ねた結
果、回路基板の上に複数の半導体集積回路チップとボン
ディングワイヤとを配設する混成集積回路において、各
半導体集積回路チップ等を絶縁性材料からなる第一の封
止層で覆い、更にこの第一の封止層を導電性材料からな
る第二の封止層で被覆することで解決できることを見出
し、本発明を完成した。Therefore, in view of such problems in the conventional hybrid integrated circuit, the present inventors can mount the existing semiconductor integrated circuit chip as it is,
As a result of intensive research to develop a hybrid integrated circuit that can be miniaturized by arranging adjacent semiconductor integrated circuit chips close to each other and that does not malfunction due to noise, electrostatic induction, etc., In a hybrid integrated circuit in which a plurality of semiconductor integrated circuit chips and bonding wires are arranged, each semiconductor integrated circuit chip or the like is covered with a first sealing layer made of an insulating material, and the first sealing layer is made conductive. The inventors have found that the problem can be solved by coating with a second sealing layer made of a conductive material, and completed the present invention.
【００１１】従って、本発明の目的は、開発の容易性や
小型化等の利点を損なうことなく誤動作を生じない混成
集積回路を提供することにある。また、ボンディングワ
イヤの状態を、それを固定した後で目視検査することが
できる混成集積回路を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a hybrid integrated circuit which does not cause a malfunction without spoiling advantages such as ease of development and downsizing. Another object of the present invention is to provide a hybrid integrated circuit capable of visually inspecting the state of the bonding wire after fixing it.
【００１２】[0012]
【課題を解決するための手段】すなわち、本発明は、複
数の接続端子を有する配線パターンを備えた回路基板
と、その上に固定される複数の半導体集積回路チップ
と、これら半導体集積回路チップと接続端子との間を電
気的に接続するボンディングワイヤとを具備する混成集
積回路において、各半導体集積回路チップとそれに接続
されるボンディングワイヤ及び接続端子とを絶縁性材料
からなる第一の封止層で覆うと共に、これら複数の半導
体集積回路チップの内少なくとも一つの半導体集積回路
チップについてはその第一の封止層を更に導電性材料か
らなる第二の封止層で被覆し、この第二の封止層を回路
基板の接地導体に接続する混成集積回路である。That is, the present invention provides a circuit board having a wiring pattern having a plurality of connection terminals, a plurality of semiconductor integrated circuit chips fixed thereon, and these semiconductor integrated circuit chips. In a hybrid integrated circuit including a bonding wire electrically connecting to a connection terminal, each semiconductor integrated circuit chip, and a bonding wire and a connection terminal connected to the semiconductor integrated circuit chip are formed of a first sealing layer made of an insulating material. And at least one semiconductor integrated circuit chip among these plurality of semiconductor integrated circuit chips, the first sealing layer is further covered with a second sealing layer made of a conductive material. It is a hybrid integrated circuit that connects a sealing layer to a ground conductor of a circuit board.
【００１３】本発明において、回路基板は、その上に積
層される複数の半導体集積回路チップを支持し、それら
複数の半導体集積回路チップの間又は半導体集積回路チ
ップと外部とを電気的に接続するための複数の接続端子
を有する配線パターンと、第二の封止層を接地するため
の接地導体とを備えていればよい。In the present invention, the circuit board supports a plurality of semiconductor integrated circuit chips stacked thereon and electrically connects between the plurality of semiconductor integrated circuit chips or between the semiconductor integrated circuit chip and the outside. It suffices to include a wiring pattern having a plurality of connection terminals and a ground conductor for grounding the second sealing layer.
【００１４】回路基板上に固定される半導体集積回路チ
ップは、それぞれ固有の機能実現する電気回路を内部に
有し、それが既存のものであっても、パシベーション膜
及び遮へい膜を有するものであってもよい。The semiconductor integrated circuit chip fixed on the circuit board has an electric circuit for realizing a unique function therein, and even if it is an existing one, it has a passivation film and a shielding film. May be.
【００１５】ボンディングワイヤは、半導体集積回路チ
ップの内部回路と回路基板の接続端子との間を電気的に
接続するものであり、通常用いられているものを使用で
きる。The bonding wire electrically connects the internal circuit of the semiconductor integrated circuit chip and the connection terminal of the circuit board, and a commonly used wire can be used.
【００１６】第一の封止層は、シリコン系の樹脂やエポ
キシ系の樹脂等の絶縁性材料からなり、半導体集積回路
チップとそれに接続されるボンディングワイヤ及び接続
端子とを覆うものである。また、第一の封止層を形成す
るための材料として透明又は半透明の材料を使用すれ
ば、第一の封止層を形成した後に外観を検査してボンデ
ィングワイヤの不良を発見でき、歩留りを向上させるこ
とができる。しかも、この第一の封止層を設けた段階で
混成集積回路の機能等の検査を行い不良チップの発見を
すれば、容易にその半導体集積回路チップの交換を行う
ことができるので、更に歩留りを向上させることができ
る。The first sealing layer is made of an insulating material such as a silicon resin or an epoxy resin and covers the semiconductor integrated circuit chip and the bonding wires and connection terminals connected thereto. In addition, if a transparent or semitransparent material is used as the material for forming the first sealing layer, the appearance can be inspected after the first sealing layer is formed and defects in the bonding wires can be found, and the yield can be improved. Can be improved. Moreover, if the defective chip is found by inspecting the function of the hybrid integrated circuit at the stage where the first sealing layer is provided, the semiconductor integrated circuit chip can be easily replaced, which further improves the yield. Can be improved.
【００１７】第二の封止層は、互いに隣接して配置され
る複数の半導体集積回路チップの内にノイズ等を発生す
るもの及びそのノイズ等より誤動作するものがある場
合、それらの間を遮蔽するために少なくともその一方に
設けられ、その為、当該半導体集積回路チップの第一の
封止層を被覆し、回路基板の接地導体に接続されるよう
に銅ペースト等の導電性材料を形成する。なお、銅ペー
ストは高いので必要な半導体集積回路チップのみを被覆
するようにすると安価に形成することができる。また、
この第二の封止層は、第一の封止層を形成してあるので
ボンディングワイヤ等は覆われており、また、ボンディ
ングワイヤは固定されているので高い位置決め精度を必
要としないので、滴下法や印刷等の簡単な方法で形成す
ることができる。The second sealing layer shields between a plurality of semiconductor integrated circuit chips arranged adjacent to each other that generate noise or the like and malfunction due to the noise or the like. Is provided on at least one of them, and therefore covers the first sealing layer of the semiconductor integrated circuit chip and forms a conductive material such as copper paste so as to be connected to the ground conductor of the circuit board. . Since the copper paste is expensive, it can be formed inexpensively by covering only the necessary semiconductor integrated circuit chip. Also,
The second sealing layer forms the first sealing layer so that the bonding wires and the like are covered, and since the bonding wires are fixed, high positioning accuracy is not required. It can be formed by a simple method such as a method or printing.
【００１８】なお、接地導体を半導体集積回路チップの
周りを囲うように形成し、第二の封止層が当該半導体集
積回路チップの周り全体において前記接地導体に接続す
るように形成すれば、当該半導体集積回路チップと他の
半導体集積回路チップとの間を効果的に遮蔽でき、その
効果を十分に発揮することができる。更に、半導体集積
回路チップの下の回路基板内に導体層と、前記導体層と
接地導体と接続し当該半導体集積回路チップの周りを囲
う層間接続電極とを形成し、半導体集積回路チップの下
面を遮蔽すれば、回路基板を介して当該半導体集積回路
チップに到達するノイズ等を防止することができる。If the ground conductor is formed so as to surround the semiconductor integrated circuit chip, and the second sealing layer is formed so as to be connected to the ground conductor around the entire semiconductor integrated circuit chip, The semiconductor integrated circuit chip and another semiconductor integrated circuit chip can be effectively shielded from each other, and the effect can be sufficiently exhibited. Further, a conductor layer and an interlayer connection electrode that is connected to the conductor layer and the ground conductor and surrounds the semiconductor integrated circuit chip are formed in the circuit board below the semiconductor integrated circuit chip, and the lower surface of the semiconductor integrated circuit chip is formed. The shielding can prevent noise or the like from reaching the semiconductor integrated circuit chip through the circuit board.
【００１９】[0019]
【作用】本発明においては、半導体集積回路チップを被
覆するように第一の封止層を設け、更に、その第一の封
止層を被覆するように導電性材料からなる第二の封止層
を形成したため、半導体集積回路チップ自体に何ら格別
の処理をすることなく、当該半導体集積回路チップとそ
の他の半導体集積回路チップとの間を遮蔽することがで
きる。その為、既存の半導体集積回路チップをそのまま
搭載して混成集積回路を形成することができ、使用でき
る半導体集積回路チップの選択の幅は変わらない。In the present invention, the first sealing layer is provided so as to cover the semiconductor integrated circuit chip, and the second sealing made of a conductive material is provided so as to cover the first sealing layer. Since the layers are formed, the semiconductor integrated circuit chip itself can be shielded from the other semiconductor integrated circuit chips without any special processing. Therefore, an existing semiconductor integrated circuit chip can be mounted as it is to form a hybrid integrated circuit, and the range of selection of usable semiconductor integrated circuit chips does not change.
【００２０】半導体集積回路チップの上に第二の封止層
を被覆形成する前に、第一の封止層により各半導体集積
回路チップやボンディングワイヤ等を被覆固定したた
め、第二の封止層とボンディングワイヤ等との間にそれ
らの間の接触を防止するための隙間を設ける必要が無い
ので、隣合う複数の半導体集積回路チップの間を格別に
空ける必要がない。Before forming the second sealing layer on the semiconductor integrated circuit chip by coating, the respective semiconductor integrated circuit chips, bonding wires, etc. are covered and fixed by the first sealing layer. Since it is not necessary to provide a gap for preventing the contact between them and the bonding wire or the like, it is not necessary to make a space between adjacent semiconductor integrated circuit chips.
【００２１】導電制材料からなる第二の封止層で必要な
半導体集積回路チップを被覆したため、当該半導体集積
回路チップは、外部にノイズを出さず、また、他の半導
体集積回路チップのノイズ等による誤動作を生じない。
また、当該半導体集積回路チップの周りを囲う接地導体
とその全体に接続されている第二の封止層とにより、導
電性材料で隙間なく当該半導体集積回路チップを包むこ
とができる。Since the necessary semiconductor integrated circuit chip is covered with the second sealing layer made of a conductive control material, the semiconductor integrated circuit chip does not emit noise to the outside, and noise of other semiconductor integrated circuit chips, etc. Does not cause malfunctions.
In addition, the grounding conductor surrounding the semiconductor integrated circuit chip and the second sealing layer connected to the entire surface of the semiconductor integrated circuit chip can wrap the semiconductor integrated circuit chip with no gap.
【００２２】なお、第二の封止層は、半導体集積回路チ
ップから混成集積回路の外部へのノイズ等の放出も防ぐ
ので、混成集積回路を搭載するシステムのノイズ低減対
策にも有効である。Since the second sealing layer also prevents noise and the like from being emitted from the semiconductor integrated circuit chip to the outside of the hybrid integrated circuit, it is also effective as a noise reduction measure for a system incorporating the hybrid integrated circuit.
【００２３】[0023]
【実施例】以下、添付図面を参照しながら、本発明の実
施例を説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００２４】図１には、本発明の実施例に係る混成集積
回路が示されている。この混成集積回路は、複数の接続
端子７を有する配線パターンとパワー用半導体集積回路
チップ１ａの周りを囲う接地導体５とが形成された回路
基板２上に、パワー用半導体集積回路チップ１ａとコン
トロール用半導体集積回路チップ１ｂとを固着し、ボン
ディングワイヤ６でそれぞれの半導体集積回路チップ１
ａ，１ｂと前記配線パターンの接続端子７とを接続し、
それぞれの半導体集積回路チップ１ａ，１ｂの上には第
一の封止層３ａ，３ｂを形成し、更に、パワー用半導体
集積回路チップ１ａの第一の封止層３ａの上には、その
周り全体において前記接地導体５に接続するように導電
性の第二の封止層４を形成してなる。FIG. 1 shows a hybrid integrated circuit according to an embodiment of the present invention. In this hybrid integrated circuit, a power semiconductor integrated circuit chip 1a and a control circuit are formed on a circuit board 2 on which a wiring pattern having a plurality of connection terminals 7 and a ground conductor 5 surrounding the power semiconductor integrated circuit chip 1a are formed. And the semiconductor integrated circuit chip 1b for use in the semiconductor integrated circuit chip 1b.
a, 1b and the connection terminal 7 of the wiring pattern are connected,
First sealing layers 3a and 3b are formed on the respective semiconductor integrated circuit chips 1a and 1b, and further, on the first sealing layer 3a of the power semiconductor integrated circuit chip 1a and around the first sealing layers 3a and 3b. A conductive second sealing layer 4 is formed so as to be connected to the ground conductor 5 as a whole.
【００２５】第一の封止層３ａ，３ｂは、透明な絶縁性
材料であるシリコン樹脂を使用して、ディスペンス法で
それぞれの半導体集積回路チップ１ａ，１ｂ上に形成し
た。そして、この第一の封止層３ａ，３ｂを形成した時
点でボンディングワイヤ６の状態を目視検査した所、ボ
ンディングワイヤ６同士の接触は無く、また、第一の封
止層３ａ，３ｂの表面から露出した部分も発見できなか
った。第二の封止層４は、銅ペーストを滴下法でパワー
用半導体集積回路チップ１ａの上に落として形成した。
そして、接地導体５との接触状態を調べた所、パワー用
半導体集積回路チップ１ａの周り全てにおいて接触して
おり、パワー用半導体集積回路チップ１ａは、第二の封
止層４及び接地導体５によって隙間なく遮蔽することが
できた。The first sealing layers 3a and 3b were formed on the respective semiconductor integrated circuit chips 1a and 1b by a dispensing method using a silicon resin which is a transparent insulating material. Then, when the state of the bonding wires 6 was visually inspected at the time when the first sealing layers 3a and 3b were formed, there was no contact between the bonding wires 6 and the surface of the first sealing layers 3a and 3b. I couldn't find the exposed part. The second sealing layer 4 was formed by dropping a copper paste on the power semiconductor integrated circuit chip 1a by a dropping method.
When the contact state with the ground conductor 5 is examined, it is in contact with the entire periphery of the power semiconductor integrated circuit chip 1a, and the power semiconductor integrated circuit chip 1a has the second sealing layer 4 and the ground conductor 5. It was possible to shield without a gap.
【００２６】このように形成した混成集積回路を動作さ
せたところ誤動作を生じることは無かった。When the hybrid integrated circuit thus formed was operated, no malfunction occurred.
【００２７】[0027]
【発明の効果】本発明によれば、半導体集積回路チップ
やボンディングワイヤ等を第一の封止層及び第二の封止
層で覆うことで、搭載する半導体集積回路チップに工夫
をこらすことなく、また、遮蔽のために隣合う複数の半
導体集積回路チップの間を格別に空ける必要もなく、同
一回路基板上に搭載される複数の半導体集積回路チップ
のノイズや静電誘導を防止し、開発の容易性や小型化等
の利点を損なうことなく誤動作を生じない混成集積回路
を提供することができる。According to the present invention, by covering the semiconductor integrated circuit chip, the bonding wire and the like with the first sealing layer and the second sealing layer, the semiconductor integrated circuit chip to be mounted can be made without any ingenuity. In addition, there is no need to make a space between adjacent semiconductor integrated circuit chips for shielding, and the noise and electrostatic induction of the semiconductor integrated circuit chips mounted on the same circuit board are prevented and developed. It is possible to provide a hybrid integrated circuit that does not cause malfunctions without impairing advantages such as ease of use and size reduction.
【００２８】また、ノイズや静電誘導を防止したい半導
体集積回路チップをその周りを囲う接地導体と第二の封
止層とで被覆したため、導電性材料で隙間なく当該半導
体集積回路チップを包み、ノイズや静電誘導の防止効果
をより確実なものにすることができる。Further, since the semiconductor integrated circuit chip whose noise and electrostatic induction are to be prevented is covered with the grounding conductor and the second sealing layer which surround it, the semiconductor integrated circuit chip is wrapped with a conductive material without any gap, The effect of preventing noise and electrostatic induction can be made more reliable.
【００２９】更に、第一の封止層に透明又は半透明の材
料を使用してボンディングワイヤ等を固定したため、第
二の封止層を形成する前に、目視検査でボンディングワ
イヤと半導体集積回路チップや接続端子との接触不良を
発見し修理することができるので、混成集積回路の歩留
りが向上する。Further, since the bonding wire or the like is fixed to the first sealing layer by using a transparent or translucent material, the bonding wire and the semiconductor integrated circuit are visually inspected before forming the second sealing layer. Since the poor contact with the chip or the connection terminal can be found and repaired, the yield of the hybrid integrated circuit is improved.
【図１】 本発明の実施例に係る混成集積回路の断面
図。FIG. 1 is a sectional view of a hybrid integrated circuit according to an embodiment of the present invention.
【図２】 本発明の実施例に係る混成集積回路の上面一
部切りかき図。FIG. 2 is a partially cutaway top view of a hybrid integrated circuit according to an embodiment of the present invention.
１ａ：パワー用半導体集積回路チップ、１ｂ：コントロ
ール用半導体集積回路チップ、２：回路基板、３ａ，３
ｂ：第一の封止層、４：第二の封止層、５：接地導体、
６：ボンディングワイヤ、７：接続端子。1a: power semiconductor integrated circuit chip, 1b: control semiconductor integrated circuit chip, 2: circuit board, 3a, 3
b: first sealing layer, 4: second sealing layer, 5: ground conductor,
6: bonding wire, 7: connection terminal.
Claims (3)
備えた回路基板と、その上に固定される複数の半導体集
積回路チップと、これら半導体集積回路チップと接続端
子との間を電気的に接続するボンディングワイヤとを具
備する混成集積回路において、各半導体集積回路チップ
とそれに接続されるボンディングワイヤ及び接続端子と
を絶縁性材料からなる第一の封止層で覆うと共に、これ
ら複数の半導体集積回路チップの内少なくとも一つの半
導体集積回路チップについてはその第一の封止層を更に
導電性材料からなる第二の封止層で被覆し、この第二の
封止層を回路基板の接地導体に接続したことを特徴とす
る混成集積回路。1. A circuit board having a wiring pattern having a plurality of connection terminals, a plurality of semiconductor integrated circuit chips fixed on the circuit board, and the semiconductor integrated circuit chips and the connection terminals are electrically connected. And a bonding wire and a connection terminal connected to the semiconductor integrated circuit chip are covered with a first sealing layer made of an insulating material, and the plurality of semiconductor integrated circuits are provided. For at least one semiconductor integrated circuit chip of the chips, the first sealing layer is further covered with a second sealing layer made of a conductive material, and the second sealing layer is used as a ground conductor of the circuit board. A hybrid integrated circuit characterized by being connected.
止層が配設される半導体集積回路チップの周りを囲うよ
うに形成され、第二の封止層が半導体集積回路チップの
周り全体において前記接地導体に接続されている請求項
第１項記載の混成集積回路。2. A grounding conductor is formed on a circuit board so as to surround a semiconductor integrated circuit chip on which a second sealing layer is disposed, and the second sealing layer covers the entire semiconductor integrated circuit chip. The hybrid integrated circuit according to claim 1, wherein the hybrid integrated circuit is connected to the ground conductor at.
材料で形成されている請求項第１項又は第２項に記載の
混成集積回路。3. The hybrid integrated circuit according to claim 1, wherein the first sealing layer is made of a transparent or semitransparent insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5257106A JPH07111299A (en) | 1993-10-14 | 1993-10-14 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5257106A JPH07111299A (en) | 1993-10-14 | 1993-10-14 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07111299A true JPH07111299A (en) | 1995-04-25 |
Family
ID=17301819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5257106A Pending JPH07111299A (en) | 1993-10-14 | 1993-10-14 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07111299A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09260552A (en) * | 1996-03-22 | 1997-10-03 | Nec Corp | Mounting structure of semiconductor chip |
| JPH11340257A (en) * | 1998-05-21 | 1999-12-10 | Hamamatsu Photonics Kk | Transparent resin-encapsulated optical semiconductor device |
| JP2000243871A (en) * | 1999-02-19 | 2000-09-08 | Towa Corp | Circuit board |
| JP2003502853A (en) * | 1999-06-23 | 2003-01-21 | エリクソン インコーポレイテッド | Gel structures for combined EMI shielding and thermal control of microelectronic assemblies |
| JP2004006973A (en) * | 2003-08-01 | 2004-01-08 | Kitagawa Ind Co Ltd | Structure and method for shielding electromagnetic wave |
| JP2004314292A (en) * | 2003-03-20 | 2004-11-11 | Robert Bosch Gmbh | Electromechanical system having controlled atmosphere. and method of manufacturing same |
| JP2007081370A (en) * | 2005-09-14 | 2007-03-29 | ▲イ▼統科技股▲分▼有限公司 | Package structure and its packaging method |
| JP2008288610A (en) * | 2008-07-17 | 2008-11-27 | Taiyo Yuden Co Ltd | Manufacturing method of circuit module |
| JP2015228422A (en) * | 2014-06-02 | 2015-12-17 | パナソニックＩｐマネジメント株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2019054216A (en) * | 2017-09-19 | 2019-04-04 | 東芝メモリ株式会社 | Semiconductor device |
| CN110277381A (en) * | 2018-03-15 | 2019-09-24 | 三星电子株式会社 | Semiconductor package assembly and a manufacturing method thereof |
| CN113614907A (en) * | 2019-04-05 | 2021-11-05 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
-
1993
- 1993-10-14 JP JP5257106A patent/JPH07111299A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09260552A (en) * | 1996-03-22 | 1997-10-03 | Nec Corp | Mounting structure of semiconductor chip |
| JPH11340257A (en) * | 1998-05-21 | 1999-12-10 | Hamamatsu Photonics Kk | Transparent resin-encapsulated optical semiconductor device |
| JP2000243871A (en) * | 1999-02-19 | 2000-09-08 | Towa Corp | Circuit board |
| JP2003502853A (en) * | 1999-06-23 | 2003-01-21 | エリクソン インコーポレイテッド | Gel structures for combined EMI shielding and thermal control of microelectronic assemblies |
| US8018077B2 (en) | 2003-03-20 | 2011-09-13 | Robert Bosch Gmbh | Electromechanical system having a controlled atmosphere, and method of fabricating same |
| JP2004314292A (en) * | 2003-03-20 | 2004-11-11 | Robert Bosch Gmbh | Electromechanical system having controlled atmosphere. and method of manufacturing same |
| US9771257B2 (en) | 2003-03-20 | 2017-09-26 | Robert Bosch Gmbh | Electromechanical system having a controlled atmosphere, and method of fabricating same |
| JP2004006973A (en) * | 2003-08-01 | 2004-01-08 | Kitagawa Ind Co Ltd | Structure and method for shielding electromagnetic wave |
| JP2007081370A (en) * | 2005-09-14 | 2007-03-29 | ▲イ▼統科技股▲分▼有限公司 | Package structure and its packaging method |
| JP2008288610A (en) * | 2008-07-17 | 2008-11-27 | Taiyo Yuden Co Ltd | Manufacturing method of circuit module |
| JP2015228422A (en) * | 2014-06-02 | 2015-12-17 | パナソニックＩｐマネジメント株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2019054216A (en) * | 2017-09-19 | 2019-04-04 | 東芝メモリ株式会社 | Semiconductor device |
| CN110277381A (en) * | 2018-03-15 | 2019-09-24 | 三星电子株式会社 | Semiconductor package assembly and a manufacturing method thereof |
| CN110277381B (en) * | 2018-03-15 | 2023-05-02 | 三星电子株式会社 | Semiconductor package and method for manufacturing the same |
| CN113614907A (en) * | 2019-04-05 | 2021-11-05 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
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