JPH0710953U - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH0710953U
JPH0710953U JP4363993U JP4363993U JPH0710953U JP H0710953 U JPH0710953 U JP H0710953U JP 4363993 U JP4363993 U JP 4363993U JP 4363993 U JP4363993 U JP 4363993U JP H0710953 U JPH0710953 U JP H0710953U
Authority
JP
Japan
Prior art keywords
external leads
support plates
lead
support plate
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4363993U
Other languages
Japanese (ja)
Other versions
JP2577640Y2 (en
Inventor
和美 高畠
定雄 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP4363993U priority Critical patent/JP2577640Y2/en
Publication of JPH0710953U publication Critical patent/JPH0710953U/en
Application granted granted Critical
Publication of JP2577640Y2 publication Critical patent/JP2577640Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 複数の半導体チップを支持するために複数の
支持板に対して不要な外力が及ぶことを阻止することが
できるリードフレームを提供する。 【構成】 リードフレームは複数のチップ14、15、
16を支持する複数の支持板11、12、13と、複数
の外部リード17a〜17hと、タイバー22と、連結
条23との他に、配線用枠状部18を有する。配線用枠
状部18は2本の外部リード17d、17eで安定的に
支持されて複数の支持板11、12、13を包囲してい
る。複数の配線用枠状部18には突出部分19a、19
bが設けられ、ここにリード細線20がボンディングさ
れている。
(57) [Summary] [Object] To provide a lead frame capable of preventing an unnecessary external force from being applied to a plurality of support plates for supporting a plurality of semiconductor chips. [Construction] The lead frame is composed of a plurality of chips 14, 15,
In addition to the plurality of support plates 11, 12, and 13 that support 16, the plurality of external leads 17a to 17h, the tie bar 22, and the connecting strip 23, the wiring frame-shaped portion 18 is provided. The wiring frame-shaped portion 18 is stably supported by the two external leads 17d and 17e and surrounds the plurality of support plates 11, 12, and 13. The plurality of wiring frame-shaped portions 18 have protruding portions 19a, 19
b is provided, and the thin lead wire 20 is bonded thereto.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は混成集積回路等の半導体装置を製作する際に使用するリードフレーム に関する。 The present invention relates to a lead frame used when manufacturing a semiconductor device such as a hybrid integrated circuit.

【0002】[0002]

【従来の技術】[Prior art]

電力用半導体チップとこれを制御するモノリシックICチップとを一体に樹脂 封止した半導体装置を図3に示すように構成することは公知である。図3におい て、1、2、3は互いに離間するように並置されたチップ支持板、4、5はパワ ートランジスタチップ、6はモノリシックICチップ、7は外部リード、8はチ ップ相互間及びチップと外部リード間を接続するリード細線、9は樹脂封止体で ある。 It is known to construct a semiconductor device in which a power semiconductor chip and a monolithic IC chip for controlling the same are resin-sealed as shown in FIG. In FIG. 3, 1, 2 and 3 are chip supporting plates arranged side by side so as to be separated from each other, 4 and 5 are power transistor chips, 6 is a monolithic IC chip, 7 is an external lead, and 8 is between chips. Also, a lead thin wire connecting between the chip and the external lead, and 9 is a resin sealing body.

【0003】[0003]

【考案が解決しようとする課題】[Problems to be solved by the device]

図3の半導体装置は、支持板1、2、3と外部リード7とから構成されるリー ドフレームにチップ4、5、6をダイボンディングし、リード細線8をワイヤボ ンディングしてリードフレーム組立体を形成し、これをモールド金型に配置して 周知のトランスファーモ−ルドを行うことによって樹脂封止体9を形成すること によって得られる。 ところが、リードフレーム組立体を搬送するときに支持板に外力が加わってリ ード細線が支持板等に接触したり破断したりすることがあった。 The semiconductor device shown in FIG. 3 is a lead frame assembly in which chips 4, 5, and 6 are die-bonded to a lead frame composed of support plates 1, 2, and 3 and external leads 7, and lead fine wires 8 are wire-bonded. Is formed, and is placed in a molding die to perform a well-known transfer molding to form the resin encapsulant 9. However, when the lead frame assembly is transported, an external force may be applied to the support plate, and the lead thin wire may come into contact with the support plate or break.

【0004】 そこで、本考案は、半導体装置の組立及び樹脂封止を安定的に進めることがで きるリードフレームを提供することにある。Therefore, the present invention is to provide a lead frame capable of stably advancing the assembly and resin sealing of a semiconductor device.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

上記目的を達成するための本考案は、第1の方向において互いに並置され且つ 回路部品を支持するように形成された複数の支持板と、前記第1の方向に直交す る第2の方向にのびて互いに並置され、且つ前記複数の支持板に連結された複数 の連結外部リードと、前記複数の支持板に対して直接に連結されないで前記連結 外部リードに対して並置された複数の支持板非連結外部リードと、前記複数の連 結外部リード及び前記複数の支持板非連結外部リードを相互に連結し且つ前記第 1の方向に帯状に延びている連結条とを備えたリードフレームにおいて、前記複 数の連結外部リード及び前記複数の支持板非連結外部リードから成る複数の外部 リードの配列の一方の端に前記複数の支持板非連結外部リードの1つが配置され 、前記複数の外部リードの配列の他方の端に前記複数の支持板非連結外部リード の別の1つが配置され、全体として略コ字状の平面パターンを有して前記複数の 支持板の配列の3方向を囲むように配置され且つ前記一方及び他方の端の支持板 非連結外部リードに連結された配線用枠状部が設けられているリードフレームに 係わるものである。 なお、請求項2に示すように配線用枠状部に支持板方向に突出する部分を設け ることが望ましい。 また、請求項3に示すように複数の支持板間の隙間及び配線用枠状部と支持板 との間の隙間をほぼ同一にすることが望ましい。 The present invention for achieving the above object includes a plurality of support plates arranged in parallel in a first direction so as to support circuit components, and a plurality of support plates in a second direction orthogonal to the first direction. A plurality of connecting external leads that are extended and juxtaposed to each other and connected to the plurality of supporting plates, and a plurality of supporting plates that are juxtaposed to the connecting external leads without being directly connected to the plurality of supporting plates. A lead frame comprising: a non-connecting external lead; and a connecting strip connecting the plurality of connecting external leads and the plurality of support plate non-connecting external leads to each other and extending in a strip shape in the first direction, One of the plurality of supporting plate non-connecting external leads is disposed at one end of an array of a plurality of external leads including the plurality of connecting external leads and the plurality of supporting plate non-connecting external leads. Another one of the plurality of support plate non-coupling external leads is arranged at the other end of the lead array, and has a generally U-shaped plane pattern as a whole to surround three directions of the array of the plurality of support plates. The present invention relates to a lead frame provided with a frame portion for wiring which is arranged as described above and is connected to the support plate non-connecting external leads at the one and the other ends. It is desirable that the wiring frame-shaped portion be provided with a portion projecting toward the support plate. Further, as described in claim 3, it is desirable that the gap between the plurality of support plates and the gap between the wiring frame-shaped portion and the support plate are substantially the same.

【0006】[0006]

【考案の作用及び効果】[Operation and effect of the device]

本考案の配線用枠状部は全体として略コ字状に形成され、一方及び他方の端の 支持板非連結外部リードに連結されているので、機械的に安定している。従って 、ここに組立又は樹脂封止時に外力が加わっても変形し難い。支持板は変形し難 い配線用枠状部に囲まれているので、ここに外力が不要に及ぶことが防止され、 組立及び樹脂封止を安定的に進めることができ、信頼性の高い半導体装置を提供 することができる。 また、請求項2に示すように配線用枠状部に突出部分を設けると、配線用枠状 部と回路部品(チップ又は回路基板)とのリード細線による接続距離を小さくす ることが可能になり、リード細線の垂れによる不良発生を防止することができる 。 また、請求項3に示すように、各部の隙間をほぼ同一にすると、樹脂の流れの 均一化を図ることができる。 The wiring frame-shaped portion of the present invention is formed in a substantially U-shape as a whole, and is mechanically stable because it is connected to the support plate non-connecting external leads at one end and the other end. Therefore, it is difficult to deform even if an external force is applied here during assembly or resin sealing. Since the support plate is surrounded by the wiring frame that is difficult to deform, external force is prevented from unnecessarily exerting on it, and assembly and resin sealing can proceed in a stable manner. A device can be provided. Further, when the wiring frame-shaped portion is provided with the projecting portion as described in claim 2, it is possible to reduce a connection distance between the wiring frame-shaped portion and the circuit component (chip or circuit board) by the fine lead wire. Therefore, it is possible to prevent the occurrence of defects due to the drooping of the fine lead wires. Further, as described in claim 3, by making the gaps of the respective parts substantially the same, it is possible to make the flow of the resin uniform.

【0007】[0007]

【実施例】【Example】

次に、図1及び図2を参照して本考案の実施例に係わるリードフレーム及びこ れを使用した半導体装置を説明する。 Next, a lead frame and a semiconductor device using the same according to an embodiment of the present invention will be described with reference to FIGS.

【0008】 樹脂封止前のリードフレームと半導体チップ(回路部品)との組立体を示す図 1において、11、12、13は第1、第2及び第3の支持板、14、15は回 路部品としてのパワートランジスタチップ、16は回路部品としてのモノリシッ クICチップ、17は外部リード、18は配線用枠状部、19a、19bは配線 用突出部分、20はリード細線、22はタイバー、23は連結条である。図1の チップ14、15、16とリード細線20を除いた部分が金属製リードフレーム である。図1には1個分の半導体装置に対応する部分のみが示されているが、実 際にはタイバー22及び連結条23によって更に多くの半導体装置を構成する部 分が連結されている。In FIG. 1, which shows an assembly of a lead frame and a semiconductor chip (circuit component) before resin sealing, 11, 12, 13 are first, second and third supporting plates, and 14, 15 are rotating members. A power transistor chip as a path component, 16 a monolithic IC chip as a circuit component, 17 an external lead, 18 a wiring frame portion, 19a and 19b a wiring protrusion, 20 a thin lead wire, 22 a tie bar, 23 is a connection article. A portion excluding the chips 14, 15 and 16 and the thin lead wire 20 in FIG. 1 is a metal lead frame. Although only a portion corresponding to one semiconductor device is shown in FIG. 1, in reality, more components constituting a semiconductor device are connected by the tie bar 22 and the connecting strip 23.

【0009】 第1、第2及び第3の支持板11、12、13は図1において横方向(第1の 方向)に互いに並置されている。外部リード17は、第1、第2及び第3の支持 板11、12、13に連結された支持板連結外部リード17a、17b、17c と、支持板11、12、13には直接に連結されていない支持板非連結外部リー ド17d、17e、17f、17g、17hとから成る。外部リード17a〜1 7hは互いに並置され、図1で縦方向(第2の方向)に延びている。タイバー2 2及び連結条23は横方向に延びて外部リード17a〜17hを相互に連結して いる。The first, second and third support plates 11, 12 and 13 are arranged side by side in the lateral direction (first direction) in FIG. The outer leads 17 are directly connected to the support plates 11, 12, and 13 and the support plate connecting outer leads 17a, 17b, and 17c connected to the first, second, and third support plates 11, 12, and 13. The outer leads 17d, 17e, 17f, 17g, and 17h are not connected to the support plate. The external leads 17a to 17h are juxtaposed to each other and extend in the vertical direction (second direction) in FIG. The tie bar 22 and the connecting strip 23 extend laterally to connect the external leads 17a to 17h to each other.

【0010】 配線用枠状部18は全体として略コ字状であり、第1、第2及び第3の支持板 11、12、13を囲むように配置されている。即ち、配線用枠状部18は支持 板11、12、13の配列の両側に配置された第1及び第2の部分18a、18 bと、支持板11、12、13の上側に配置された第3の部分18cとを有して 支持板11、12、13の配列の3方向を包囲している。この配線用枠状部18 には外部リード17a〜17hの配列の一方及び他方の端に配置された支持板非 連結外部リード17d、17eが連結されている。配線用枠状部18の第1及び 第2の部分18a、18bには第1及び第2の支持板11、12の方向に突出し た部分19a、19bが設けられている。配線用枠状部18と各支持板11、1 2、13との間の隙間24の幅及び支持板11、12、13の相互間の隙間25 の幅はほぼ同一に設定されている。また、隙間24は角部が生じない曲率を有し て屈曲したパターンを有する。The wiring frame-shaped portion 18 has a substantially U-shape as a whole, and is arranged so as to surround the first, second and third support plates 11, 12, 13. That is, the wiring frame-shaped portion 18 is arranged above the support plates 11, 12, 13 and the first and second portions 18a, 18b arranged on both sides of the arrangement of the support plates 11, 12, 13. The third portion 18c is provided to surround the arrangement of the support plates 11, 12, and 13 in three directions. The wiring frame-like portion 18 is connected to support plate non-connecting external leads 17d and 17e arranged at one end and the other end of the array of external leads 17a to 17h. The first and second portions 18a, 18b of the wiring frame portion 18 are provided with portions 19a, 19b projecting toward the first and second support plates 11, 12. The width of the gap 24 between the wiring frame-shaped portion 18 and each of the support plates 11, 12, and 13 and the width of the gap 25 between the support plates 11, 12, and 13 are set to be substantially the same. Further, the gap 24 has a bent pattern having a curvature that does not cause a corner.

【0011】 パワートランジスタチップ14、15は第1及び第2の支持板11、12に半 田で固着され、これを制御するためのモノリシックICチップ16は第3の支持 板13に固着されている。チップ14、15、16の相互間及びチップ14、1 5、16と外部リード17c、17f、17g、17h、突出部分19a、19 bとの間がリード細線20によって接続されている。なお、リード細線20によ る接続は周知のワイヤボンディング方法で行われている。The power transistor chips 14 and 15 are fixed to the first and second support plates 11 and 12 in a half-pad, and the monolithic IC chip 16 for controlling them is fixed to the third support plate 13. . The leads 14, 15 and 16 are connected to each other and the leads 14, 15 and 16 and the external leads 17c, 17f, 17g and 17h and the protruding portions 19a and 19b are connected to each other by a lead wire 20. The connection with the thin lead wire 20 is performed by a known wire bonding method.

【0012】 図2に示す樹脂封止体21を形成する際には、図1に示すリードフレーム組立 体を周知のトランスファモールドの金型に配置し、樹脂封止体21に対応する成 形空所(キャビティ)に流動樹脂を注入する。支持板1、12、13、外部リー ド17の一部、及び配線用枠状部18の表面側及び裏面側を覆うように樹脂封止 体21を形成する。しかる後、タイバー22及び連結条23を切断除去して図2 に示す半導体装置を完成させる。When forming the resin encapsulant 21 shown in FIG. 2, the lead frame assembly shown in FIG. 1 is placed in a well-known transfer mold, and a molding space corresponding to the resin encapsulant 21 is formed. Inject fluid resin into the cavity. The resin sealing body 21 is formed so as to cover the support plates 1, 12, 13 and a part of the external lead 17, and the front surface side and the back surface side of the wiring frame-shaped portion 18. After that, the tie bar 22 and the connecting strip 23 are cut and removed to complete the semiconductor device shown in FIG.

【0013】 リードフレームを本実施例に示すように構成すると、複数の支持板11、12 、13が配線用枠状部18によって包囲されているので、支持板11、12、1 3に不要な外力が加わることが防止され、リード細線20の支持板11、12、 13への接触やリード細線20の切断が防止される。なお、配線用枠状部18は 外部リード17d、17eによって両持ち支持されているので、外力によって変 形し難い。 また、配線用枠状部18に突出部分19a、19bが設けられ、ここにリード 細線20がボンディングされているので、チップ14、15と突出部分19a、 19bとの距離が短くなり、リード細線20の垂れ下りによる誤った接続を防ぐ ことができる。 また、配線用枠状部18と支持板11、12、13との間の隙間24及び支持 板11、12、13の相互間の隙間25がほぼ同一幅であり、且つ隙間24が曲 率を有して屈曲しているので、樹脂封止体21を形成する際の流動樹脂の流れを 均一化し、良好な樹脂封止体を形成することができる。When the lead frame is constructed as shown in this embodiment, since the plurality of support plates 11, 12, 13 are surrounded by the wiring frame-shaped portion 18, the support plates 11, 12, 13 are not required. External force is prevented from being applied, and contact of the thin lead wires 20 with the support plates 11, 12, 13 and cutting of the thin lead wires 20 are prevented. Since the wiring frame-shaped portion 18 is supported on both sides by the external leads 17d and 17e, it is difficult to be deformed by an external force. Further, since the wiring frame-shaped portion 18 is provided with the projecting portions 19a and 19b and the lead thin wire 20 is bonded thereto, the distance between the chips 14 and 15 and the projecting portions 19a and 19b becomes short, and the lead thin wire 20 is formed. It is possible to prevent incorrect connection due to drooping. Further, the gap 24 between the wiring frame-shaped portion 18 and the support plates 11, 12, and 13 and the gap 25 between the support plates 11, 12, and 13 have substantially the same width, and the gap 24 has a high curvature. Since the resin encapsulating body is bent, the flow of the flowing resin when forming the resin encapsulating body 21 can be made uniform, and a good resin encapsulating body can be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の実施例のリードフレーム組立体を示す
平面図である。
FIG. 1 is a plan view showing a lead frame assembly according to an embodiment of the present invention.

【図2】図1の組立体を使用して作った半導体装置を示
す平面図である。
FIG. 2 is a plan view showing a semiconductor device manufactured by using the assembly of FIG.

【図3】従来の半導体装置を示す平面図である。FIG. 3 is a plan view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

11、12、13 支持板 14、15、16 チップ 17 外部リード 18 配線用枠状部 11, 12, 13 Support plate 14, 15, 16 Chip 17 External lead 18 Frame part for wiring

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 第1の方向において互いに並置され且つ
回路部品を支持するように形成された複数の支持板と、 前記第1の方向に直交する第2の方向にのびて互いに並
置され、且つ前記複数の支持板に連結された複数の連結
外部リードと、 前記複数の支持板に対して直接に連結されないで前記連
結外部リードに対して並置された複数の支持板非連結外
部リードと、 前記複数の連結外部リード及び前記複数の支持板非連結
外部リードを相互に連結し且つ前記第1の方向に帯状に
延びている連結条とを備えたリードフレームにおいて、 前記複数の連結外部リード及び前記複数の支持板非連結
外部リードから成る複数の外部リードの配列の一方の端
に前記複数の支持板非連結外部リードの1つが配置さ
れ、前記複数の外部リードの配列の他方の端に前記複数
の支持板非連結外部リードの別の1つが配置され、 全体として略コ字状の平面パターンを有して前記複数の
支持板の配列の3方向を囲むように配置され且つ前記一
方及び他方の端の支持板非連結外部リードに連結された
配線用枠状部が設けられていることを特徴とするリード
フレーム。
1. A plurality of support plates arranged in parallel in a first direction and formed to support a circuit component, and arranged in parallel in a second direction orthogonal to the first direction, and A plurality of connection external leads connected to the plurality of support plates; a plurality of support plate non-connection external leads juxtaposed to the connection external leads without being directly connected to the plurality of support plates; A lead frame comprising a plurality of connection external leads and a plurality of support plate non-connection external leads which are connected to each other and which extend in a strip shape in the first direction, wherein the plurality of connection external leads and the connection external lead One of the plurality of support plate non-connecting external leads is arranged at one end of an array of a plurality of external leads formed of a plurality of support plate non-connecting external leads, and the other end of the array of the plurality of external leads is arranged. Another one of the plurality of support plate non-coupling external leads is arranged, and has a generally U-shaped planar pattern as a whole so as to surround three directions of the arrangement of the plurality of support plates and A lead frame, wherein a wiring frame-like portion connected to a support plate non-connection external lead at the other end is provided.
【請求項2】 前記配線用枠状部は、前記支持板の方向
に突出する部分を有していることを特徴とする請求項1
記載のリードフレーム。
2. The wiring frame-shaped portion has a portion projecting toward the support plate.
Lead frame as described.
【請求項3】 前記複数の支持板間の隙間及び前記配線
用枠状部と前記複数の支持板との間の隙間がほぼ同一で
あることを特徴とする請求項1又は2記載のリードフレ
ーム。
3. The lead frame according to claim 1, wherein a gap between the plurality of support plates and a gap between the wiring frame-shaped portion and the plurality of support plates are substantially the same. .
JP4363993U 1993-07-14 1993-07-14 Lead frame Expired - Fee Related JP2577640Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4363993U JP2577640Y2 (en) 1993-07-14 1993-07-14 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4363993U JP2577640Y2 (en) 1993-07-14 1993-07-14 Lead frame

Publications (2)

Publication Number Publication Date
JPH0710953U true JPH0710953U (en) 1995-02-14
JP2577640Y2 JP2577640Y2 (en) 1998-07-30

Family

ID=12669446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4363993U Expired - Fee Related JP2577640Y2 (en) 1993-07-14 1993-07-14 Lead frame

Country Status (1)

Country Link
JP (1) JP2577640Y2 (en)

Also Published As

Publication number Publication date
JP2577640Y2 (en) 1998-07-30

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