JPH07105434B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a manufacturing method suitable for separating element regions in a semiconductor integrated circuit.

2. Description of the Related Art Conventionally, a selective oxidation method has been widely used as a technique for separating element regions in a MIS type semiconductor integrated circuit. This method is LO
This is called the COS (Local Oxidation of Silicon) method, in which a mask of an oxidation resistant material such as a silicon nitride film is formed on a semiconductor substrate, and a thick silicon oxide film is grown on a portion not covered with the oxidation resistant material to form an isolation region. It is what In recent years, there has been proposed a selective oxidation technique which is an improvement of the LOCOS method and is applicable to a fine pattern of about 1 micron (for example, Japanese Patent Publication No. 58-49027).

In the above selective oxidation method, a channel stop region is provided under the thick silicon oxide film in order to increase the threshold voltage of the parasitic transistor.

Problems to be Solved by the Invention Impurities for forming a channel stop region are previously introduced into a substrate surface by an ion implantation method after patterning an oxidation resistant material. For this reason, the channel stop impurity diffuses into the element region due to the acceleration effect and heat effect during the growth of the isolation silicon oxide film. Due to this phenomenon, a narrow channel effect occurs and the gate width becomes shorter than the actual size. Further, in the case of a separation width of about 1 micron, with the conventional implantation amount (about 1 × 10 ¹³ cm ^-2 ), the breakdown voltage between the element regions becomes 5 V or less, and good separation characteristics cannot be obtained. Therefore, the injection volume must be increased,
As the concentration increases, the diffusion becomes longer and the narrow channel effect becomes noticeable. As described above, the formation of the channel stop region is a major obstacle to miniaturization.

Means for Solving the Problems In order to solve the above problems, in the present invention, a concentration difference and a depth difference are provided in the diffusion region for channel stop by the first implantation step and the second implantation step. First, a first channel stop impurity is implanted into the entire isolation region by the first implantation step. Then, after covering a predetermined region at the end of the separation region with a material that can serve as a mask for implantation, a second implantation process is performed to form a second region at a region other than the predetermined region at the end of the isolation region, that is, at the center position of the separation region. Impurities for channel stop are implanted. The first channel stop region is
In order to prevent the formation of the inversion layer under the isolation silicon oxide film, the depletion layer regions of the source and drain of the second channel stop region are located at deep positions below the interface between the isolation silicon oxide film and the silicon substrate. This prevents the punch-through phenomenon caused by the collision of the two.

Further, in the present invention, the second implantation amount is made larger than the first implantation amount, and the acceleration voltage of the second implantation is made larger than the acceleration voltage of the first implantation. Will increase.

One of the advantages of the selective oxidation method is that the channel stop impurities can be injected in a self-aligned manner. In the present invention, the first implantation step is self-aligned, using the resist as a mask for implantation as in the conventional case. Also for the second implantation step, the resist that is also the mask for the first implantation is
Heat treatment at a temperature of ℃ ~ 210 ℃ for about 30 minutes, soften and extend to form a shape that covers a predetermined area of the end of the separation area.
According to the method used as a mask for the implantation of Si, it becomes easily self-aligning.

Effect According to the present invention, the first channel stop layer formed by the first implantation prevents the formation of the inversion layer at the interface, and the second channel stop layer formed by the second implantation causes the formation of the lower layer below the interface. It is possible to prevent punch-through in. Since the first implantation amount may be relatively thin, it is possible to cause the narrow channel effect due to the lateral diffusion of the channel stop region. Therefore, for example, even if the element isolation width is 1 micron or less, isolation by the selective oxidation method is possible. Furthermore, since the first and second implants can be performed in a self-aligned manner, they are not limited by photolithography and can be sufficiently applied to a fine pattern.

Embodiment FIG. 1 is a sectional view of a typical semiconductor device formed by a manufacturing method according to an embodiment of the present invention. This semiconductor device
A silicon dioxide film 2 is formed in a predetermined region of the silicon substrate 1 by the LOCOS method, and a shallow and low-concentration first channel stop layer 3 is formed immediately below the silicon dioxide film 2 and near the center position. Therefore, the second channel stop layer 4 having a deep and high concentration is provided. In each of the first and second channel stop layers 3 and 4, before the step of forming the silicon dioxide film 2 formed by the LOCOS method, an appropriate amount of impurity ions are implanted by the ion implantation method in advance, It is formed by diffusing this in the process of implementing the LOCOS method.

FIGS. 2A to 2I are process sectional views when the present invention is applied to the LOCOS method. Below, according to FIG.
1 shows an embodiment of the present invention.

A silicon oxide film 6 for stress relaxation is formed on the P-type silicon substrate 5.
Of about 500 Å, and a silicon nitride film 7 as an oxidation resistant material is formed on this for about 2000 Å. Then, a resist 8 having a thickness of about 1.4 μm is applied, and nitridation of the isolation formation region is performed using a known photoetching technique. The silicon film 7 is removed as shown in FIG. Then, as shown in FIG. 2B, the resist 8 is used as a mask and boron ions 9 are added at 40 KeV,
Implantation is performed under the condition of 5 × 10 ¹² atom / cm ² to form the first implantation layer 10 as shown in FIG. 2 (c).

At this time, heat treatment is performed at 200 ° C. for 30 minutes to soften and extend the resist 8 to the separation formation region as shown in FIG. In this embodiment, the lateral extension of the resist 8 is 0.25 μm on one side, but the lateral extension length can be controlled by appropriately selecting the heat treatment conditions. Then
Again using the resist 8 as a mask, boron ions 11 are implanted under the conditions of 60 KeV, 1.5 × 10 ¹³ atom / cm ² as shown in FIG. 2 (e), and as shown in FIG. 2 (f), The second injection layer 12 is formed. Then, as shown in FIG. 2G, the resist 8 is removed, the first implantation layer 10 and the second implantation layer 12 are annealed in a nitrogen atmosphere at 900 ° C. for 30 minutes, and then the second implantation is performed.
As shown in FIG. 6H, the isolation silicon oxide film 13, the first channel stop region 14 and the second channel stop layer 15 are formed by wet oxidation at 1000 ° C. for 150 minutes. Then, the silicon nitride film 7 and the stress relaxation silicon oxide film 6 are removed, and the silicon dioxide film 13 is left as shown in FIG. Hereinafter, a desired active element was formed in a silicon substrate region surrounded by the isolation silicon oxide film 13 by a normal MOS process.

Although the resist is used as the mask for the second implantation in the above embodiment, a material that can be used as a mask for the implantation (for example,
Even when a silicon oxide film, a silicon nitride film, etc.) is formed by patterning, it is obvious that the separation as shown in FIG. 1 can be performed.

Effect of the Invention In the isolation region obtained by the present invention, the breakdown voltage between the element regions was 15 V or more and the parasitic threshold voltage was 16 V or more even in the isolation width of 1.0 micron. Furthermore, the junction breakdown voltage is 1
Since it is 5V or more, the selective oxidation method can be applied to fine patterns.

In the description of the present embodiment, the case of applying the LOCOS method has been described, but it goes without saying that the present invention can be applied to all selective oxidation type element isolation techniques.

As described above, the present invention is directed to miniaturization of semiconductor integrated circuits,
This greatly contributes to higher performance.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device formed by the manufacturing method of the present invention, and FIGS. 2A to 2I are process sectional views for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. Is. 1,5 …… Silicon substrate, 2,6,13 …… Silicon dioxide film,
3,14 …… First channel stop layer (region), 4,15 ……
Second channel stop layer, 7 ... Silicon nitride film, 8
...... Photoresist, 9,11 ・ ・ ・ Boron ion, 10 ・ ・ ・ First injection layer, 12 ・ ・ ・ Second injection layer.

Claims (1)

[Claims] 1. A step of forming an element isolation region on a semiconductor substrate surface by a selective oxidation method, a step of implanting a first channel stop impurity into the semiconductor substrate in the element isolation formation region, and a heat treatment thereafter. Then, a step of softening and extending the resist around the element isolation region to the element isolation region, a step of implanting a second channel stop impurity using the softened and extended resist as a mask, and removing the resist And a step of oxidizing the element isolation region to form an isolation oxide film, and forming first and second channel stop regions under the element isolation oxide film. .