JPH0697772A - Method and device for delaying arithmetic data of digital filter - Google Patents

Abstract

PURPOSE:To shorten the calculation time of a pointer by displacing an input address in the direction in which an address increases, while holding it in a position relation in which a relative address increases by '1' each from the head address of each data buffer. CONSTITUTION:At a timing 2, a value of a pointer (p) is added by '1' and an output address of a data buffer of each fundamental filter advances by '1' from an address at a timing 1, and a relative address becomes an address of '1'. Also, an input address, as well advances by '1' from the address at the timing 1, and in a data buffer of a fundamental filter of a stage 1, the relative address becomes an address of 2. In the same way, in data buffers of fundamental filters of stages 2-4, relative addresses become addresses of 3, '0' (head address), and '1', respectively. Subsequently, at a timing 5, the value of the pointer (p) becomes 4, and becomes the same as a state that the value of the pointer (p) is '0', and thereafter, the state from the timing 1 to 4 is repeated, and the time required for a pointer calculation is shortened remarkably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of delaying data for the operation of a digital filter which is constructed by cascading basic filters having an increasing number of delay stages. More specifically, speech synthesis, in particular, LogMagnitude Approxi
mation) filter (hereinafter abbreviated as LMA filter)
The present invention relates to a method of delaying operation data of a digital filter for performing voice synthesis using.

[0002]

2. Description of the Related Art The LMA filter used for speech synthesis is a digital filter capable of approximating a logarithmic amplitude spectrum which is important for human hearing and has a transfer function as shown in FIG. As shown in the signal flow graph of FIG. 2, it is configured by a cascade connection of basic filters in which the number of delay stages is sequentially increased. In order to perform the operation of this filter, conventionally, a data buffer that stores the same number of data as the number of delay stages of the basic filter is prepared for the basic filter of each stage, and the data (first While inputting new data to the data buffer of the basic filter of one stage, and inputting the calculation result of the basic filter of the previous stage to the data buffer of the basic filter of the other stage), the data of each buffer has one address The data is delayed by moving the data, and the data delayed by the number of timings required for the operation of the corresponding basic filter is output. However, in this method, when it is realized by software, if the total number of delay stages becomes large, it takes a lot of time to move the data. for that reason,
In the case of performing speech synthesis in real time, current hardware performance cannot be realized by reducing the total number of delay stages at the expense of approximation accuracy of the logarithmic amplitude spectrum due to the restriction on the calculation time.

Therefore, in order to improve the approximation accuracy of the logarithmic amplitude spectrum, it is necessary to increase the total number of delay stages of the filter.
For that purpose, it was necessary to increase the speed of data delay processing. For that purpose, a delay method without data movement was effective. This method is similar to the above method in that each basic filter uses a data buffer for storing the same number of data as the number of delay stages, but the data is not moved and the input address of the data is changed as the timing progresses. It is to displace. The data of each address is advanced by one timing delay as the timing advances by one. When the stored data is output after being delayed by the required number of timings and is no longer needed, the data is written to that address. In order to input / output this data, pointers for designating the input address and output address of each data buffer are used, the pointer of each data buffer is calculated at each timing, and the input address and output address are calculated. I had decided on the address.

However, this method has a problem that a large number of pointers must be held when it is realized by hardware. Further, when it is realized by general-purpose hardware, there is a problem that the hardware having a plurality of pointers is extremely small, so that it is customary to use a part of the memory as a pointer, and it takes time to calculate the pointer. Further, when it is realized by software, a single CPU cannot calculate a plurality of pointers at a time, so it takes time to calculate the pointers.
There is a problem that hardware and programs become complicated when an attempt is made to calculate in parallel by a plurality of CPUs.

[0005]

It is an object of the present invention to hold a large number of pointers when it is realized by hardware, and it takes time to calculate the pointers when it is realized by software and when it is realized by general-purpose hardware. This is to solve the drawback of the prior art.

[0006]

SUMMARY OF THE INVENTION The present invention is a digital filter including a cascade connection of basic filters in which the number of delay stages is sequentially increased.
For each basic filter of the filter, allocate a data buffer of the same size that can store at least the delay data of the basic filter with the maximum number of delay stages, and allocate them consecutively in memory, and store the data in each data buffer. The input address to be written has a positional relationship in which the relative addresses from the start address of each data buffer are equal to each other, or the output addresses for reading data from each data buffer have the same relative address from the start address of each data buffer. The above problem is solved by cyclically displacing each data buffer as the timing progresses while maintaining such a positional relationship.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for delaying operation data of a digital filter according to the present invention will be described with reference to the drawings.

For simplification of the description, a digital filter having a transfer function as shown in FIG. 3 and a signal flow graph as shown in FIG. An embodiment to which the invention is applied will be described.

FIG. 5 shows the structure of the data buffer.
In this embodiment, data buffers of the same size (size 4) as the number of delay stages of the basic filter having the maximum number of delay stages are allocated to all the basic filters cascaded, and those data buffers are stored in the memory. They are arranged consecutively.

The size of the data buffer can be made larger than the number of delay stages of the basic filter having the maximum number of delay stages.

FIG. 6 is an explanatory diagram showing the positional relationship between the input address and the output address of each data buffer and the displacement due to the progress of timing.

In this embodiment, as shown in FIG. 6, the input address of each data buffer is kept in a positional relationship in which a relative address (hereinafter referred to as a relative address) from the head address of each data buffer increases by one. While advancing the timing, the address is advanced by one address (displaced in the direction in which the address increases). However, when it exceeds the last address of each data buffer, it is circularly displaced within each data buffer by returning to the start address. As a result, the output addresses of the respective data buffers have the same relative address and are displaced according to the displacement of the input address. When the number of delay stages of the basic filter increases by a plurality of stages, the relative address of the output address of each data buffer becomes equal by increasing the relative address of each data buffer by the same number of addresses.

Therefore, the difference address between the output addresses of each data buffer is equal to the size of each data buffer. Moreover, since the size of each data buffer is made equal, the difference address between the output addresses of each data buffer becomes the same.

In this embodiment, the pointer p is used to specify the relative address of the output address of each data buffer. Therefore, the value of pointer p and each data
The relationship between the input address and output address of the buffer is as follows.

Assuming that the value of the pointer p at timing 1 is 0, the output address of the data buffer of each basic filter is 0 as the relative address of each data buffer.
Address (start address). Further, the input address of the data buffer of each basic filter is such an address that the difference address from the output address becomes equal to the number of delay stages of the corresponding basic filter as described above, and in the data buffer of the basic filter of stage 1, Relative address is 1 and data of stage 2 basic filter
Address with relative address 2 in buffer, stage 3
In the basic filter data buffer, the relative address is an address of 3, and in the basic filter data buffer of stage 4, the relative address is an address of 0 (because it exceeds the last address, it returns to the first address). Therefore, the relative address of the input address of each data buffer is incremented by 1 as shown in the figure.

At timing 2, the value of the pointer p is incremented by 1 and set to 1. As a result, the data of each basic filter
The output address of the buffer is advanced from the address at timing 1 by one, and the relative address becomes one. The input address is also advanced by one from the address at timing 1, and the relative address is 2 in the stage 1 basic filter data buffer, and the relative address is 3 in the stage 2 basic filter data buffer. Data of 3 basic filters
The relative address is 0 (starting address) in the buffer, and the relative address is 1 in the data buffer of the stage 4 basic filter.

At timings 3 and 4, similarly, the value of the pointer p is advanced by 1 to 2 and 3. As a result, the output address and input address of the data buffer of each basic filter are incremented by 1 according to the above rule,
As shown in the figure.

At the timing 5, when the value of the pointer p is advanced by 1, it becomes 4, which is the same as the state when the value of the pointer is 0. Therefore, after timing 5, the states of timings 1 to 4 are repeated.

FIGS. 7 and 8 show the method of calculating the relative address and the relative address of the output address and input address of each data buffer from the start address of the entire data buffer (start address of the data buffer of stage 1). Show.

FIG. 9 shows a data input / output algorithm for the data buffer from the start to the end of the filter calculation.

Further, FIGS. 10A and 10B show a data output algorithm and a data input algorithm at each timing, respectively.

At each timing, the data read from the output address of each data buffer by the output algorithm is input to an arithmetic circuit (not shown) to execute the filter operation of each basic filter, and the operation of each basic filter. The result is written by the input algorithm to the input address of the data buffer of the next stage elementary filter. It should be noted that new data is written to the input address of the data buffer of the stage 1 basic filter.
The output of the basic filter in the final stage is D-A converted and input to the speaker drive circuit.

In this embodiment, as described above, since the relative addresses of the output addresses of the respective data buffers are made equal, the difference addresses of the output addresses of the respective data buffers are made equal. Therefore, if the output address of the data buffer of the basic filter of stage 1 is calculated, the output address of the data buffer of the basic filter of stage 2 or later can be calculated only by shifting the output address by one constant.

Next, another embodiment of the present invention will be described.

FIG. 11 is an explanatory diagram showing the positional relationship between the input address and the output address of each data buffer and the displacement due to the progress of timing.

In this embodiment, as shown in FIG. 11, the input address of each data buffer is cyclically displaced as the timing advances while keeping the relative address from the head address of each data buffer equal. As a result, the output address of each data buffer has its relative address reduced by one and is displaced according to the displacement of the input address.

Therefore, the difference address between the input addresses of each data buffer is equal to the size of each data buffer. Moreover, since the size of each data buffer is made equal, the difference address between the input addresses of each data buffer becomes the same.

In this embodiment, the pointer p is used to specify the relative address of the input address of each data buffer. Therefore, the value of pointer p and each data
The relationship between the input address and output address of the buffer is as follows.

At the timing 1, the value of the pointer p is set to 0, and the relative address of the input address of each data buffer is set to 1. That is, the value obtained by adding 1 to the value of the pointer is used as the relative address of the input address of each data buffer. Then the output address of each data buffer is
From the above relationship, the data of the stage 1 basic filter
Address with relative address 0 in buffer, stage 2
In the basic filter data buffer, the relative address is 3 (returning from the first address to the last address), in the stage 3 basic filter data buffer, the relative address is 2 and in the stage 4 basic filter data In the buffer, the relative address is 1.

At the timing 2, the value of the pointer p is incremented by 1 and set to 1. As a result, the data of each basic filter
The input address of the buffer is advanced by one from the address at timing 1 and becomes the address of relative address 2. The output address also advances by one from the address at timing 1, and the relative address is 1 in the data buffer of the stage 1 basic filter, and the relative address is 0 in the data buffer of the stage 2 basic filter. Data of 3 basic filters
The relative address is 3 (last address) in the buffer, and the relative address is 2 in the data buffer of the stage 4 basic filter.

At timings 3 and 4, the value of the pointer p is advanced by 1 to 3 and 4. As a result, the input and output addresses of the data buffer of each basic filter are incremented by one according to the above rule, and are as shown in the figure.

At the timing 5, when the value of the pointer p is advanced by 1, it becomes 4, and the state returns to the state at the timing 1 when the pointer value is 0. Therefore, after timing 5, the states of timings 1 to 4 are repeated.

FIGS. 12 and 13 show the method of calculating the relative address and the relative address of the input address and output address of each data buffer from the start address of the entire data buffer (start address of the stage 1 data buffer). Show.

The data input / output algorithm for the data buffer from the start to the end of the filter operation is the same as in the previous embodiment.

Further, FIGS. 14A and 14B show an output algorithm and an input algorithm of data at each timing, respectively.

At each timing, the data read from the output address of each data buffer by the output algorithm is input to an arithmetic circuit (not shown) to execute the filter operation of each basic filter, and the operation of each basic filter. The result is written by the input algorithm to the input address of the data buffer of the next stage elementary filter. It should be noted that new data is written to the input address of the data buffer of the stage 1 basic filter.
The output of the basic filter in the final stage is D-A converted and input to the speaker drive circuit.

In the second embodiment, as described above, since the relative addresses of the input addresses of the respective data buffers are made equal, the difference addresses between the input addresses of the respective data buffers are made equal. Therefore, if the input address of the data buffer of the basic filter of stage 1 is calculated, the input address of the data buffer of the basic filter of stage 2 and subsequent stages will be 1
It can be calculated simply by shifting by a constant.

[0038]

As described above, according to the method for delaying operation data of a digital filter of the present invention, for each basic filter, at least the delay data of the basic filter having the maximum number of delay stages can be stored. Data of the same size
Buffers are allocated and arranged consecutively in memory, and the input address to write data to each data buffer has a positional relationship where the relative address from the start address of each data buffer is equal or the timing required from each data buffer While maintaining the positional relationship such that the output address for reading the data delayed by several delays has the same relative address from the start address of each data buffer, the cyclic displacement is performed in each data buffer as the timing progresses. The difference addresses between the input or output addresses of the buffer are equal. Therefore, if the input address or output address of the data buffer of stage 1 is calculated, the input address or output address of the data buffer of stage 2 or later can be calculated by only shifting it by one constant. Therefore, when it is realized by hardware, only one pointer of the input address or the output address needs to be held, and the number of pointers to be held is smaller than that in the conventional method. Further, when it is realized by software or general-purpose hardware, the calculation of the input address or the output address of the delay data becomes easy, and the time required for the calculation of the pointer can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a transfer function of an LMA filter used for speech synthesis.

FIG. 2 is a diagram showing a signal flow graph showing a configuration of a digital filter that realizes the transfer function of FIG.

FIG. 3 is a digital circuit for implementing the data delay method of the present invention.
The figure which shows the transfer function of a filter.

FIG. 4 is a diagram showing a signal flow graph showing a configuration of a digital filter that realizes the transfer function of FIG.

5 is an explanatory diagram of a configuration of a data buffer when the data delay method of the present invention is applied to the filter operation according to the configuration of FIG.

FIG. 6 is an explanatory view showing the positional relationship between the input address and the output address of each data buffer and the displacement due to the progress of timing in the embodiment of the present invention.

FIG. 7 is a diagram showing a method of calculating a relative address from the start address of the entire data buffer of the output address of each data buffer and the relative address in the embodiment of the present invention.

FIG. 8 is a diagram showing a relative address calculation method and a relative address from the start address of the entire data buffer of the input address of each data buffer in the embodiment of the present invention.

FIG. 9 is a flowchart showing a data input / output algorithm for a data buffer from the start of filter operation to output.

10A and 10B are flowcharts showing an output algorithm and an input algorithm of data at each timing in the embodiment of the present invention.

FIG. 11 is an explanatory view showing the positional relationship between the input address and the output address of each data buffer and the displacement due to the progress of timing in another embodiment of the present invention.

FIG. 12 is a diagram showing a method of calculating a relative address from the start address of the entire data buffer and the relative address of the output address of each data buffer in another embodiment of the present invention.

FIG. 13 is a diagram showing a method of calculating a relative address from the start address of the entire data buffer and the relative address of the input address of each data buffer in another embodiment of the present invention.

14A and 14B are diagrams showing a data output algorithm and a data input algorithm at each timing in another embodiment of the present invention.

Claims (3)

[Claims] 1. A method of delaying operation data of a digital filter configured by cascade connection of basic filters in which the number of delay stages is sequentially increased, and for each basic filter, delay data of the basic filter having the maximum number of delay stages. Allocate data buffers of the same size that can store data, allocate them consecutively in memory, and set the input address to write data to each data buffer to the same relative address from the start address of each data buffer. It is characterized by cyclically displacing each data buffer as the timing progresses while maintaining the following positional relationship, and reading the data delayed by the number of timings necessary for the operation of the corresponding basic filter of each data buffer as output data. Method for delaying calculated data of digital filter. 2. A method of delaying operation data of a digital filter configured by cascade connection of basic filters in which the number of delay stages is sequentially increased, wherein the delay data of the basic filter having the maximum number of delay stages is set for each basic filter. Allocating data buffers of the same size that can store data, and arranging them sequentially in memory, and inputting the address to write data to each data buffer, and inputting the address of each data buffer of the output address of each data buffer A method of delaying operation data of a digital filter, which is characterized by cyclically displacing each data buffer as timing progresses while maintaining a positional relationship such that relative addresses from a head address become equal. 3. A digital filter configured by connecting basic filters having different numbers of delay stages in cascade, when accessing delayed data from a delayed data buffer and storing new data in the delayed data buffer, A delay data buffer of equal size for each basic filter, and 1 with a period equal to the delay data buffer size
Data characterized by having a pointer that changes in sequence, a delay data access unit that extracts the delay data in the delay data buffer, and a new data storage unit that stores new input data in the delay data buffer Delay device.