JP2001520429A - How to emulate shift registers using RAM - Google Patents

Abstract

(57) [Summary] A method of emulating a long shift register and storing an input bit stream using a RAM (10) and a short shift register (20). A pointer points to one of the RAM registers. To save the input bits, the contents of the RAM register pointed to by the pointer are written into the shift register (20) and shifted by one bit, and the input bits are saved at the position of the shift register (20) released by the shift operation. Then, the updated contents of the shift register (20) are written back to the RAM register pointed to by the pointer, and the pointer is incremented.

Description

DETAILED DESCRIPTION OF THE INVENTION

FIELD OF THE INVENTION The present invention relates to digital computing, and in particular, to emulate very long shift registers using random access memory (RAM) and short shift registers.
(emulating) method.

[0002] Many applications require that the input bit stream be processed in real time. For example, it may be desirable to use a finite impulse response filter on the input bitstream, where each coefficient is a single bit. Assuming that the K coefficient of this filter is {C _k } (k = 0 to K−1) and the bits of the (undefined length) input stream are {X _n }, the output of the filter is represented by the following expression. Is a set of numbers {Y _n } and means that the indicated operation is an XOR operation.

[0003]

(Equation 1)

A simple way to implement this filter is to use a register of length K to store the coefficients {C _k }
, And several consecutive input bits {X _n } may be stored in a shift register having a length of K bits. Each time a new input bit arrives, the contents of the shift register are shifted by one bit to accept the new input bit. As a result, the old input bits that are K bits ahead of the new input bits are automatically discarded. From the arrival of one new input bit to the arrival of the next new input bit, an inner product operation is performed on the contents of the coefficient register and the shift register, and the latest filter output is obtained.

This simple implementation has the disadvantage that for filters of useful length (for example, K = 1024), it is too costly to manufacture correspondingly long shift registers on the processor chip. is there. Therefore, there is a widely recognized need for a method of emulating a shift register using a cheaper form of memory, such as RAM, and providing such a method would be very beneficial. .

SUMMARY OF THE INVENTION According to the present invention, there is provided a method of processing consecutive input bits, comprising: (a) (i) a RAM having a plurality of registers each storing words of equal length;
A) providing a shift register at least as long as the word, and (iii) a pointer; (b) initializing the pointer to point to one of the registers in the RAM; For input bits: (i) write the word stored in the register pointed to by the pointer to the shift register; (ii) shift the word in the shift register by j bits;
iii) generating an update word in the shift register by writing the j input bits of the group to the shift register; (iv) storing the update word in the register pointed to by the pointer; (v) A method is provided that includes incrementing the pointer.

[0007] RAM typically consists of a single group of independently addressable (addressable) registers. Each register has a unique address. Each register stores a word of a fixed length (typically 8, 16, 32 or 64 bits) and can be retrieved later. An important aspect of the present invention is the use of a word addressable memory as described above to efficiently store successive individual input bits as they arrive. This is relatively short (one word long)
This is accomplished with a shift register, and a pointer that encodes the address of the RAM register. The pointer is initialized to point to one of the RAM registers. As each input bit arrives, the word stored in the RAM register pointed to by the pointer is written to the shift register, shifted by one bit to make room for the new input bit, and then extracted from the RAM Written back to register.
Thereafter, the pointer is incremented to point to the next RAM register. It should be noted that while incrementing the pointer is repeatedly defined in this specification, when the pointer pointing to the last RAM register is incremented, the first R
A pointer to the AM register appears. As will be described in more detail later, the input bits are stored in the RAM in the transposed order.

[0008]

【Example】

The present invention is a method for emulating very long shift registers using RAM. In particular, the invention can be used to apply a finite impulse response filter to a series of bits and transpose the series of bits.

The principles and operation of a shift register simulation according to the present invention may be better understood with reference to the drawings and the accompanying description.

Referring to the drawings, FIG. 1 shows a RAM 10 having M RAM registers with indices R ₀ -R _M-1 . Each RAM register can store N bits for the total capacity of NM bits at the moment when NM bits _{Xn to Xn-NM + 1} of the input bit stream are stored according to the present invention. Earliest arriving input bit _{X n ~X n-NM + 1} are stored in the N-1 position of the RAM registers _{R 0,} input bits _{X n-NM + 2} which was then arrive to the N-1 position of the RAM registers _{R 1} The input bits are stored sequentially, such as stored. The last arriving bit _Xn is stored in the zero position of the RAM register _RM-1 . Pointer P points to RAM register _R0 . RAM register _R0 holds the earliest arriving stored input bit _{Xn-NM + 1} in the N-1 position.

[0011] The arrival of the next input bit X _{n + 1} initiates the next input bit storage cycle. The first step is to store the contents of the RAM register R ₀ pointed by the pointer P to N
Writing to the bit shift register 20. FIG. 2A shows N-bit shift register 20 at the end of this step. The second step shifts the bits in the N-bit shift register 20 by one position, _discards the bit _{Xn-NM- 1,} and _{places the} Nth bit in the N-bit shift register 20 for a new input bit _{Xn + 1} . This is to make the position 0 empty. The third step is to store the new input bit _{Xn + 1} in the 0th position of the N-bit shift register 20. FIG. 2B shows N-bit shift register 20 at the end of this step. The fourth step is to write the contents of the N-bit shift register 20 to the RAM register _R0 pointed to by the pointer P. Finally, the pointer P is incremented to R
It refers to the AM register _{R 1.} Currently, RAM registers _{R 1} is a RAM register currently held earliest arriving save input bits _{X n-NM + 2} to the N-1 position. FIG. 3 shows the RAM 10 at the end of this step.

[0012] Between one input bit storage cycle and the next input bit storage cycle, the RAM 1
The contents of 0 can be read and processed in a conventional manner. For example, the finite input response above
Next output of filter Y_{n + 1}(Assuming K = NM), so that RAM1
The M words stored in 0 are successively read out and the coefficients {C_kXOR
It is. Coefficient ｛C_k｝ Is also stored in different memory units by M words.
To do this correctly, the coefficient ｛C_k｝ Must be stored in transpose order as follows:
Must. C_k-1, C_k-M-1, C_k-2M-1, ... C_2M-1, C _M-1 , C_k-2, C_km-2, C_k-2M-2, ... C_2M-2, C_{M- 2} , ... C_{k-M + 1}, C_{k-2M + 1}, C_{k-3M + 1}, ... C_{M + 1}, C₁ , C_km, C_k-2M, C_k-3M, ... C_M, C₀. This is exactly the book
The method of the invention uses a bit $ C_k｝ And the bit ｛C_k｝ Input bit
This is a transposition order generated by processing as a ring.

A typical value of N and M is 32 each. The pointer P is incremented periodically. Thus, in an input bit storage cycle where the pointer P initially points to the highest indexed register _{RM- 1} , incrementing the pointer P changes the value of the pointer P to point to the lowest indexed register _R0. Means that.

The principles of the present invention are applicable to the processing of input bit streams as well as one bit at a time. For example, processing the input bit stream three bits at a time by using a plurality of RAM registers that are multiples of three bits and shifting the contents of the shift register by three bits every input three bit storage cycle. Can also. The shift register must be at least as long as the plurality of RAM registers. If the shift register is used only for unloading and loading the RAM register and the output of the shift register is not used for other processing, the length of the shift register need not be a multiple of 3 bits. The only practical limitation is that traditional RA
If the typical word length of M (for example, 8, 16 or 32) is j and several bits are divided into several groups of processing, this processing is also performed, for example, in US Pat. No. 5,568,443 to Dixon et al. It can be performed on a word-by-word basis, rather than bit by bit as described in the prior art.

Although the present invention has been described with respect to a limited number of embodiments, many variations, modifications, and other applications of the present invention are possible.

[Brief description of the drawings]

FIG. 1 illustrates a RAM at the beginning of an input bit storage cycle.

2A and 2B show an N-bit shift register at two different stages of an input bit storage cycle.

FIG. 3 shows the RAM at the end of an input bit storage cycle.

[Procedure amendment]

[Submission date] April 27, 2000 (2000.4.27)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

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Claims (6)

[Claims] 1. A method of processing consecutive input bits, comprising: (a) (i) a RAM having a plurality of registers each storing words of equal length; and (ii) at least the same length as said words. (B) initializing the pointer to point to one of the registers of the RAM; (c) for each group of j input bits, (i) Writing the word stored in the register pointed to by the pointer to the shift register; (ii) shifting the word in the shift register by j bits; (iii) shifting the j input bits of the group. Generating an update word in the shift register by writing to the register; and (iv) storing the update word in the register pointed to by the pointer. Storing an update word; and (v) incrementing the pointer. 2. The method of claim 1, wherein j is 1. 3. The method of claim 1, wherein all of said RAM registers are the same length as each of said words. 4. The shift register is of the same length as each of the words.
The method of claim 1. 5. The method of claim 1, further comprising the step of: (d) sequentially reading and processing at least some of the words stored in the register of the RAM. 6. The method of claim 5, wherein all of the words stored in the register of the RAM are sequentially read and processed.