AU9402098A - Method of emulating a shift register using a ram - Google Patents

Method of emulating a shift register using a ram

Info

Publication number
AU9402098A
AU9402098A AU94020/98A AU9402098A AU9402098A AU 9402098 A AU9402098 A AU 9402098A AU 94020/98 A AU94020/98 A AU 94020/98A AU 9402098 A AU9402098 A AU 9402098A AU 9402098 A AU9402098 A AU 9402098A
Authority
AU
Australia
Prior art keywords
emulating
ram
shift register
register
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU94020/98A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I C Com Ltd
Original Assignee
I C Com Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by I C Com Ltd filed Critical I C Com Ltd
Publication of AU9402098A publication Critical patent/AU9402098A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/104—Delay lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Executing Machine-Instructions (AREA)
AU94020/98A 1997-10-09 1998-09-18 Method of emulating a shift register using a ram Abandoned AU9402098A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US94746797A 1997-10-09 1997-10-09
US08947467 1997-10-09
PCT/US1998/019708 WO1999019798A1 (en) 1997-10-09 1998-09-18 Method of emulating a shift register using a ram

Publications (1)

Publication Number Publication Date
AU9402098A true AU9402098A (en) 1999-05-03

Family

ID=25486184

Family Applications (1)

Application Number Title Priority Date Filing Date
AU94020/98A Abandoned AU9402098A (en) 1997-10-09 1998-09-18 Method of emulating a shift register using a ram

Country Status (6)

Country Link
EP (1) EP1027649A4 (en)
JP (1) JP2001520429A (en)
KR (1) KR20010024466A (en)
CN (1) CN1119745C (en)
AU (1) AU9402098A (en)
WO (1) WO1999019798A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733049A (en) * 2015-03-27 2015-06-24 中国电子科技集团公司第二十研究所 Shifting register realized by using random access memory (RAM) unit
CN110888601B (en) * 2019-11-14 2023-05-19 中国电子科技集团公司第五十四研究所 Shifting register implementation method based on RAM IP core

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755788A (en) * 1972-05-01 1973-08-28 Honeywell Inf Systems Data recirculator
US4393482A (en) * 1979-11-08 1983-07-12 Ricoh Company, Ltd. Shift register
US5153846A (en) * 1990-07-30 1992-10-06 At&T Bell Laboratories Digital shift register using random access memory
US5406518A (en) * 1994-02-08 1995-04-11 Industrial Technology Research Institute Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration
US5479128A (en) * 1994-03-16 1995-12-26 Industrial Technology Research Institute Single ram multiple-delay variable delay circuit

Also Published As

Publication number Publication date
EP1027649A4 (en) 2004-08-04
EP1027649A1 (en) 2000-08-16
CN1119745C (en) 2003-08-27
JP2001520429A (en) 2001-10-30
CN1281559A (en) 2001-01-24
KR20010024466A (en) 2001-03-26
WO1999019798A1 (en) 1999-04-22

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase