JPH0696019A - Control circuit for self-synchronizing system - Google Patents

Abstract

PURPOSE:To provide the control circuit for the self-synchronizing system which is small in scale and generates an operation start signal I and receives a signal of data validity DV. CONSTITUTION:This control circuit consists of a 1st exclusive OR circuit(EXOR) 200 which inputs signals REQj-1 and ACKj and outputs a signal I and a 2nd EXOR 300 which inputs signals DV and ACKj+1 and outputs a signal REQj-1 becomes '1' and the signal I becomes '1' while all the signal values are '0', a logic block processes input data, so that DV becomes '1' and REQj becomes '1'. When ACKj+1 becomes '1', I becomes '0' and DV becomes '0', so that REQj is held at '1'. When REQj-1 becomes '0', I becomes '1', DV '1', REQj, '0', and ACKj+1 '0'. Then I becomes '0' and DV becomes '0', so that the initial state is entered.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to control circuits for self-synchronizing systems, and more particularly to non-pipelined circuits.
The present invention relates to a handshaking circuit used for configuring a control unit of a self-timed system.

[0002]

2. Description of the Related Art As a function of a handshaking circuit of a non-pipeline self-synchronous system, a 2-cycle full-handsh shown in FIG.
ake) circuit, refer to the technical paper “JE Sutherland,“ Mic
ropipelines, "Communications of the ACM, Vol.32, N
o.6, pp.720-738, June 1989 ".
In addition, the 4-cycle full-handshake shown in FIG.
ake) circuit, refer to the technical paper "GM Jacobs and R.W. Bro.
dersen, "A Fully Asynchronous Digital Signal Proce
ssor Using Self-Timed Circuits, "IEEE Journal of So
lid-State Circuits, Vol.25, No.6, pp.1526-1537, De
c. 1990 ”. Furthermore, the technical paper “TH-Y.Me
ng, RWBrodersen and DGMesserschmitt, "Automatic
Synthesis of Asynchronous Circuits from High-leve
l Specifications, "IEEE Trans. on CAD Vol.8, No.1
1, pp.1185-1205, Nov. 1989 "describes a half-handshake circuit shown in FIG.

[0003]

The non-pipeline self-synchronization system is configured as shown in FIG. 5, and the logic block corresponding to the data processing unit is a DCVSL (Differential Ca
scode Voltage Switch Logic: `` CK Erdelyi, WR Griffi
n and RDKilmoyer, "Cascode Voltage SwitchLogic D
esign, "VLSI DESIGN, pp.78-86, Oct. 1984") or SSDL
(Sample-Set Differential Logic: `` TAG rotjohn and
B. Hoefflinger, "Sample-Set Differential Logic for
Complex High-speed VLSI, "IEEE Journal of Solid-St
ate Circuits, Vol.SC-21, No.2, pp.367-369, Oct. 19
84 '') or LDCL (Latched Domino CMOS Logic: `` JA Preto
rius, ASShubat and CASalama, "Latched Domino CM
OS Logic, "IEEE Journal of Solid-State Circuits, V
ol.SC-21, No.4, pp.514-522, Aug. 1986)) or E
CDL (Enable-disable Differential Logic: "Shih-Lien
Lu, "Implementation of Iterative Networks with CMO
S Differential Logic, "IEEE Journal of Solid-State
Circuits, Vol.23, No.4, pp.1013-1017, Aug. 1988 '')
It is realized by logic. The basic configuration of the logic block of FIG. 5 is shown in FIG. When the control signal of I in the figure is "0",
The upper two p-type MOS transistors 300 and 305 become conductive, and the lower n-type MOS transistor 324 becomes high impedance. A tree composed of n-type MOS transistors that realizes the function of a logic block by this
(Hereinafter, abbreviated as n-type MOS tree) is separated, and the output of logic block F and the negative value of F (shown as F bar in the figure)
Signal DV (Dat that both become "1" and display data valid
a Valid) becomes "0".

The REQ _j signal of the handshaking circuits of FIGS. 2, 3 and 4 is used as the I signal of FIG. 5, and the D signal of FIG.
If the V signal is the REQ _j signal, it can be used in the system configuration of FIG. However, when any of the above circuits is used, the control protocol becomes 4 cycles. That is, the next data cannot be processed unless all the signals are returned to the original initial state. The first 2 cycles of the 4-cycle protocol correspond to the process, and the last 2 cycles are used to return the request signal and the acknowledge signal to "0".

No data is processed in the latter two cycles of the above-mentioned four cycles. Further, when the circuits of FIGS. 2 and 3 are used for these two cycles, it is necessary to start processing of data from the input side in order to prevent malfunction. Therefore, the processing time of the data and the propagation time of the signal from the output side to the input side of the control circuit must be taken into consideration. When the circuit of FIG. 4 is used, an external acknowledge signal on the output side is propagated to the input side, each logic block is initialized in the middle, and the above-mentioned problem does not occur, but the control circuit itself is somewhat large. .

An object of the present invention is to provide a control circuit which facilitates generation of I and DV signals according to a predetermined protocol and has a small scale structure.

[0007]

As shown in FIG. 1, two 2-input exclusive OR circuits 200 and 210 are used.
A request RE for one input of the exclusive OR circuit 200 on the input side
Connect to the Q _j-1 signal line and connect the other input to the acknowledge ACK _{j + 1} signal line from the output side. Acknowledgment of this output side ACK _{j + 1}
The signal line is the acknowledge ACK _j signal line to the input side. The output of the exclusive OR circuit 200 is used as the I control signal to the logic block. One input of the exclusive OR circuit 210 is connected to the data valid signal line DV from the logic block, and the other input is connected to the acknowledge ACK _{j + 1} signal line from the output side. Request the output of the exclusive OR circuit 210 to the output side RE
Use the Q _j signal line.

[0008]

The operation of the method of the present invention will be described below with reference to FIG. External request REQ _j-1 when all signal values are "0"
When the signal becomes "1", the signal of I becomes "1" because the acknowledge ACK _j signal to the outside is "0". When I goes to "1", the logic block processes the data input and brings the DV signal to "1". When the DV signal becomes "1", the request REQ _j signal to the outside becomes "1". External acknowledgment AC for this request REQ _j signal
When the K _{j + 1} signal becomes "1", the external request REQ _j-1 signal is "1", so that I becomes "0" and the DV signal becomes "0". Request to the outside by moving DV from "1" to "0" REQ _j
The signal may temporarily become "0", but it does not cause malfunction. At this time, signals other than I and DV become "1", and the control circuit enters the standby state. When the external request REQ _j-1 signal becomes "0", the I signal becomes "1" because the external acknowledge ACK _j signal is "1". When I becomes "1", the logic block processes the input data and sets the DV signal to "1".
Since the external acknowledge ACK _{j + 1} signal is “1”, when the DV signal becomes “1”, the external request REQ _j signal becomes “0”. When the external acknowledgment ACK _{j + 1} signal becomes “0” with respect to this request REQ _j signal, the external request REQ _j-1 signal is “0”.
I becomes "0", and the DV signal becomes "0". In this case as well, the request REQ _j signal to the outside may temporarily become "0" due to the movement of DV from "1" to "0", but it does not cause a malfunction as before. At this point, all the signals become "0" and the control circuit returns to the initial state. As described above, it can be confirmed that the circuit of FIG. 1 easily generates I and DV signals according to the protocol of claim 1 and is of a small scale.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT One embodiment of the present invention will be described with reference to FIG. 7, which illustrates a time diagram corresponding to the system of FIG. Below, the delay time Δ shown in FIG. 7 from when the input data becomes valid until the input request signal rises (or falls), and the delay time 2Δ from the rise of the I signal to the rise of the DV signal is 2Δ. It is assumed that the delay time from the rise of the request signal to the outside to the rise of the acknowledge signal from the outside is Δ, and that the logic block of FIG. 1 is configured as shown in FIG. When all the signal values in FIG. 7 are "0" and the external request REQ _j-1 signal rises, the external acknowledge ACK _j signal is "0", so the I signal changes from "0" to "0". 1 ”, and the logic block n-type M
One side of the OS tree converts the output F of the logic block into "0" or "1" (the negative value of F is "1" or "0").
At this time, since the inputs of the logical sum element 600 in FIG. 6 are different,
The DV signal becomes "1". Since the external acknowledge ACK _{j + 1} signal in FIG. 1 is “0”, the output of the exclusive OR circuit 210, that is, the request REQ _j signal to the outside becomes “1”. External understanding AC
When the K _{j + 1} signal becomes “1”, the external acknowledgment ACK _j signal becomes “1”.
Since the external request REQ _j-1 signal and the DV signal are "1", the I and external request REQ _j signals are "0". However, since DV becomes "0" as I becomes "0", the state of "0" of the request REQ _j signal is temporary and does not affect the control. At this point, all signals except I and DV are "1", and the control circuit is in a standby state.
When new data is prepared and the external request REQ _j-1 signal falls, the external acknowledge ACK _j signal is "1", so the I signal is converted from "0" to "1", and the logic block Inputs new data and sets the DV signal to "1". At this time,
Since the external acknowledge ACK _{j + 1} signal in FIG. 1 is "1", the output of the exclusive OR circuit 210, that is, the request REQ _j signal to the outside becomes "0". Since the acknowledged ACK _{j + 1} signal from the outside becomes “0” and the acknowledged ACK _j signal to the outside becomes “0”, and the request REQ _{j + 1} signal from the outside is “0”, I and DV Signal becomes "0". Similarly to the above, the request REQ _j signal to the outside temporarily becomes "1". Does not affect control as before. At this point, all the signals become "0" and the control circuit is newly initialized. If the self-synchronizing system of FIG. 5 uses the positive and negative values of the control signal, the elements having the outputs of the exclusive OR and the exclusive NOR of FIG. Can save
Of course, the MOS transistors 310 and 320 and 314 and 3 in FIG.
It is possible to save the negative logic element composed of 26 MOS transistors. In this case, the control unit of the self-synchronization system can be made smaller.

[0010]

INDUSTRIAL APPLICABILITY The present invention is a non-pipeline.
ed) Applicable to the construction of self-timed systems. Moreover, it is possible to configure a control unit of a small-scale and low power consumption self-synchronization system. Also, when configuring a control circuit that uses positive and negative control signals,
The circuit for generating the data valid signal of the processing unit can be saved, and the structure of the exclusive OR circuit which is a constituent element of the present invention can be reduced.

[Brief description of drawings]

FIG. 1 is a handshake control circuit according to an embodiment of the present invention.

FIG. 2 is a prior art two-cycle handshake control circuit.

FIG. 3 is a prior art 4-cycle full handshake control circuit.

FIG. 4 is a prior art two-cycle half handshake control circuit.

FIG. 5 is a block diagram of a general non-pipeline self-synchronizing system.

FIG. 6 is a configuration when a logic block of a self system is realized by DCVL logic.

FIG. 7 is a time diagram explaining the operation of the control circuit of the embodiment of FIG.

FIG. 8 is a circuit diagram of one implementation example of the exclusive OR circuit of the embodiment of FIG.

[Explanation of symbols] Input Data ... Input data, Output Data ... Output data,
----- Control line, I ... Processing start signal, DV ... Data valid signal, VDD ... Power supply, GND ... Ground, 200, 210 ... Exclusive OR circuit, 500, 510 ... Negative logic element, 400, 405 ... 2-input AND element, 600 ... 2-input OR element, 300, 30
5, 310-313 ... p-type MOS transistor, 320-324
… N-type MOS transistor, C… Muller-C element, RE
Q _j-1 ,, REQ _j ... request signal, ACK _j , ACK _{j + 1} ... OK (ac
knowledge) signal.

Claims (1)

[Claims] 1. A request from the outside of the self-synchronization system in a state in which input data to the self-synchronization system can be processed.
A DV (Data Valid) signal indicating that the start (Initiate) signal for starting the processing of the input data by receiving the st) signal is transmitted to the self-synchronization system and the processing result of the input data can be output. Is generated from the self-synchronizing system to generate a request signal to the outside, and after receiving an acknowledge signal from the outside to the request signal to the outside, the start signal is returned to the original state, and the input data side The control circuit for the self-synchronization system that generates an acknowledge signal to the outside of the first exclusive control circuit, which receives the request signal from the outside of the self-synchronization system and the acknowledge signal to the outside of the input data side and outputs the start signal Logical OR circuit and a second exclusive OR circuit which receives the DV signal and the acknowledge signal from the outside and outputs a request signal to the outside. Circuit.