JPH06232732A - Self-synchronous logic circuit - Google Patents

Abstract

PURPOSE:To design the circuit of a smaller area by defining a logical 1 to be (0, 1), logical 0 to be (1, 0), an invalid value to be (0, 0) and a fault/test value to be (1, 1). CONSTITUTION:When an input (a) or (b) is (1, 1) representing a fault/test state, outputs of NAND gates 401, 402 go to 0 and outputs (c) of NAND gates 500, 900 go to (1, 1) representing a fault/test state. With the inputs a, b set to an invalid (0, 0), when both inputs are invalid and not a fault/test value and when both inputs are (1, 0) and (0, 1), outputs of all NAND gates go to 1 and outputs (c) of both output gates 500, 900 are invalid (0, 0). Moreover, with both inputs (a), (b) set to 1, 0 respectively, the outputs (c) are (1, 0), and when the inputs (a), (b) are 0, 1 respectively, the outputs (c) are (0, 1). Thus, an AND logic is formed by less number of MOS transistors(TRs) and problems of an area of the logic circuit and the delay time or the like are solved.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to self-synchronizing logic circuits, and more particularly to logic circuits that can be used to implement self-timed systems that facilitate the design of integrated circuits.

[0002]

2. Description of the Related Art With the progress of integrated circuits, the area of a chip has increased and the width of wiring has become narrower. Therefore, the length of wiring has a great influence on clock distribution. Therefore, in order to solve the problem that appears in clock distribution, buffered tree structure distribution and PLL (Phase
Locked Loop) technology is used. However, using such a method increases the area of the clock system. Therefore, a self-timed system that does not use a clock has recently attracted attention in order to realize a next-generation digital system.
There are two main approaches to realize a self-synchronizing system. One is based on using the configuration as shown in FIG. This approach uses a handshake circuit that controls the data transfer between the functional blocks. For this configuration, refer to the technical paper "JE Sutherland,
"Micropipelines," Communications of the ACM, Vol.
32, No. 6, pp. 720-738, June 1989 '',
Often used in pipeline systems. In another approach, the input and output signals of each functional block are encoded and each signal X is represented by a signal pair of (Xt, Xf). In this approach, the value of "1" is represented by (0,1), the value of "0" is (1,0), and the value of "invalid" is (0,0). Therefore, a circulating signal such as ACK in FIG. 2 is unnecessary. For this approach, see the technical paper SR Jones, K. Sammut,
C. Nielsen and J. Staunstrup: "Toroidal Neural Ne
twork Processor: Architecture and Processor Granul
arity Issues, "in U. Ramacher and U. Ruckert (ed
s.): "VLSI Design of Neural Networks," pp.229-255,
Kluwer Academic, 1991. ”. However, a major drawback of this approach is the area of the circuit that produces the sign signal. The design method to reduce the area is
Technical paper "D. Lloyd and S. Jones," Improved Self-Tim
ed Circuit Design Method, "Electronics Letters, Vo
L.28, No.5, pp.492-493, February 1992. ".

[0003]

[Problems to be Solved by the Invention] The above technical paper "SR
Jones, K. Sammut, C. Nielsen and J. Staunstrup: "
Toroidal Neural Network Processor: Architecture an
d Processor Granularity Issues, "in U. Ramacher an
d U. Ruckert (eds.): "VLSI Design of NeuralNetwork
s, "pp.229-255, Kluwer Academic, 1991.", uses a Muller-C element on the input side to implement a functional block circuit. Therefore, as the input line of the circuit becomes N, the number of Muller-C elements becomes necessary in proportion to the Nth power of 2 and the area of the circuit becomes large. An example implementation of an AND gate using this approach is shown in FIG. on the other hand,
The above technical paper "D. Lloyd and S. Jones," Improved Se
lf-Timed Circuit Design Method, "Electronics Lette
rs, Vol.28, No.5, pp.492-493, February 1992. ”, the number of Muller-C elements is fixed, so even in the case of a multi-input circuit, Muller-C The area of the element increases only slightly. Apply this approach A
An implementation example of the ND gate is shown in FIG. However, compared to the former approach, this approach results in a slightly larger signal delay.

It is therefore an object of the present invention to provide a self-synchronizing logic circuit which solves the area and delay problems of the above approaches.

[0005]

First, the signal pair of (Xt, Xf) corresponding to the value of the input or output signal X of the logic circuit is redefined. The value of "1" is (0,1), the value of "0" is (1,0) and "invalid"
The value of defines (0,0), but in addition to this, "fault / test"
Define the value of as (1,1). In addition, when any of the input signals is (0,0) or (1,1), the logic circuit outputs the output of a function with that signal as a variable (0,0) or (1,1). It shall be. However, when the same function has both (0,0) and (1,1) input signals, the output of the function is (1,1). Further, the logic circuit evaluates the function when none of the input signals of the function is (0,0) or (1,1), and when the value of its output is "1", it It is represented by (0,1), and when it is "0", it is represented by (1,0). That is, the self-synchronous logic circuit according to the exemplary embodiment of the present invention receives n input signals Xi each consisting of the timing signal Xi.t and the function evaluation signal Xi.f, and each of them receives the timing signal Xi.t.
M output signals consisting of Yj.t and function evaluation result signal Yj.f
When Yj is output and any one of the n input signals (Xi.t, Xi.f) is (invalid) (0,0), the other input of the function is "failure". If not (1,1) of `` / test '', the output signal pair (Yj.t, Y of the function that uses the timing signal Xi.f as a variable
jf) is set to (invalid) (0,0) and one of the input signal pairs
When (Xi.t, Xi.f) is (fault / test) (1,1), the output signal pair (Yj.t, Yj.f) is (fault / test) (1,1). , When all the input signal pairs (Xi.t, Xi.f) of the above function are not (0,0) of "invalid" or (1,1) of "fault / test", the output of the above function When the signal Yj is "0", the output signal pair (Yj.t, Yj.f) is
(1,0), when the output signal Yj is "1", the output signal pair
It is characterized in that (Yj.t, Yj.f) is (0, 1) (see FIG. 1).

[0006]

[Operation] Therefore, when any input signal pair (Xt, Xf) is (invalid) (0, 0), the output signal pair (Yt, Yf) of the function having Xf as a variable is "invalid". Becomes (0,0), and when any of the input signal pair (Xt, Xf) is (Failure / Test) (1,1),
The output signal pair (Yt, Yf) becomes (1, 1) of “fault / test”. However, when the same function has both input signals (0,0) of "invalid" and (1,1) of "fault / test", the output of the function is (1,1) of "fault / test". Become. In addition, all input signal pairs (Xt, Xf) of the function are (invalid) (0,0) or "fault / test".
When (1) is not (1,1), when the output signal Y of the function is "0", the output signal pair (Yt, Yf) is (1,0), and the output signal Y is "1". At this time, the output signal pair (Yt, Yf) becomes (0, 1). Clearly, the logic circuit of an exemplary embodiment of the invention is
It is used to implement a self-synchronizing system because the signal is comparable to that of a conventional encoding-based self-synchronizing circuit. Note that either output of the logic circuit can be
It can be set to (0,0) or (1,1).

[0007]

FIG. 5 shows one embodiment of the present invention. This is an implementation of the same kind of AND gates of FIGS. When the input a or b of the circuit of FIG. 5 is (1,1) of "fault / test", the output of the NAND gate 401 or 402 is "0", so the output c of the NAND gate 500 or 900 is " It becomes (1, 1) of "Fault / Test". If the input a or b is "invalid" (0,0) and the input b or a is not "fault / test" (1,1), the input b or a is (1,1).
When 0) or (0,1), the output c of the NAND gates 500 and 900 becomes (0,0) which is "invalid" because all the outputs from the NAND gates 400 to 405 become "1". . When inputs a and b are (1,0), the output of NAND gate 400 is "0" and NAND gate 401 outputs
Since the output up to 405 becomes "1", the output of the NAND gate 500 becomes "1" and the output of the NAND gate 900 becomes "0", and the output c
Becomes (1,0). NAND gate when inputs a and b are (0,1)
The output of the NAND gate 500 is "0" and NAN because the output of the 405 is "0" and the outputs from the NAND gates 400 to 404 are "1".
The output of the D gate 900 becomes "1" and the output c becomes (0,1). NAND gate when input a is (1,0) and input b is (0,1)
Since the output of 403 is “0” and the outputs of NAND gates 400, 401, 402, 404, 405 are “1”, the output of NAND gate 500 is “0” and the output of NAND gate 900 is “1”, and the output c is (0, 1 ). When the input a is (0,1) and the input b is (1,0), the output of the NAND gate 404 is “0” and the NAND gates 400, 401, 402, 403, 405.
Output of the NAND gate 500 is "0" because the output of "1" becomes
And the output of the NAND gate 900 becomes "1", and the output c is (0,1)
Becomes The self-synchronizing 2-input AND gate of FIG. 5 has a smaller number of logic stages than those of FIGS. 3 and 4 based on the conventional design technique. The Muller-C element used in the logic circuits of FIGS. 3 and 4 is described in the technical paper “JE Sutherland,“ Micropipelines, ”Comm.
unications of the ACM, Vol.32, No.6, pp.720-738, Ju
6 shown in "ne 1989", the delay of the logic circuit of FIG. 5 according to the present invention is smaller. Using standard gates, the AND of FIG. 3 is 56 MOS transistors, the AND of FIG. 4 is 66 MOS transistors, and the AND of FIG.
Since it can be configured with 40 MOS transistors, the area of the logic circuit according to the present invention is the smallest. Furthermore, if the logic circuit of the present invention is combined with other similar circuits to form a large system, either output of the system can be easily set to (1,1) or (0,0). This is considered useful for testing self-synchronizing systems.

[0008]

According to the present invention, it is possible to design a circuit having a small area as compared with a circuit designed based on the conventional technique. In addition, a circuit with a small signal delay can be obtained. The output of the circuit can be set by the definition of the signal of the present invention.

[Brief description of drawings]

FIG. 1 is a diagram showing a general configuration of the present invention.

FIG. 2 is a functional block configuration of a conventional self-synchronizing system using a handshake signal.

FIG. 3 is an implementation example of a self-synchronizing NAND gate based on encoding.

FIG. 4 is an implementation example of a conventional self-synchronous NAND gate using a fixed number of Muller-C elements.

FIG. 5 is an implementation example of a self-synchronizing NAND gate according to the present invention.

FIG. 6 is an example of a Muller-C element used in the logic circuits of FIGS. 3 and 4.

[Explanation of symbols]

X1.t ~ Xn.t, X1.f ~ Xn.f, at, bt, af, bf, A, B ... Input signal line, Y1.t ~ Ym.t, Y1.f ~ Ym.f, ct, cf, Z ... Output signal line, I, DV ... Control signal line, VDD ... Power supply, GND ... Ground,
100 ... Logic circuit, 200 ... Processing logic circuit, 300 ... Control handshake circuit, 400-405 ... 2-input NAND circuit element,
500 ... 3-input NOT logical AND element, 600-605 ... Muller-C element, 700, 701 ... 3-input logical OR element, 750-752 ... 2-input logical OR element, 800-804 ... 2-input logical AND element, 900 ... 5-input NAND device, 161-166 ... p-type MOS transistor,
171 to 176 ... N-type MOS transistor, REQj, REQj-1 ... Request signal line, ACKj, ACKj + 1 ... Acknowledge
Signal line.

Claims (1)

[Claims] 1. An n number of input signals Xi each consisting of a timing signal Xi.t and a function evaluation signal Xi.f, each of which receives a timing signal Yj.t and a function evaluation result signal Yj.f.
Output m output signals Yj consisting of the input signal pairs (Xi.t, Xi.
When f) is (disabled) (0,0) and the other inputs of the function are not (fault / test) (1,1), the timing signal X
Disable the output signal pair (Yj.t, Yj.f) of the function with if as a variable
(0,0), and one of the input signal pair (Xi.t, Xi.f) is "fault / test".
When (1,1), the output signal pair (Yj.t, Yj.f) is (fault / test) (1,1), and all the input signal pairs (Xi.t, Xi.f) is "disabled"
When not (0,0) or (1,1) of `` fault / test '', when the output signal Yj of the above function is `` 0 '', the output signal pair (Yj.
t, Yj.f) is (1, 0), when the output signal Yj is "1", the output signal pair (Yj.t, Yj.f) is (0, 1), Logic circuit to do.