JPS6020634A - Cmos logical circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation by eliminating the need for an inverter for the purpose of phase matching of each stage. CONSTITUTION:In the i-th stage and the (i+1)th stage constituting a carry circuit comprising a full adder or the like by a Domino circuit, an N-channel positive logical circuit comprising n11-n15 clipped between a point being pulled up and a point being pulled down by an N-channel transistor (TR) n10 includes an j-digit output C as an input during a sampling period of a P-channel TR p10 during the precharge period of the i-digit, i.e., while a clock phi is 0. Further, in the (i+1)-th digit, a negative logical circuit comprising P-channel TRs p21-p25 clipped between a P-channel TR n20 pulled down for an output point D during the precharge period, i.e., while the clock phi is 0 and a point pulled up by an N- channel TR n20 while the clock phi is logical 1 includes a j-digit output C as the input. The Domino circuit is formed by the positive logical circuit as mentioned above and a negative logical circuit comprising elements being complementary to the elements controlled by the input including at least one output of the said positive logical circuit and costituting the positive logical circuit.

Description

[Detailed Description of the Invention] Kineiyu'' relates to complementary 1M08 (hereinafter referred to as CMO8) logic circuits, and particularly to dynamic logic circuits (domino circuits) configured such that logic signals propagate like a chess game during a sampling period. Regarding circuit configuration.

The CMO8 logic circuit consists of nMO8 (P-type substrate n-channel M
O8) The current consumption in the steady state is extremely small compared to ratio logic circuits, etc., and it is especially suitable for circuit configurations constituting large-scale integrated circuits (LSI) where a large number of elements are concentrated in a small area and heat generation is a problem. It is considered effective. However, since the static CMOSwi logic circuit has a complementary logic of P-n, the circuit scale becomes large and the operation speed is limited by signal propagation delay due to parasitic capacitance due to the large number of high-power terminals. Also monolithic CM 08 LSI
So, 808 (S 1licon on 5apph
ive) Unless a special structure such as a twin well structure is adopted, a high-grade well structure is required, resulting in a relatively large junction capacitance, which further limits the operating speed.

A dynamic CMO8 logic circuit was constructed to eliminate these drawbacks, and as shown in Figure 1, it is possible to change the logic value only once during the domino circuit ridge sampling period (however, depending on the configuration, it is possible to change the logic value only once). By appropriately matching the phases (only changes in direction), it is possible to configure the signal propagation to spread like a chess player, and the logic of a long bus can be precharged and sampled during the sampling period 11! ] can be realized.

Figure 1 is a circuit diagram illustrating the i stage and i+1 stage in which carry circuits such as full adders are constructed using domino circuits. It is controlled by the phase clock ψ. From now on, the operation will be described in terms of positive logic, but the clock ψ is set periodically to the I level (logical value '''
1#) and low level (logical value 0'''), all n-channel transistors are conductive at the logic value ``1#'' level (J N '' I) channel transistors are cut off ``OF'' I) Channel transistor @ l U N 71 Logic level and threshold voltage of each transistor (logic threshold: VTL)
is set. Here, the n-channel transistor P
, , P2 is ``ON'' for the period of clock ψ'''0# and is connected to A and B via the Pt and Pt channels.
During this period, the point is precharged to the logic value "1j", so no steady current flows.
+l... is set to a stable value.

Furthermore, the carries ci-i, ci, and ci+1 are undetermined and only change in this period, since the clock ψ is allowed to change only - times from 60# to 1'1 during which it becomes l#. If so, it must be “0”. clock ψ
When becomes ``ul'', P2 is turned ``OFF'' instead.
1 y n2 turns 'ON'.

Again, there is no DC bus connecting the power supply ground, so there is no steady current. The value of point A is aibi and c
i-1 is determined during this period, but especially a i vb i
= l, this is determined by ci-1
1 has already been set when the clock ψ changes to 1#, or it can change only once from '0' to '1' during this period. Under this condition, when Ci-1 is '0#', the A point is ul
If `` remains as it is and changes from ``0# to ``1'', the charge charged at point A via the nq channel will fall to the ground and become 0.''
becomes.

In this way, when point A changes to °゛0'', it is 1! ps w
``s constitutes an inverter, so Ci is 0'' → I
In this way, the logic of the i stage operates as a carry circuit such as a full adder, and C1 is "0" when the clock ψ is "O"' for the i+1 stage, and the clock ψ is @1. When # is 0" or "0#' → pa IM
Since there is only a permissible change in , the carry is propagated in a chess-like manner during the period when the clock ψ is 1'' and during the sampling period as Ci+1C1+... Here, the transistors P3, n3 and The inverter configuration of p4.n4 is important in ensuring this unique operation.As mentioned above, this is necessary to match the signal changes allowed during the sampling period and to compensate for the levels at points A and B. However, when increasing the signal propagation speed, the logic for one stage of this inverter always suffers from failures, and the number of elements also increases.

As described above, the present invention provides an output point that is pulled up to a precharge M rks'J and a node that is pulled down during a sampling period without providing an inverter configuration for the purpose of phase matching at each stage in a domino circuit. controlled by a first positive logic circuit interposed therebetween and an input group including at least one output of the first logic circuit, and composed of elements in complementary/interpolative relationship with the first logic circuit constituent elements. , and a second negative logic circuit interposed between the output point that is pulled down during the pre-charge period and the point that is pulled down during the sampling J91. The domino circuit described above eliminates the above drawbacks without adding any other special mechanism, and has a remarkable effect in constructing a CMOS domino logic circuit that is capable of high-speed operation and has a small number of constituent elements.

The basic components of the present invention are an element or control mechanism that pulls up the output point (Full-up) during the precharge period, and a pull-down (1'ull-do) during the Zumbling period.
wn ), a first positive logic circuit sandwiched therebetween, and an element having a complementary relationship with the first logic circuit component, and at least one of the first logic circuits. an element that is controlled by a group of inputs and that pulls the output point during the pre-charge period, or
It includes a second negative logic circuit sandwiched between the control mechanism and an element or mechanism that is pulled up during the sampling period.

Next, a specific embodiment of the present invention will be described with reference to FIG.

FIG. 2 is a CMO8 logic circuit diagram showing one embodiment of the present invention, which is applied to a carry (Φ carry) circuit such as a full adder logic circuit, similar to that shown in FIG. During the charging period, the p-channel transistor plO pulls up the output point C to the power supply while the clock ψ is "0". During the sampling period, the n-channel transistor nIo pulls down the output point C. ``11~''Is n-channel positive logic circuit,! +
The first digit indicates the precharge period, the clock cycle ψ″′
Consists of a p-channel transistor 20 that pulls down the output point at 0'', and p-channel transistors p21 to p2B sandwiched between a point that pulls up the output point at clock ψ''J# and an n-channel transistor r120. j digits d output C as input in negative logic circuit
It consists of a configuration including. In such a configuration, the clock ψ is @
0 #, precharge period, 0 points through plo is 1”
On the other hand, point D is preset to '0#' via p. At this time, nl. , n20 are all ""
OFF"'L, so the DC bus is j.

It does not exist in any of the j+1 digit logic circuits. Clock ψ11#, sampling period, pto+pzo are “OF
F'l..."Since IO+n20 is 'ON', there is no DC bus anywhere, but in the jth digit, n11~"
The value of the 0 point is determined in the state of 14. Here, the j-th digit input is allowed to change by only -1 in the direction of "0#→"1"' during this sampling period.

Along with this, the value of the 0 point changes from '1-' or '1' to '0#' during this time, and logically this value is the inverted carry value here. On the other hand, the logic of the j+1st digit is p
Point D is determined in the state of 21 to p24, but at the j+1st digit, the input is allowed to change only once in the direction of @I 1 # → "0" during this sampling period, so the jth digit input to this digit is consistent with the change in carry output. Also, the j+1st digit is in negative logic, so even if the inverted logic of the j+1st carry carry is directly input as a carry signal, it is logically consistent, and the output is also the same as the negative logic carry. Since it is inverted logic, it can be used directly as a positive logic machine. In this way, it is possible to connect the output of the j+1st digit to a circuit similar to the logic circuit of the jth digit, and
As the carry input for the jth digit, the carry output can be connected with a circuit configuration similar to the j+1st digit in this example, so this type of configuration can be connected in cascade in multiple stages to form a domino circuit that propagates the logic signal in a chess-like manner. Is possible.

As explained above, during the precharge period, pull-
The output points that are pulled up and the output points that are pulled up during the sampling period are
a first positive logic circuit stage sandwiched between points to be down;
It is controlled by an input including at least one output of the first logic circuit stage, and is composed of elements having a complementary relationship with the elements constituting the first logic circuit, and during the precharge period, the pull-d
Owned output point and pull-u during sampling period
A domino circuit that is composed of a second negative logic circuit stage sandwiched between two negative logic circuits, or a CMO8 logic circuit connected in a chain of these stages, is fast, has a small number of elements, and has the characteristic of low current consumption peculiar to 0MO8. It is sure to have a significant effect on structuring the system.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram configuring a carry circuit such as a full adder, which is one of the conventional dynamic CMO8 logic circuits and is made up of domino circuits configured so that logic signals are propagated in a chess-like manner. Configure the i-th digit logic circuit. Second
The figure is a domino circuit diagram showing an embodiment of the present invention, and is an example in which a carry circuit is configured in the same way as in FIG. 1. p-channel transistors constituting the j-th digit logic circuit.

Claims (1)

[Claims] a first logic circuit group interposed between an output point to be precharged and a node to be reset during a sampling period; and a first logic circuit group controlled by an input including at least an output of the first logic circuit. A CM OS @ logic circuit that is composed of elements that are complementary to the constituent elements and includes a second logic circuit group that is interposed between an output point that is reset during a precharge period and a node that is charged during a sampling period.