JPH0693603B2 - Data strobe circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a data strobe circuit for strobing data consisting of a digital signal obtained by reproduction in, for example, an R-DAT.

[Technical Background of the Invention and Problems Thereof] The function required as a data strobe circuit is to accurately measure the position of an input digital signal from the edge of the signal waveform by 1/2 the clock period plus an integral multiple of the clock period. Strobe at, which allows the input digital signal to be read with a minimum error rate.

Conventionally, as this type of circuit, a circuit having a configuration shown in FIG. 5 is known. In the figure, 1 is 8 in the case of R-DAT, for example.
-10 Input terminal for inputting modulated digital signal, 2
Is a delay unit that delays the digital signal input to the input terminal 1 for a predetermined time, for example, a delay line, a delayed multivibrator, and the like, and 3 multiplies the input digital signal and the digital signal delayed by the delay unit 2. The multiplier 3 produces a pulse having a pulse width equal to the delay time of the delay means 2 rising at the edge portion of the waveform of the input digital signal.

4 is a phase detector (P
D) 5 is a low pulse filter (LPF) as a PLL loop filter, 6 is a PLL voltage controlled oscillator (VCO), and 7 is V
It is a D-type flip-flop (FF) as a divider for dividing the oscillation output signal of CO6 by 2,
L is configured.

Reference numeral 8 is a D-type FF as a frequency divider that divides the oscillation output signal of the VCO 6 by 2 like the D-type FF7. The signal divided by the D-type FF8 is divided by the D-type FF7. It is output from the clock output terminal 9 with the phase delayed by 90 °. this
The 90 ° phase delay is necessary to strobe the input digital signal based on the clock signal reproduced by the PLL. 10 is a D type by inverting the oscillation output signal of VCO6
This is an inverter applied to the clock (CK) input of FF8. Reference numeral 11 is a D-type FF that strobes the input digital signal with the clock reproduced by the PLL.
The output of the type FF11 is output from the output terminal 12 as strobe data.

The operation of the circuit having the above-described configuration will be described with reference to each part (a) to (g) in the circuit.
This will be described with reference to FIG.

The output of the multiplier 3 to which the input digital signal shown in FIG. 6 (a) and the input digital signal shown in FIG. 6 (b) delayed by the delay means 2 are input is shown in FIG. 6 (c). A pulse of the waveform shown is obtained. The pulse obtained at the output of the multiplier 3 rises at each rising and falling edge of the input digital signal, and lasts for the delay time Td of the delay means 2 and then falls.
This is hereinafter referred to as an edge pulse.

The PLL composed of PD4, LPF5, VCO6 and frequency divider 7 is
The edge pulse shown in FIG. 6 (c) and the output signal of the frequency divider 7 shown in FIG. 6 (d) operate so as to be phase locked. The condition for phase locking of this PLL is that the average value of the output signal of PD4 shown in FIG. 6 (e) becomes zero. In other words, the integrated value of the time of the H level section of the output of PD4 is equal to the integrated value of the time of the L level section. Therefore, in the locked state, there is a 90 ° phase difference between the edge pulse shown in FIG. 6 (c) and the output signal of the frequency divider 7 shown in FIG. 6 (d). The rising edge of the output signal of the frequency divider 7 comes to the center of the edge pulse shown. Now, assuming that the time from the center of the edge pulse to the rising edge and the falling edge is T1 and T2, respectively, T1 = T2 = Td / 2 (1).

Further, the output signal of the frequency divider 8 is delayed in phase by 90 ° from the output signal of the frequency divider 7 as shown in FIG. 6 (f), but the cycle of the output signals of both frequency dividers 7 and 8 is It is the clock cycle itself. When the clock cycle is Tck, the 90 ° phase delay is 1/4 of Tck in time.

From the above, if the time from the edge of the input digital signal to the rising edge of the clock is T, then T = T1 + Tck / 4 = Td / 2 + Tck / 4 (2), and if Td = Tck / 2, then T = 1 / 2 · Tck / 2 + Tck / 4 = 1/2 · Tck (3). Therefore, if the input digital signal is strobed by the output signal of the frequency divider 8, the input digital signal, that is, the input data can be strobed at the ideal strobe point.

In the above-mentioned conventional circuit, when the delay time Td of the delay means 2 increases or decreases from a desired value due to component variations or the like, the strobe point will deviate from the optimum point.

FIG. 7 and FIG. 8 show the waveforms of the respective parts when the delay time of the delay means 2 is longer and shorter than the optimum time. The edge pulse shown in FIGS. 7 (c) and 8 (c) and the output signal of the frequency divider 7 shown in FIGS. 7 (d) and 8 (d) are divided in the center of the edge pulse. Since the phase is locked in the PLL so that the rising edge of the output signal of 7 comes, the strobe point shifts from the optimum position when the duration of the edge pulse changes due to the change of the delay time Td of the delay means 2. This shift time is shown as Toff in FIGS. 7 and 8.

This Toff is Toff = Tck / 2− (Td / 2 + Tck / 4) = Tck / 4−Td / 2 (4) as is clear from the above equation (2). When Toff obtained by the equation (4) is negative, the strobe point is delayed from the optimum position, and when positive, it is advanced.

Therefore, in the conventional circuit of this type, the delay means 2 is configured to be manually adjustable to eliminate the deviation of the delay time from the optimum value due to the component variation, but this adjustment increases the cost. Was imitating. In addition, even if it is adjusted once, the delay time may change afterwards due to external factors, and in such a case, no measures could be taken.

[Object of the Invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks of the prior art, and makes it possible to automatically adjust the delay time so that the edge of the clock always comes to the center of the input digital signal, thereby making the adjustment work unnecessary. An object of the present invention is to provide a data strobe circuit capable of always strobing input data accurately.

[Outline of Invention]

In order to achieve the above object, the data strobe circuit according to the present invention has a delay for delaying an input digital signal in order to obtain an edge pulse used for generating a recovered clock for strobing the input digital signal at an optimum timing. The delay time of the circuit is variable. Then, the delay time is obtained by strobing the input digital signal at the rising edge of the reproduction clock and outputting the data obtained as strobe data by the first strobe means and the exclusive OR of the input digital signal, and Area comparison type by the output of the first strobe means and the exclusive OR of the output of the second strobe means for outputting the data obtained by strobing the output of the first strobe means at the falling edge of the recovered clock. It is controlled by the signal obtained by performing the phase comparison of.

The optimum strobe point is the midpoint between the rising section and the falling section of the input digital signal at the rising edge of the recovered clock.When the input digital signal is strobed at such a point, the input digital signal and strobe data are 1/4 cycle between the strobe data and the signal obtained by strobeing the strobe data with the falling edge of the reproduction clock, and 1/4 cycle, and the input digital signal and strobe data falling edge of the reproduction clock. 1/2 with the signal obtained by strobing with edges
The period and the phase are shifted from each other.

Therefore, when the area comparison type phase comparison is performed by the two exclusive ORs, a signal corresponding to the deviation from the desired relationship is obtained, and by utilizing this, the delay time of the delay circuit is controlled, The recovered clock always rises at the center of the input digital signal, which makes it possible to always accurately strobe the input data without troublesome adjustment work.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data strobe circuit according to the present invention.

In the figure, 21 is an input terminal, 23 is a multiplier, 24 is a phase comparator (PDI), 25 is a low-pass filter (LPFI), 26 is a VCO,
27 and 28 are frequency dividers, 29 is a clock output terminal, 30 is an inverter, and 32 is a data output terminal. These correspond to the reference numerals 1, 3 to 10 and 12 described above with reference to FIG. 5, respectively. There is.

35 is a variable delay circuit that is composed of, for example, a delayed multivibrator, CCD, shift register, etc., and can electrically control the delay time, 36 is an area comparison type phase comparator (PDII), and 36a is a D input. First strobe means for outputting strobe data obtained by striking the input digital signal to the Q output of the frequency divider 28, that is, the reproduction clock, and strobing the input digital signal at the rising edge of the reproduction clock. D-type FF as
In 36c, the Q output of the D-type FF 36a, that is, strobe data is applied to the D input, and the Q output of the frequency divider 28 inverted by the inverter 36b, that is, the regenerated clock is applied to the CK input. The D-type FF serves as the second strobe means for outputting the data obtained by strobing the data. The strobe data of the Q output of the D type FF 36a is output from the output terminal 32 as data. In addition, 36 is an area comparison type phase comparator (PDII),
37 is a low-pass filter (LPFI
I).

The phase comparator (PDII) 36 has exclusive OR (exclusive OR; EXOR) circuits 36d and 36e, and strobe data is applied to one input of each of these EXOR circuits 36d and 36e. . The input digital signal before delay is applied to the other input of the EXOR circuit 36d, and the Q output of the D-type FF 36c as the second strobe means is applied to the other input of the EXOR circuit 36e. The EXOR circuits 36d and 36e are applied to the non-inverting input and inverting input of the adder 36f, respectively. A signal reflecting the phase relationship among the strobe data, the input digital signal, and the reproduction clock is output to the output of the adder 36f, and this signal is applied as a control signal to the variable delay circuit 35 via the LPFII 37.

The operation of the circuit configured as described above is performed by
This will be described with reference to FIG. 2 showing the waveforms (f) and (h) to (k).

The waveforms shown in FIGS. 2 (f) and (g) are obtained by the same operation as the conventional circuit described above with reference to FIG. D
The type FF 36c latches the strobe data obtained at the output of the D type FF 36a at the timing corresponding to the falling edge of the reproduction clock shown in FIG. 2 (f) and outputs the signal shown in FIG. 2 (h). The EXOR circuit 36d receives the input digital signal shown in FIG. 2 (a) and the strobe data shown in FIG. 2 (g).
EXOR is taken and the signal shown in FIG. 2 (i) is output to the output. The EXOR circuit 36e takes the EXOR of the data shown in FIG. 2 (g) and the output signal of the D-type FF 36c shown in FIG. 2 (h), and outputs the signal shown in FIG. 2 (j). EXOR circuit 36d
The output signals of 36e and 36e are added by the adder 36f, and the signal shown in FIG. 2 (k) is output to the output.

The output signal of the adder 36f shown in FIG. 2 (k) is at equal time intervals when the delay time of the variable delay circuit 35 has an optimum value and the rising edge of the reproduction clock coincides with the center of the input digital signal. It swings positive and negative. Therefore, the output of the LPFII 37 to which the output signal of the adder 36f is input, that is,
The control signal of the variable delay circuit 35 is zero, and the delay time is kept as it is.

FIG. 3 shows the waveform of each part when the delay time of the variable delay circuit 35 is larger than the optimum value, and the output signal of the adder 36f is the third
As shown in FIG. 9 (k), the time on the positive side becomes longer than the time on the negative side, which causes a positive control signal to be generated at the output of the LPFII 37. This positive control signal controls the variable delay circuit 35 in such a direction that its delay time becomes shorter.

FIG. 4 shows the waveform of each part when the delay time of the variable delay circuit 35 is smaller than the optimum value, and the output signal of the adder 36f is the fourth
As shown in FIG. 9 (k), the time on the negative side is long, which causes the variable delay circuit 35 to be applied with a negative control signal via the LPF II 37 and controlled so that its delay time becomes long.

〔The invention's effect〕

As described above, according to the present invention, the delay time of the means for delaying the input digital signal is electrically automatically controlled so as to raise the reproduction clock at the center of the input digital signal. The effect that the troublesome adjustment work becomes unnecessary and the strobe of the input digital signal can always be performed at the optimum position can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data strobe circuit according to the present invention, and FIG. 2 is a waveform diagram showing waveforms of respective parts when the delay time of the variable delay circuit in FIG. FIG. 4 is a waveform diagram showing the waveform of each part when the delay time is large, FIG. 4 is a waveform diagram showing the waveform of each part when the delay time is small, and FIG. 5 is a block diagram showing an example of a conventional data strobe circuit. FIGS. 6 to 8 are waveform diagrams showing waveforms of respective portions when the delay time of the delay means of FIG. 5 has an optimum value, when it is large and when it is small. 23 …… Multiplier 24 …… Phase comparator (PLL) 25 …… LPFI (PLL) 26 …… VCO (PLL) 27, 28 …… Divider (PLL) 36a …… D-type FF (first strobe) Means) 36c …… D type FF (second strobe means) 36 …… area comparison type phase comparator 36d, 36e …… EXOR circuit 36f …… adder

Claims (1)

[Claims] 1. A variable delay circuit for delaying an input digital signal, the delay time of which can be electrically controlled, and an edge pulse obtained by multiplying the input digital signal delayed by the variable delay circuit and the input digital signal. A multiplier for outputting, a phase-locked loop for generating a reproduction clock based on the edge pulse from the multiplier and outputting the reproduction clock as a clock, and a strobe of the input digital signal at the rising edge of the reproduction clock. First strobe means for outputting the strobe data as strobe data; second strobe means for outputting the data obtained by strobing the output of the first strobe means at the falling edge of the reproduction clock; 1 output of the strobe means and the exclusive OR of the input digital signal, and the first strobe Area comparison type that performs an area comparison type phase comparison by the output of the first strobe means and the exclusive OR of the output of the second strobe means, and outputs a signal according to the delay or advance of the strobe point in the first strobe means. A data strobe circuit comprising a phase comparator, wherein the delay time of the variable delay circuit is controlled by the output of the area comparison type phase comparator.