JPS62173831A - Bit synchronizing signal reproducing circuit - Google Patents

Abstract

PURPOSE:To obtain a stable and accurate output by converting the edge part of a PCM signal including a jitter component to positive and negative pulses based on zero and feeding back the phase difference to a voltage controlled oscillator through a loop filter. CONSTITUTION:A digital signal S1 including a jitter component is delayed by a time corresponding to a half clock having a minimum repeat width 1/fmax of the signal S1 through a CR integrated circuit 6 and an inverter 7. Exclusive OR between this delays signal and the original signal S1 is operated to detect the edge part. The oscillation output of a voltage controlled oscillator VCO 4 has the frequency divided by a 1/N frequency divider 5 and has the timing adjusted by a timing circuit 9 so that the high level having a width 2fmax is equally divided into two by the trailing of the clock. The pulse in the edge part is equally divided into two by AND and inverter AND between outputs of the timing circuit 9 and an exclusive OR circuit 8. The difference of pulse width between positive and negative pulses is obtained by TTLs 12 and 13 and is fed back to the VCO 4 through a loop filter 2 and a DC amplifier 3. Thus, an accurate signal is reproduced stably.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is based on PCM (Pulse Code Mo
The present invention relates to a bit synchronization signal reproducing circuit for regenerating a bit synchronization signal that provides accurate bit timing in transmission (duration).

[Prior Art] Bit timing information of reproduction information in PCM transmission includes an external timing signal and a self-timing signal. Among these, the external timing signal is transmitted via a separate cable, superimposed on the same cable with the PCM signal, or inserted in a time-sharing manner with the PCM signal.

On the other hand, self-timing signals extract timing components from the code sequence itself to be reproduced or received.
It has been widely used in this type of bit synchronization signal reproducing circuit since it is easy to operate and hardly causes a phase deviation with the reproduced code. Therefore, a phase synchronized type for extracting the self-timing signal, that is, P L
A conventional example of an L (Phase Locked Loop) circuit is shown in FIG.

This PLL circuit consists of phase comparators 1. Loop filter 2.
DC amplifier 3. Voltage controlled oscillator 4. and a 1/N frequency divider 5.

In the above configuration, the PCM data S1 and the output signal S2 of the voltage controlled oscillator 4 are input to the phase comparator 1, phase detection is performed by the phase comparator 1, and a phase error signal serving as a jitter component is output. .

The output signal S3 of this phase error is guided to a loop filter 2, where it is converted into a DC component and used as a control voltage for the next voltage controlled oscillator 4.

The clock generated by this voltage controlled oscillator 4 is
Negative feedback is sent to the phase comparator 1 via the 1/N frequency divider 5, and a closed loop is formed in which the data is compared with the next data and phase detection is performed.

[Problems to be Solved by the Invention] Since the conventional PLL circuit has a closed-loop configuration as described above, it has difficulty tracking phase errors.

There were problems such as a wide lock-in range, short pull-in time, and other unstable aspects, and the need for numerous adjustments and stabilizing elements.

The present invention has been made to solve the above-mentioned problems, and aims to provide a bit synchronization signal regeneration circuit in PCM transmission that has good followability for phase errors and can provide a stable and accurate output voltage. purpose.

[Means for Solving the Problems] A bit synchronization signal reproducing circuit according to the present invention generates positive pulses in the positive direction and in the negative direction with respect to zero volts at the edge portion of a PCM signal containing a jitter component.

A conversion means for converting the pulse into a negative pulse is provided.

[Operation] In the bit synchronization signal reproducing circuit according to the present invention,
The phase error signal output by the conversion means is fed back to the voltage controlled oscillator via a loop filter, and the PCM
Control is performed by following the fluctuation of the interval between the edge portions of the signal.

[Embodiment] Hereinafter, an embodiment of the bit synchronization signal reproducing circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a bit synchronization signal reproducing circuit showing an embodiment of the present invention.

In the figure, before the loop filter 2, the minimum repetition width (1/2
A CR integration circuit 6 and an inverter 7 are provided as half-clock delay means for generating a signal delayed by half the time (half clock) of f max ). 8 is an exclusive OR circuit that takes the exclusive OR of the signal delayed by the half clock delay means and the original signal; 9 is an inverter 98; a 1/2 frequency divider 9b; a delay flip-flop 9c , and an inverter 9d; 10 is an AND circuit for calculating the AND of the output from the exclusive OR circuit 8 and the output from the timing circuit 9; 11 is the exclusive OR circuit; 8 and the inverted output from the timing circuit 9 obtained via the inverter lla.

12.13 is a transistor transistor for converting the output pulse of the AND circuit 10.11 into output pulses of +12 volts and -12 volts, for example.
nsister Logic), 14.15 is the T
This is a resistor for adding the output of LL12.13.

The above constitutes a means for converting the edge portion of a PCM signal containing a jitter component into a positive pulse signal and a negative pulse signal.

In addition, in the figure, 16 is the PC only when the clock signal from the 172 frequency divider 9d via the inverter 9d is input.
The D input of M data Sl is a delay flip-flop that acts on the circuit.

Next, the operation of the bit synchronization signal reproducing circuit configured as described above will be explained with reference to the timing chart of FIG.

First, the PCM data S1 containing the jitter component shown in {circle around (2)} in FIG. PC via inverter 7
M data S, minimum repetition width (1/2 f max
) is delayed by half a clock, resulting in a pulse signal shown in (■) in the same figure. By taking the exclusive OR of this pulse signal and the original PCM signal S1 in the exclusive OR circuit 8, a pulse signal in which an edge portion, which is a data change point, is detected is obtained, as shown in (■) in the same figure. .

Next, the oscillation output from the voltage controlled oscillator 4 is divided by the 1/N frequency divider 5, and the delay flip-flop 9c of the timing circuit 9 divides the oscillation output by I/2 at a frequency four times fmax. Frequency twice as high as fmax via device 9d ■
is latched, and at the transition point of the falling edge of the clock,
The timing is adjusted so that the high part of the frequency ■, which is twice the f raax, is divided into two equal parts.

Also, by AND circuit 10.11, ■ and ■, respectively.
By taking the AND of the inverted outputs of the pulse signals of ■ and ■,
Divide the pulse signal at the edge portion shown by (2) into two equal parts.

By the way, if the pulse signal at the edge portion indicated by ■ does not include a jitter component, the pulse is completely divided into two equal parts, and the pulse width of the pulse signal indicated by ■ and ■ output from the AND circuit 10.11 is as follows. be equal.

On the other hand, when the pulse interval of the pulse signal shown by ■ becomes more advanced compared to when the jitter component is not included, the pulse width of the pulse signal shown by ■ becomes wider, and the pulse width of the pulse signal shown by ■ becomes narrower. Conversely, if the pulse interval of the pulse signal shown by ■ is delayed compared to when it does not include jitter components, then ■
The pulse width of the pulse signal shown by is narrow, and the pulse width of the pulse signal shown by ■ is wide.

By the above processing, the jitter component of PCM data S1 is reduced by 2
This means that the signal has been converted into a pulse signal with two pulse widths.

Next, by TTL12.13, the pulse signal indicated by ■ is, for example, +12 volts, and the pulse signal indicated by
Each voltage is converted into volts, resistances are added through resistors 14 and 15, and the signal is shaped into an AC waveform signal shown by a square square that swings to +12 volts. When this AC waveform signal shown by ■ is passed through the following loop filter 2 and DC amplifier 3, as shown in ■, if the plus and minus sides are the same width, the DC waveform will be close to zero volts, and the plus width will be large. Then, if the positive DC current becomes large, and the negative width increases, negative DC current will be output.

When this DC output is input to the voltage controlled oscillator 4, a clock is generated that is automatically controlled so that it advances when the edge interval becomes late, and conversely, it lags when the edge interval advances. The bit clock indicated by and the PCM data S1 indicated by [phase] are outputted via the delay flip-flop 16. [Effect of the Invention] As explained above, the bit synchronization signal reproducing circuit of the present invention has the following effects. , convert the edge part of the PCM data into a pulse signal centered on zero volts, and move in the positive direction.

By converting the amount of jitter in the negative direction into a pulse signal having the pulse width of a positive pulse and a negative pulse, it is possible to stably control the DC potential around zero volts with the pulse width of the AC pulse signal, and by increasing the pulse potential, The more the dynamic range of the amount of change increases, the more excellent effects can be achieved, such as the ability to reproduce a bit synchronized signal with excellent followability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bit synchronous signal reproducing circuit showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the bit synchronous signal reproducing circuit, and FIG. 3 is a block diagram of a conventional bit synchronous signal reproducing circuit. FIG. 2 is a block diagram showing an example of a reproducing circuit. 2...Loop filter, 3...DC amplifier, 4...
・Voltage controlled oscillator, 5...1/N frequency divider, 6...C
R integration circuit, 7... Inverter, 8... Exclusive OR circuit, 9... Timing circuit, 10□
11...AND circuit, 12.13...TLL, 14
．． 15...Resistor, 16...Delay flip-flop.

Claims (1)

[Claims] It is equipped with a conversion means that converts the edge portion of the PCM signal containing jitter components into positive pulses and negative pulses in the positive direction and negative direction with zero volts as a reference, and the phase error signal outputted by this conversion means is passed through a loop filter. 1. A bit synchronization signal regeneration circuit characterized in that the bit synchronization signal regeneration circuit is configured to feed back to a voltage controlled oscillator via a PCM signal, and perform control in accordance with fluctuations in interval between edge portions of a PCM signal.