JPH0691075B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0691075B2 JPH0691075B2 JP60129871A JP12987185A JPH0691075B2 JP H0691075 B2 JPH0691075 B2 JP H0691075B2 JP 60129871 A JP60129871 A JP 60129871A JP 12987185 A JP12987185 A JP 12987185A JP H0691075 B2 JPH0691075 B2 JP H0691075B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- silicon oxide
- oxide film
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、表面安定化保護膜について改良を図った半導
体装置に関する。The present invention relates to a semiconductor device having an improved surface stabilizing protective film.
半導体装置は、そのpn接合の露出表面に不純物等が付着
すると劣化の原因となるので、その表面を保護するため
に表面安定化保護膜が被覆される。The semiconductor device is deteriorated when impurities or the like adhere to the exposed surface of the pn junction, and therefore, a surface stabilizing protective film is coated to protect the surface.
第２図はこの表面安定化保護皮膜を示したもので、２は
シリコン半導体基体１の表面を酸化して形成するシリコ
ン酸化膜（SiO2）、３はその上面にプラズマCVDで形成
されるプラズマシリコン窒化膜（SiNH）である。FIG. 2 shows this surface stabilizing protective film, 2 is a silicon oxide film (SiO 2 ) formed by oxidizing the surface of the silicon semiconductor substrate 1, and 3 is a plasma formed on the upper surface by plasma CVD. It is a silicon nitride film (SiNH).
このプラズマシリコン窒化膜３は、柔らかくて硬度が低
いので、樹脂封止の際等の変形に対して割れにくいとい
う利点がある。Since the plasma silicon nitride film 3 is soft and has a low hardness, it has an advantage that it is unlikely to be cracked by deformation such as resin sealing.
ところが、このプラズマシリコン窒化膜３は、水素を含
むために、半導体装置の最終保護膜としてその膜３を形
成する際に、或いはその後のアニール等の熱処理の際
に、水素がシリコン酸化膜２内に拡散して浸入するため
に、半導体装置自体の特性が悪くなり、例えばFETのス
レッシュホールドレベルの変動等が発生し、よって上記
したプラズマシリコン窒化膜３の適用範囲が狭められて
いた。However, since the plasma silicon nitride film 3 contains hydrogen, when the film 3 is formed as the final protective film of the semiconductor device, or during the subsequent heat treatment such as annealing, hydrogen is contained in the silicon oxide film 2. The characteristics of the semiconductor device itself are deteriorated due to the diffusion and infiltration into the semiconductor device, and, for example, fluctuations in the threshold level of the FET occur, which narrows the applicable range of the plasma silicon nitride film 3 described above.
本発明は以上のような点に鑑みて成されたもので、その
目的は、水素による悪影響が生じないようにした半導体
装置を提供することである。The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device in which the adverse effect of hydrogen does not occur.
このため本発明では、半導体基体の表面にシリコン酸化
膜とプラズマシリコン窒化膜を順次積層して表面安定化
保護膜を形成した半導体装置において、上記シリコン酸
化膜と上記プラズマシリコン窒化膜との間に鉛ガラス層
又はアルミナガラス層を介在させて構成した。Therefore, in the present invention, in the semiconductor device in which the silicon oxide film and the plasma silicon nitride film are sequentially laminated on the surface of the semiconductor substrate to form the surface stabilizing protective film, between the silicon oxide film and the plasma silicon nitride film. It was configured with a lead glass layer or an alumina glass layer interposed.
以下、本発明の実施例について説明する。第１図はその
一実施例を示すものである。本実施例では、水素の透過
係数の小さい鉛ガラス層４をシリコン酸化膜２とプラズ
マシリコン窒化膜３との間に介在させて、その鉛ガラス
層４により、例え高温となっても、プラズマシリコン窒
化膜３からの水素がシリコン酸化膜２内に浸透しないよ
うにしている。Examples of the present invention will be described below. FIG. 1 shows an embodiment thereof. In the present embodiment, a lead glass layer 4 having a low hydrogen permeability coefficient is interposed between the silicon oxide film 2 and the plasma silicon nitride film 3, and the lead glass layer 4 allows the plasma silicon to be formed even at high temperatures. Hydrogen from the nitride film 3 is prevented from penetrating into the silicon oxide film 2.
上記鉛ガラス層４を形成する方法としては、鉛ガラスを
直接堆積するスパッタやCVD法があり、またシリコン酸
化膜２の上に鉛（Pb）を載せてから、低温アニールし、
鉛ガラス（SiO2＋Pb）とする方法もある。後者の方法は
極めて簡単である。As a method of forming the lead glass layer 4, there is a sputtering method or a CVD method in which lead glass is directly deposited, and after placing lead (Pb) on the silicon oxide film 2, low temperature annealing,
There is also a method of using lead glass (SiO 2 + Pb). The latter method is extremely simple.
この鉛ガラスは、温度400℃での水素透過率が10-14cc・
mm/sec・cm2・Torrでシリコン酸化物（シリコン酸化膜
２）に比較して1/105倍であり、水素の透過を問題のな
い程度まで遮断する。This lead glass has a hydrogen permeability of 10 -14 cc
It is 1/10 5 times that of silicon oxide (silicon oxide film 2) in mm / sec · cm 2 · Torr, and cuts off hydrogen permeation to the extent that there is no problem.
なお、上記した鉛ガラス層に代えて、別アルミナガラス
等を使用することもできる。Instead of the lead glass layer described above, another alumina glass or the like can be used.
以上から本発明によれば、プラズマシリコン窒化膜から
シリコン酸化膜に対する水素の浸透を効果的に防止する
ことができ、素子の安定化を実現することが可能とな
る。As described above, according to the present invention, it is possible to effectively prevent the permeation of hydrogen from the plasma silicon nitride film into the silicon oxide film, and to realize the stabilization of the device.
第１図は本発明の一実施例の半導体装置の表面安定化保
護膜の部分の断面図、第２図は従来の半導体装置の表面
安定化保護膜の部分の断面図である。 １……半導体基体、２……シリコン酸化膜、３……プラ
ズマシリコン窒化膜、４……鉛ガラス層。FIG. 1 is a sectional view of a surface stabilizing protective film portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a surface stabilizing protective film portion of a conventional semiconductor device. 1 ... Semiconductor substrate, 2 ... Silicon oxide film, 3 ... Plasma silicon nitride film, 4 ... Lead glass layer.
Claims (1)
ズマシリコン窒化膜を順次積層して表面安定化保護膜を
形成した半導体装置において、 上記シリコン酸化膜と上記プラズマシリコン窒化膜との
間に鉛ガラス層又はアルミナガラス層を介在させたこと
を特徴とする半導体装置1. A semiconductor device in which a silicon oxide film and a plasma silicon nitride film are sequentially laminated on a surface of a semiconductor substrate to form a surface stabilizing protective film, wherein a lead is provided between the silicon oxide film and the plasma silicon nitride film. Semiconductor device characterized by interposing a glass layer or an alumina glass layer
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60129871A JPH0691075B2 (en) | 1985-06-17 | 1985-06-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60129871A JPH0691075B2 (en) | 1985-06-17 | 1985-06-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61288430A JPS61288430A (en) | 1986-12-18 |
| JPH0691075B2 true JPH0691075B2 (en) | 1994-11-14 |
Family
ID=15020360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60129871A Expired - Fee Related JPH0691075B2 (en) | 1985-06-17 | 1985-06-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691075B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0828356B2 (en) * | 1987-10-19 | 1996-03-21 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0630355B2 (en) * | 1983-05-16 | 1994-04-20 | ソニー株式会社 | Semiconductor device |
| JPS60224229A (en) * | 1984-04-20 | 1985-11-08 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-06-17 JP JP60129871A patent/JPH0691075B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61288430A (en) | 1986-12-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |