JPH0683564A - Display controller and control method - Google Patents

Abstract

PURPOSE:To improve the picture drawing performance when a hardware cursor is moved by synthesizing a cursor and display data based on display data subjected to binarization processing and a position stored in a storage means. CONSTITUTION:A binarizing data processing section 204 applies binarizing processing such as error propagation and dither to display data among data demultiplexed by a signal demultiplexer section 202. A sprite processing section 205 receives data relating to sprite processing among data demultiplexed by the signal demultiplexer section 202, stores a sprite pattern to a sprite memory 206, reads as required a sprite pattern from the sprite memory 206 and sends the read pattern to a synthesis processing section 207. The synthesis processing section 207 synthesize the display data from the binarization processing section 204 and the data of the sprite pattern fed from the sprite processing section 207 in a desired timing and logic and gives the result to a display screen 208.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and method, and more particularly, it can hold a display state updated by applying an electric field or the like by using a ferroelectric liquid crystal as an operation medium for display update. The present invention relates to a display control device and method for a display device including a display element.

[0002]

2. Description of the Related Art Generally, in information processing systems and the like, a display device is used as an information display means that fulfills the function of visually expressing information. As such a display device, a CRT is used.
Display devices are widely known.

In the display control of the CRT display device, the C
The writing operation of the system side CPU to the video memory as the display data buffer of the RT side, and the CRT
The operation of reading and displaying the display data from the video memory by, for example, the CRT controller on the side is independently executed.

In the case of CRT display control as described above,
The writing of display data to the video memory for changing the display information and the operation of reading the display data from the video memory and displaying the data are independent, so the program on the information processing system side considers the display timing etc. There is an advantage that desired display data can be written at any timing without needing to do so.

Further, in the operation of reading display data from the video memory and displaying it, in order to sequentially read the display data from the video memory and determine the position to be displayed on the CRT, a horizontal synchronizing signal, a vertical synchronizing signal, and a blank signal. The display data is transmitted in synchronization with the above.

On the other hand, the CRT requires a certain length in the thickness direction of the display screen, so that the volume as a whole becomes large, and it is difficult to reduce the size of the entire display device.
Further, this impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

A liquid crystal display (hereinafter, referred to as LCD) can be used to supplement this point. That is,
According to the LCD, it is possible to reduce the size (in particular, reduce the thickness) of the entire display device. In such LCD, the above-mentioned ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroselect) is used.
There is a display (hereinafter referred to as FLCD: FLC display) using a liquid crystal cell of ric liquid crystal (hereinafter, referred to as FLCD: FLC display), and one of its features is that the liquid crystal cell has a storage state of a display state against application of an electric field. It is in. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and excluding the electric field. However, each alignment state is maintained.

Due to the bistability of such FLC molecules,
The FLCD has a memory property. Such FLC and F
Details of the LCD are described in, for example, Japanese Patent Application No. 62-76357.

As a result, when driving the FLCD,
Unlike CRTs and other liquid crystal displays, there is a time margin in the cycle of continuous refresh drive of the display screen.
Apart from the continuous refresh driving, partial rewriting driving for updating the display state of only the portion corresponding to the change on the display screen is possible.

Because of the above-mentioned characteristics, it is difficult to make a multi-gradation display color tone having continuity in display color tone as compared with the case of a CRT, and as a means for solving this, a small number of colors is used. Binary processing such as the error diffusion method, the ED method, and the dither method is performed on the display device in advance to perform apparent multi-gradation display.

The hardware cursor is VRA.
In addition to the image information existing on M, it has cursor position information and cursor shape information, which is output to the display device by using the superimpose function, and delays the cursor moving on the display screen at high speed. It is a function to display smoothly on the display screen without any.

[0012]

However, in the above-mentioned conventional example, when the binarization process is performed on the display side, whether information about whether or not it is a binarization process target is received from the display controller unit as the area separation information. ,
Alternatively, it is necessary for the display side to judge from the image data content. In either method, sprite expression, which is generally called mouse display, moves on the screen at high speed, so if you binarize it without separating it, its outline will not be emphasized and it will be difficult to see. In addition, when the sprite display moves on the screen, there is a possibility that the portion and the ripple portion due to the binarization of the surrounding area may be different from the expected image. These cause deterioration of image quality, and the instruction pattern displayed by the sprite function is the part that the user particularly pays attention to in the entire screen.
Even if the image quality is deteriorated in a small range, it cannot be ignored.

Further, in the case of having the function of supporting the hardware cursor, there were the following drawbacks. (1) When the hardware cursor moves at high speed, there is a drawback that the cursor image is destroyed by the procedure of partial rewriting. (2) It was necessary to perform partial rewriting at high speed when the hardware cursor moved at high speed.

When partial rewriting is performed by giving priority to the display of the mouse cursor, when the screen rewriting speed decreases, the display quality deteriorates although it moves in synchronization with the mouse cursor.

FIG. 20 shows a display example of an object that moves in synchronization with the mouse. The display example of FIG. 20 is Microsoft.
It is a window system such as Windows (Microsoft Corporation). The user can move the window by moving the mouse cursor over the title bar at the top of the window and dragging. At this time, the window display and the cursor display move in synchronization. In such a case, prioritizing the mouse display deteriorates the display quality of the moving window.

Further, the partial rewriting of the FLCD is performed in units of horizontal lines. If the display of the mouse cursor is prioritized, the line on which the mouse cursor is located and the other line are misaligned in drawing, and the display is difficult for the user to see.

It is an object of the present invention to solve the above-mentioned drawbacks by performing sprite processing in a route different from that of the binarization processing when the display processing is performed.

Another object of the present invention is to improve the drawing performance when the hardware cursor is moved by rewriting the cursor partly by interlacing when the hardware cursor is moved.

Further, according to the present invention, it is determined whether or not there is a region which moves in synchronization with the mouse cursor, and when there is no region which moves in synchronization with the mouse cursor, the mouse cursor is preferentially displayed and synchronized with the mouse cursor. When there is a moving area, the mouse cursor is not preferentially displayed, and the user's attention is aimed at improving the display of the area.

[0020]

According to the present invention, a storage means for storing display data, a processing means for binarizing the display data, a storage means for storing the position of a cursor, and the binary value are provided. It is composed of combining means for combining the converted display data and the cursor as display data based on the position stored in the storage means, and display control means for displaying the display data on the display means.

Further, according to the present invention, in a display control device of a display device capable of updating a display state of a display element associated with a change in display, a storage means for storing display data, a first cursor shape and a second cursor shape. A shape storing means for storing a cursor shape, a storage means for storing cursor display position information, a detecting means for detecting movement of the cursor, and a first cursor shape when the detecting means moves the cursor. And a control means for displaying the cursor in the second cursor shape when the cursor is not moving.

Further, according to the present invention, in a display control device of a display device capable of updating a display state of a display element according to a change of display data, a storage means for storing the display data, a movement of a cursor and a synchronization with the cursor. And means for detecting the presence or absence of an area to be moved, and display control means for prioritizing display of the cursor when there is no area to move in synchronization with the cursor.

Further, according to the present invention, the display data is stored, the display data is binarized, the cursor based on the cursor position information and the binarized display data are combined, and the combined display data is converted. It consists of a display structure.

Furthermore, the present invention is a display control method of a display device capable of updating the display state of a display element associated with a change in display, detects movement of a cursor, and when the cursor is moving, displays means The display is made in the first cursor shape, and when the cursor is not moving, it is displayed in the second cursor shape on the display means.

Further, according to the present invention, in the display control method of the display device capable of updating the display state of the display element according to the change of the display data, the movement of the cursor and the presence / absence of the area moving in synchronization with the cursor are detected. However, when there is no area that moves in synchronization with the cursor, the cursor display is prioritized over the display of the display data.

With the above arrangement, the present invention focuses on the movement of the cursor and performs display control according to the movement of the cursor.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system including a display control device according to an embodiment of the present invention.

In the figure, 101 is a CPU that controls the entire information processing system, 102 is an arithmetic processor that supports the arithmetic processing of the CPU 101 at high speed, and 103 is a CPU.
A ROM that stores a program that realizes the basic control function of 101, and 104 is a main memory that stores a program that the CPU 101 executes and that is used as a work area for this execution. Also used as screen memory.

Reference numeral 105 denotes a DMA controller (Direct) which transfers data between the main memory 104 and VRAMs described later, or between those memories and various devices constituting the present system without the control of the CPU 101.
Memory Access Control
r, hereinafter referred to as DMAC), 106 is an interrupt controller for controlling hardware interrupt requests generated by various devices making up this system, 107 is a C-MOS RAM for storing calendar, clock function and non-flash information. Real time clock including 108, a lithium battery for backup for the real time clock 17 to function even when the system is powered off, 109 a keyboard for inputting character information such as various characters and control information, and 110 a A keyboard controller for controlling the keyboard 109, 111 is a hard disk device as an external storage device, 112 is an HD for performing data transfer and other control between the hard disk device 111 and this system.
D (Hard Disk Drive) controller,
Reference numeral 113 is a floppy disk device as an external storage device, and 114 is an FDD (Fl) for performing data transfer and other control between the floppy disk device 113 and this system.
oppy Disk Drive) controller, 11
5 is a mouse as a pointing device, 116 is a mouse controller for connecting signals between the mouse 115 and this system, 117 is RS232 for connecting an external input / output device having an RS232C system interface.
The present invention is a C interface, 118 is a printer interface for connecting an external printer or other external devices, and 200 is an interface between a display screen using a ferroelectric liquid crystal as its display medium and an FLCD controller described later. A display unit (hereinafter, referred to as FLCD) having a signal processing circuit according to one embodiment, 240 is an FLCD controller having an interface with the FLCD 200 according to one embodiment of the present invention, and 280 is an FLCD2.
A display interface 119 between 00 and the FLCD controller 240 is a system bus including a data bus, a control bus, and an address bus for signal connection between the above-mentioned devices.

FIG. 2 is a block diagram showing details of the FLCD controller 240.

Reference numeral 241 is a bus interface including a data bus, a control bus and an address bus of the system bus 119 and a buffer for connecting the internal circuits of the display controller 240, a driver, an address decoder and other circuits, and 242 is the CPU 101 and others. The command and data sent from the device connected to the system bus 119 are analyzed, processed, or calculated, thereby passing a control signal to a display controller described later, or C
PU101 or other command or data sent from a device connected to the system bus 119, or data in a video memory described below is analyzed, processed, or operated, and display data generated thereby is stored in the video memory described below. A processor 243 is a display controller, which generates various display timings under the control of the display processor 242 or the CPU 101, and a system bus 119.
Alternatively, the display data from the display processor 242 is stored in a video memory described later, and the DRA of the video memory described later is stored.
The refresh operation of the M element is performed.

Further, the display controller 243 reads out the data to be displayed together with the control signal from the video memory, which will be described later, and outputs it directly or after processing it.

244 is a display processor 242, a display controller 243, a video memory which can be read / written by the CPU 101 and various devices connected to the system bus 119, and 245 is a display processor 242, which displays sprite information such as the mouse 115. Controller 243 or CPU 101 or other system bus 11
A sprite interface 246 which receives information from various devices connected to the device 9 and converts the information into a format required by the FLCD interface described later is supplied from the display controller 243 with data for display and control signals and from the sprite interface 245. It is an FLCD interface for converting the sprite information to be converted into a format required by the FLCD 200.

FIG. 3 is a block diagram showing the details of the FLCD 200.

In the figure, 201 is an FLCD controller interface for exchanging signals with the FLCD controller 240, and 202 is an FLCD controller 240.
Received from the FLCD controller interface 201 and separated by function, and
FLCD controller 240 generated in FLCD 200
Data sent to the FLCD controller interface 2
A signal separation unit to pass to 01, 203 receives data relating to control among the data separated by the signal separation unit 202, thereby controlling each function in the FLCD 200, and 204 separated by the signal separation unit 202. A controller 203 is a binarization processing unit that performs binarization processing such as error diffusion and dither on display data among data.
Select whether or not to perform binarization under the control from. When the binarization processing is not performed, it has a function of converting the data into the number of display colors of the display screen described later.

Reference numeral 205 receives the data related to the sprite processing out of the data separated by the signal separation unit 202, stores the sprite pattern in a sprite memory described later, and reads the sprite pattern from the sprite memory as necessary, and the sprite pattern is described later. Is a sprite processing unit to be sent to the synthesizing unit, and reads and writes the sprite memory under the control of the controller 203. Furthermore, when there are a plurality of sprite patterns, the sprite processing unit 205 also selects a sprite pattern.

Reference numeral 206 denotes a sprite memory which is read and written under the control of the sprite processing unit 205, and can store one or a plurality of sprite patterns. Further, the sprite memory 206 can store other necessary control data.

Reference numeral 207 is a combining process in which the display data supplied from the binarization processing unit 204 and the sprite pattern data supplied from the sprite processing unit 205 are combined at desired timing and logic and sent to a display screen described later. The controller 203 controls the timing of combining, logic, and other necessary controls.

A display screen 208 is a visual output means,
It is composed of a display device, a driver, and the like. Display data is given from the synthesis processing unit 207, and control signals such as timing signals are given from the controller 203.

FIG. 4 is a conceptual diagram showing the control structure of the display device.

Reference numeral 401 is an application program operating on the information processing system, 402 is a graphic display interface (GDI) in WINDOWS of Microsoft Corporation, 403 is a device driver, 404 is hardware, and in this case, the FLCD described below is Not included.

Reference numeral 405 is a display (DISP) showing a part or all of the display screen of the FLCD 200.

In a general information processing system, the application program 401 is the hardware 40.
It is usual to make it independent of 4 from the viewpoint of cost and resources. In this case, the hardware 40
The difference of 4 is absorbed (or interfaced) by the device driver 403. Now, when handling the control of the graphic screen, the application program 401
Then, the number of colors is represented by the maximum that can be represented by a program so as not to depend on the hardware 404.

This is a general method in consideration of compatibility of the hardware 404 and future expandability.

The maximum number of colors that can be handled by the application program 401 is about 16.7 million colors. Each of the three primary colors of red (hereinafter referred to as R), green (hereinafter referred to as G), and blue (hereinafter referred to as B) is 8 bits, which is a total of 24 bits.

In this case, if the color display capability of the display 405 is 16 colors, it is necessary to convert the expression of about 16.7 million colors into 16 colors. Here, the general one is the device driver 403 or the hardware 404.
In FIG. 5, a method of simply converting (rounding) about 16.7 million colors 411 into 16 colors 413 using the table 412 (FIG. 5). Similarly, in the device driver 403 or the hardware 404, an error diffusion method, an ED method, a dither method, etc. The binarization process 414 is performed, and the binarized 1
This is a method (FIG. 6) of using the six-color representation 415.

It is advantageous in terms of final image quality to adopt the former method for characters and the like, and the latter method for pictures and multi-gradation images such as pictures.

Since various methods have been proposed as methods of identifying, separating, and switching the screen information when the former method, the latter method, or both are switched and processed,
The description is omitted.

In FIG. 4, when the application program 401 expresses the number of colors by about 16.7 million colors and the display 405 has the capability of expressing 16 colors, the application program 401 attempts to express multicolors such as photographs and pictures. In that case, the binarization process can be performed by any of the application program 401, GDI 402, device driver 403, hardware 404, and display 405.

When the display 405 has this binarization processing, the information as to whether it is a target of the binarization processing is received from the hardware 404 as the area separation information, or from the image data contents on the display 405. You can judge.

The former can be realized relatively easily because information can be obtained from a higher level such as the device driver 403.

In the latter case, since it is necessary to process high-speed image data in real time, its realization becomes somewhat difficult.

In any of the methods, the sprite display such as an arrow-shaped cursor, which is generally used as a means for visually indicating the position on the display screen, moves on the screen at high speed, so that it is different from other information. If the binarization processing is performed in a unified manner without separating the contours, the contours will not be emphasized and will be difficult to see. Also, for the binarization process,
When the sprite display moves, the calculation of the ripple due to the binarization of the part and the surrounding becomes different from what is originally expected, which causes the deterioration of the image quality of the picture and the like.

As for the sprite display, the contents are directly written in the video memory 244, which is expressed by scanning the entire screen, and a memory is separately provided in another area, and a sprite pattern is previously stored in the memory. By writing and setting the display controller 243 or the like at which position on the screen the sprite pattern is to be displayed, the sprite pattern is read from the memory at a desired timing in terms of hardware and read from the video memory. There is a display controller 240 that controls the display content by superimposing the displayed content and sending it to the display unit 200.

The latter is becoming popular because the sprite pattern can be moved at high speed.

In FIG. 2, the function of the sprite interface 245 does not have the memory for the sprite pattern, but is set by the display processor 242, the display controller 243, the CPU 101, and other various devices connected to the system bus 119. When a sprite pattern to be generated, its display position, a logic for combining with a video output, etc. are given, the information is sent to the display interface 246 in a required format.

The FLCD interface 246 multiplexes this information with the image data from the display controller 243 on the same signal line, or after this information remains in its format or is modulated, the FLCD.
To send to 200.

The display controller interface 201 according to each of the above-described modes separates various data, and sends the data related to the display data to the binarization processing unit 204. In addition, the control data is passed to the controller 203 based on the information on the sprite display, and the sprite processing unit 2
Data concerning the sprite display is passed to 05.

The sprite processing unit 205 stores the sprite pattern included in the received data regarding the sprite display in the sprite memory 206.

For example, as shown in FIG. 7, there are a plurality of sprite patterns 420, 421, 422, and even when these sprite patterns are selected and used, all of these sprite patterns or those with high frequency of use are selected. You can select and store multiple files.

FIG. 8 is a conceptual diagram showing an example of the contents stored in the sprite memory 206. In the figure, it is shown that the sprite memory 206 has an area in which a plurality of sprite patterns can be stored.

Further, it is possible to store even when the size of the sprite pattern is plural. For example, when the size of the sprite pattern is 64 × 64 bits, the data is 512 bytes, and when the size is 128 × 128 bits, the data is 2 Kbytes.
6 and 6 have different capacities, but 450 and 451 respectively
Can be stored as

In this case, the number of each sprite pattern,
The controller 203 manages the size and the like.

When the work memory is required for the operation, the controller 203 uses a part of the sprite memory 206 as a control area for purposes other than storing the sprite pattern.

The sprite processing unit 205 reads a desired sprite pattern from the sprite memory 206 at a desired timing under the control of the controller 203 during normal operation, and at a desired timing when performing sprite display, and sends it to the synthesis processing unit 207. .

The synthesis processing unit 207 synthesizes this signal and the data sent from the binarization processing unit 204.

In this case, the logic to be combined is directly from the controller 203 or the sprite processing unit 2
It is given via 05.

Here, the combined data is sent to the display screen 208 as the final display data.

FIG. 9 is a flowchart showing a process relating to sprite information in the signal sent from the display controller 240 to the display section 200.

In the figure, first, when the power is turned on or reset (S100), the sprite pattern is stored in the sprite memory 206 (S101). When there is a sprite display (S102), the following processing is performed. The sprite pattern selection (S103), the sprite pattern read (S104), the composition logic instruction (S105), the sprite pattern display color instruction (S106), the sprite pattern X / Y coordinate instruction (S107), and the sprite pattern display instruction (S108) The signal is separated by the signal separation unit 202, and the control is passed to the controller 203 as a command.

When the command interpreting and executing speed in the controller 203 is much lower than the transfer speed in the display interface 280, the controller 2
In the case of the display interface 280 having a function of returning an ACK signal (or a ready signal) to the display controller 240 each time a command is received,
As shown in FIG.
By having 209, transfer and execution can be performed smoothly.

(Second Embodiment) Next, a second embodiment of the present invention will be described.

FIG. 11 is a block diagram showing details of the FLCD controller 240. In the figure, 302 is a VRAM for accumulating image information, and 303 is a rewriting format generation device, which outputs a partial rewriting address and data to the FLCD 200 to issue an instruction to perform interlace rewriting and partial rewriting. Reference numeral 310 is an information signal line of information output from the rewriting format generation device to the FLCD. Thirty
A position register 5 indicates the position of the hardware cursor on the screen, and a shape RAM 306 stores the shape of the hardware cursor. Reference numeral 304 denotes a partial rewrite detection device that detects writing of data in the VRAM 302, the position register 305, and other registers via the computer bus 119. Reference numeral 307 is another register. Three
08 and 309 are signal lines.

VRA via computer bus 119
M302, position register 305, shape RAM 30
6. When information is written in the other register 307, the partial rewrite detection device 304 detects it and informs the rewrite format generation device 303 via the signal line 308.
Then, the rewrite format generation device 303 causes the FLCD 20 via the signal line 310 according to the rewritten data.
Output data to 0.

FIG. 12 is a flow chart showing the processing when the hardware cursor is moved by the FLCD controller 240. The movement of the cursor in this flowchart is detected by rewriting the position register 305, and the data output process to the FLCD 200 is
It is performed by the rewriting format generation device. That is, whether or not the cursor has moved is determined by whether or not the position register 305 has been rewritten (S200).

When the cursor is moved, the cursor is displayed in interlace based on the information in the position register 305 (S201). Next, it is determined whether or not the movement of the cursor has stopped (S202). When the cursor stops, the entire shape of the cursor is displayed (S203).

FIG. 13 is a diagram showing how the cursor moves on the display screen 501. Reference numeral 510 indicates a cursor before movement, 511 and 512 indicate a cursor during movement, and 513 indicates a cursor after movement.

FIG. 14 shows 510 and 51 of FIG. 13, respectively.
It is a figure showing an example 520, 521, 522, and 523 of dot composition of a cursor corresponding to 1, 512, 513. In this example, interlaced display is performed every other dot.

(Third Embodiment) Next, a third embodiment of the present invention will be described.

In the second embodiment, the interlaced display is displayed when the hardware cursor is moved. However, as a drawing procedure when the hardware cursor is moved, a part of the cursor shape may be transferred at every dot in the cursor movement direction. For example, the same effect as the interlaced display can be obtained.

That is, as shown in FIG. 15, the display shape at the time of movement is determined by matching the shape of the hardware cursor with the movement direction, and the shape is displayed when the hardware cursor is moved. In the figure, 550 is the original cursor shape. When this cursor is moved in the upper right direction or the lower left direction, it is displayed in the shape indicated by 551. When moving in the upper left direction or the lower right direction, the shape shown by 552 is displayed. In addition, the detection of the moving direction is
It can be easily obtained from the values before and after the movement of the position register 305.

The shape of the hardware cursor is not particularly limited, and even if the interlace is every other dot, n
It may be every other dot.

If interlacing is performed every n dots when the cursor is moved, it may be variable between 1 and n depending on the cursor moving speed.

FIG. 16 shows a flowchart of the operation of the third embodiment.

In the figure, whether or not the cursor is moved is determined by whether or not the position register 305 is rewritten (S).
300). Position register 3 if the cursor moves
The moving speed of the cursor is calculated based on the information of 05 (S3
01), the cursor is displayed in interlaced every n dots according to the moving speed (S302). Next, it is determined whether or not the movement of the cursor has stopped (S303). When the cursor is stopped, the entire shape of the cursor is displayed (S304).

As described above, when the hardware cursor is moved, by displaying the cursor in an interlaced manner, the movement drawing performance of the hardware cursor is improved, and a high-speed response when the hardware cursor is moved becomes possible.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.

FIG. 17 shows the FLCD interface 240.
3 is a block diagram showing the details of FIG.

In the figure, reference numeral 601 denotes a VRAM which can be accessed by both the main body side CPU 101 and the partial rewrite control circuit 607. The main body CPU 101 is
Display data is written in the VRAM 601 as a bitmap via the system bus. At this time, the address data is also sent to the partial rewriting line address storage buffer 605 or the priority display partial rewriting line address storage buffer 606. A mouse event detection circuit 602 supplies a mouse event signal to the address storage buffer selector 603 when detecting a mouse drawing operation.
An address storage buffer selector 603 receives a mouse event signal and a mouse cursor priority display signal from the main body side CPU 101, and switches the changeover switch 604 according to these signals. A flowchart of the detailed operation of 603 will be described later. The switch 604 selects either the partial rewriting line address storage buffer 605 or the priority display partial rewriting line address storage buffer 606 as the storage destination of the partial rewriting address data. Reference numeral 605 is a partial rewriting line address storage buffer. Absolute address data when the CPU 101 accesses the VRAM 601 for rewriting the display contents and the like is converted into a display line address and stored in the partial rewriting line address storage buffer 605. The address storage buffer 605 is a double buffer, and two buffers alternately perform input and output for a fixed period. Reference numeral 606 is a partial rewriting line address storage buffer for priority display, which is a partial rewriting line address storage buffer 606.
Has the same function as. The reading of the line address from the priority display partial rewriting line address storage buffer 606, which is performed later, is performed prior to the reading of the line address from the partial rewriting line address storage buffer 605. As a result, the display data on the VRAM 601 corresponding to the line address stored in the preferential display partial rewriting line address storage buffer 606 is preferentially displayed. Reference numeral 607 is a partial rewrite control circuit. The line addresses stored in the partial rewriting line address storage buffer 605 and the priority display partial rewriting line address storage buffer 606 are read,
The display data on the VRAM 601 corresponding to this is read. 607 multiplexes the display data and the address data, and outputs the multiplexed display data to the FLCD as display data with an address. The detailed operation of 607 will be described later. 200 is FLC
D, the display data with an address transferred from the FLCD interface is displayed and output for one line on the line designated by the address.

Next, the address storage buffer selector 603
The operation will be described with reference to the flowchart of FIG.

First, in the determination S401, the current VRAM 60
It is determined whether the access to 1 is due to a mouse event. This determination is made by the mouse event detection circuit 602 and notified to the address storage buffer selector 603. This determination is made by monitoring the address accessed when the mouse event occurs. If it is not a mouse event, the address is stored in the buffer 605. In step S402, it is determined whether or not there is something that moves in synchronization with the mouse. This determination is made by software such as a device driver operating on the main body side CPU 101 and a window manager, and is notified to the address storage buffer selector 603. A method of determining whether or not there is an object that moves in synchronization with the mouse cursor by hardware can be considered. If nothing moves in synchronization with the mouse cursor, the address is stored in the priority display buffer 606. If there is something that moves in synchronization with the mouse cursor, the address is stored in the buffer 605.

Next, the operation of the partial rewrite control circuit 607 will be described with reference to the flowchart of FIG.

In step S501, the line address is read from the priority display rewriting line address storage buffer 606. In step S502, the display data corresponding to the line address is read from the VRAM 601. In step S503, the address and display data are multiplexed and FLCD2
To 00. The processes S501 to S503 are repeated for all the address data in the buffer 606.
In steps S505 to S508, similar processing is performed on the rewrite line address storage buffer 605.
Rewrite line address storage buffer 606 for priority display
Is performed prior to the processing for the rewrite line address storage buffer 605. This gives 6
The data in 06 is displayed preferentially.

With the above processing, when there is no area that moves in synchronization with the mouse cursor, the mouse cursor is displayed with priority, and when there is an area that moves in synchronization with the mouse cursor, priority display of the mouse cursor is performed. You can display that there is no.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. The presence or absence of the mouse cursor priority display is determined according to the size of the area that moves in synchronization with the mouse cursor.

FIG. 21 is a block diagram showing details of the FLCD interface 240 of the fifth embodiment.

In the figure, a VRAM 601 is accessible from both the main body side CPU 101 and the partial rewrite control circuit 607. The main body side CPU 101 writes display data as a bitmap in the VRAM 601 via the system bus. At this time, the address data is
Partial rewriting line address storage buffer 605 or priority display partial rewriting line address storage buffer 6
It is also sent to 06. Reference numeral 602 denotes a mouse event detection circuit, which detects the mouse drawing operation and changes the switch 6
04 is switched to the 606 side. The switch 604 selects either the partial rewriting line address storage buffer 605 or the priority display partial rewriting line address storage buffer 606 as the storage destination of the address data for partial rewriting. Reference numeral 605 is a partial rewriting line address storage buffer. Absolute address data when the CPU 101 accesses the VRAM 601 for rewriting the display contents and the like is converted into a display line address and stored in the partial rewriting line address storage buffer 605. The address storage buffer 605 is a double buffer, and two buffers alternately perform input and output for a fixed period. 606
Is a partial rewriting line address storage buffer for priority display, and a partial rewriting line address storage buffer 60
It has the same function as 5. Reference numeral 607 is a partial rewrite control circuit. The line addresses stored in the partial rewriting line address storage buffer 605 and the priority display partial rewriting line address storage buffer 606 are read out, and the display data on the VRAM 601 corresponding thereto are read out. 607 multiplexes display data and address data, and displays the FLCD 2 as display data with address.
Output to 00. The detailed operation of 607 will be described later. 20
0 is the FLCD, and the FLCD interface 240
The display data with an address transferred from is displayed and output for one line on the line designated by the address.

The operation of the partial rewrite control circuit 607 will be described with reference to the flowchart of FIG.

In step S601, the number of lines stored in the partial rewriting line address storage buffer 605 is read. In step S602, it is determined whether the number of lines exceeds a certain value. This value is the system performance, FLCD2
An appropriate value is determined based on the display speed of 00, etc. If the number exceeds the predetermined value, processing S603 is performed in order to cancel the priority display of the mouse cursor. If the number does not exceed the certain value, processing S604 and processing S605 are performed in order to perform preferential display of the mouse cursor. In step S603, the line address in the priority display rewriting line address storage buffer 606 and the data corresponding to the line address in the rewriting line address storage buffer 605 are alternately displayed. In step S604, the data corresponding to the line address in the priority display rewriting line address storage buffer 606 is displayed. In step S605, the data corresponding to the line address in the rewrite line address storage buffer 605 is displayed.

By the above processing, when the size of the area that moves in synchronization with the mouse cursor is less than a certain value, the mouse cursor is displayed with priority, and the size of the area that moves in synchronization with the mouse cursor exceeds a certain value. In the case of, it is possible to display that the priority display of the mouse cursor is not performed.

[0102]

As described above, according to the present invention, when displaying the display data, the display can be performed without any discomfort by focusing on the cursor.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing system including a display control device according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of the FLCD controller according to the first embodiment of the present invention.

FIG. 3 is a detailed block diagram of the FLCD according to the first embodiment of the present invention.

FIG. 4 is a conceptual diagram showing a control structure of the display device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing conversion of color representation using the table according to the first embodiment of the present invention.

FIG. 6 is a diagram showing conversion of color representation by performing the binarization processing process according to the first embodiment of the present invention.

FIG. 7 is a diagram showing an example of a sprite pattern.

FIG. 8 is a conceptual diagram showing a storage state of a sprite memory.

FIG. 9 is a flowchart showing the processing of the first embodiment of the present invention.

FIG. 10 is a block diagram when a FIFO is used in the FLCD of the first embodiment of the present invention.

FIG. 11 is a detailed block diagram of an FLCD controller according to a second embodiment of the present invention.

FIG. 12 is a flowchart showing the processing of the second embodiment of the present invention.

FIG. 13 is a diagram showing cursor movement on a display screen.

FIG. 14 is a diagram showing a configuration example of cursor dots.

FIG. 15 is a diagram showing a configuration example of cursor dots according to a third embodiment of the present invention.

FIG. 16 is a flowchart showing the processing of the third embodiment of the present invention.

FIG. 17 is a detailed block diagram of an FLCD interface according to a fourth embodiment of the present invention.

FIG. 18 is a flowchart showing the processing of the address storage buffer selector according to the fourth embodiment of the present invention.

FIG. 19 is a flowchart showing the processing of the partial rewriting circuit according to the fourth embodiment of the present invention.

FIG. 20 is a diagram showing an example of a region that moves in synchronization with a mouse.

FIG. 21 is a detailed block diagram of an FLCD interface according to a fifth embodiment of the present invention.

FIG. 22 is a flowchart showing the processing of the partial rewrite control circuit according to the fifth embodiment of the present invention.

[Explanation of symbols]

 101 CPU 102 Arithmetic Processor 103 ROM 104 Main Memory 105 DMAC 106 Interrupt Controller 107 Real Time Clock 108 Lithium Battery 109 Keyboard 110 Keyboard Controller 111 Hard Disk Device 112 HDD Controller 113 Floppy Disk Device 114 FDD Controller 115 Mouse 116 Mouse Controller 117 RS232C Interface 118 Printer Interface 119 system bus 200 FLCD 201 FLCD controller interface 202 signal separation unit 203 controller 204 binarization processing unit 205 sprite processing unit 206 sprite memory 207 synthesis processing unit 208 display screen 240 FLCD 241 bus interface 242 Display processor 243 the display controller 244 video memory 245 sprite interface 246 FLCD interface 302 VRAM 303 rewrite format generator 304 partial rewrite detector 305 location register 306 shape RAM 307 other registers

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiichi Matsuzaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tatsuya Sakashita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Masami Shimakura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Kenichiro Ono 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (6)

[Claims] 1. Storage means for storing display data; processing means for binarizing the display data; storage means for storing the position of a cursor; and display data for the binarization processing and the storage means. A display control device comprising: a synthesizing unit that synthesizes a cursor with display data based on a stored position, and a display control unit that displays the display data on the display unit. 2. A display control device of a display device capable of updating a display state of a display element according to a change in display, a storage means for storing display data, a first cursor shape and a second cursor shape. Shape storing means for storing the cursor, storage means for storing display position information of the cursor, detecting means for detecting movement of the cursor, and when the cursor is moving by the detecting means, the cursor is moved in the first cursor shape. And a control means for displaying the cursor and displaying the cursor in a second cursor shape when the cursor is not moving. 3. A display control device of a display device capable of updating a display state of a display element according to a change of display data, a storage means for storing display data, a movement of a cursor, and a movement in synchronization with the cursor. A display control device comprising: means for detecting the presence or absence of an area to be moved; and display control means for performing priority display of the cursor when there is no area to move in synchronization with the cursor. 4. The display data is stored, the display data is binarized, the cursor based on the cursor position information and the binarized display data are combined, and the combined display data is displayed. Characteristic display control method. 5. A display control method for a display device capable of updating the display state of a display element associated with display change, wherein movement of the cursor is detected, and when the cursor is moving, the first means is displayed on the display means. A display control method comprising displaying in a cursor shape, and displaying in a second cursor shape on the display means when the cursor is not moving. 6. A display control method for a display device capable of updating a display state of a display element according to a change in display data, wherein the cursor movement and the presence or absence of an area moving in synchronization with the cursor are detected, A display control method characterized in that when there is no area that moves in synchronization with, the cursor display is prioritized over the display of the display data.