JP2768327B2 - Graphics display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphics command for displaying graphic elements on a display device by a CPU, and a graphics controller for displaying graphics elements on the display device based on the graphics commands generated by the CPU. The present invention relates to a graphics display device for displaying the image.

[0002]

2. Description of the Related Art When a graphic element such as a window is displayed on a display device, a graphics command for displaying the graphic element on the display device is used in order to reduce the load on the CPU and improve the drawing speed.
It is conventional for a graphics controller to display graphic elements on a display device based on graphics commands created by U and created by the CPU.

As such a technique, for example, “Nikkei Electronics, July 14, 1986, No. 399
No., published by Nikkei McGraw-Hill, P124 to P128 ". FIG. 18 is a block diagram for explaining the above-described conventional technique. The display device 108 has two windows 1 in addition to the background screen.
When displaying images 09 and 110, the CPU 100 changes the display screen of the display device 108 to five strips ST1.
To ST5, and further strips ST1 to ST5
Make a tile by dividing the inside horizontally. For example, the strip ST3 is divided into four tiles T1 to T4.

[0004] The CPU 100 includes a bitmap information 104 corresponding to the background screen and windows 109 and 11.
The bitmap information 105 and 106 corresponding to 0 are stored in the bitmap memory 103, and the window descriptor 102 is stored in the memory 101. The window descriptor 102 is a graphics command including a width of each tile, an address of a bitmap memory 103 in which bitmap information to be displayed on each tile is stored, and the like, and is created by the CPU 100 and stored in the memory 101. Things.

[0005] The graphics controller 107 displays two windows 109 and 110 on the display device 108 in addition to the background screen by switching the display address in accordance with the display timing while referring to the window descriptor 102. For example, strip S in which windows 109 and 110 overlap.
When displaying the first scan line of T3, the display address is changed to the address A1, A2, A3, A4 in the bitmap memory 103 each time the display timing of the first scan line of the tiles T1, T2, T3, T4 comes. Switch to

[0006]

As described above, conventionally, it is necessary to divide a display screen of a display device into strips and tiles. In order to perform this processing, a portion where graphic elements overlap is calculated. In such a case, there is a problem that the load on the CPU increases. In addition, when the display screen of the display device is divided into tiles that do not overlap with each other in consideration of how the graphic elements to be displayed on the display device overlap, when the graphic elements are displayed, the width of each tile and the display of each tile should be performed. Since the display address is switched to the start address corresponding to the tile at each display timing of each tile while referring to the window descriptor including the address of the bitmap information, etc. There is a problem that synthesis processing such as alpha blending cannot be performed.

An object of the present invention is to provide a graphics display device capable of reducing the load on a CPU and performing a synthesizing process between graphic elements.

[0008]

SUMMARY OF THE INVENTION In order to achieve the object of reducing the load on the CPU, the present invention provides a graphics display device for displaying graphic elements on a display device, comprising a graphics command memory and a scan line. The span descriptors for each graphic element including the position of the span of the graphic element to be displayed on the scan line and the storage address of the corresponding bitmap information are arranged in order from the one with the largest depth of the graphic element displayed on the scan line. A CPU configured to create a line descriptor arranged for each scan line of the display device and storing the created line descriptor in the graphics command memory; and the display device based on the line descriptor stored in the graphics command memory. Shape It is obtained by a graphics controller for displaying the element.

Further, in order to achieve the object of the present invention to enable a synthesizing process between graphic elements such as alpha blending, the span descriptor includes an alpha value at the time of performing alpha blending, and the bitmap information storing means. Is a bit map for one scan line stored in the line buffer of the first and second line buffers which is written by the line buffer controller in accordance with the alpha value included in the span descriptor. 1 indicated by the information and the storage address contained in the span descriptor
It has an alpha blending unit that performs alpha blending with bitmap information for scan lines.

The CPU displays a span descriptor for each graphic element including the position of the span of the graphic element displayed on the scan line on the scan line and the storage address of the corresponding bitmap information on the scan line. A line descriptor arranged in order from the element having the largest depth is created for each scan line of the display device, the created line descriptor is stored in the graphics command memory, and the graphics controller is stored in the graphics command memory. The graphic element is displayed on the display device based on the line descriptor.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a CPU 1 having a function of creating a graphics command defining a display screen of a display device 5 and the like,
A system memory 2 used by the CPU 1, a graphics command memory 3 for storing graphics commands created by the CPU 1, bitmap information of graphic elements to be displayed on the display device 5, and the like, and a graphics command memory 3 for storing graphics commands A graphics controller 4 for displaying graphic elements on a display device 5 according to graphics commands and bitmap information
And a PU bus 6.

FIG. 2 is a diagram showing an example of the configuration of a graphics command created by the CPU 1. The number of line descriptors 21-
1 to 21-n and a screen descriptor 22.

Line descriptors 21-1 to 21-n
Respectively correspond to the first to n-th scan lines SL1 to SLn of the display device 5, and indicate the position of the graphic element arranged on the corresponding scan line on the scan line of each span. It has a configuration in which span descriptors for each of the graphic elements shown are arranged in descending order of the graphic elements displayed on the scan line. All span descriptors in one line descriptor are stored at consecutive addresses in the graphics command memory 3.

The span of the graphic element is determined by the display device 5
Are divided into scan line units of the display device 5. Therefore, as shown in FIG. 3, a background screen (the background screen is also a kind of graphic element) a
When the graphic element b is displayed on the graphic element b and the graphic element c is further superimposed on the graphic element b, the line descriptor 21 corresponding to the i-th (1 ≦ i ≦ n) scan line SLi of the display device 5 is displayed. -I is a span descriptor indicating a position on the scan line SLi of each of the spans Sa, Sb, Sc corresponding to the background screen a, the graphic elements b, c, and SDa, SDb, SDc.
They are arranged in order of depth, such as SDa, SDb, and SDc.

Line descriptors 21-1 to 21-n
The span descriptor 23 serving as a component includes a source address 24, an arrangement position 25, a span width 25, and an extension instruction 27.

The source address 24 indicates an address or the like in the graphics command memory 3 where bit map information of a span targeted by the span descriptor 23 is stored.

The disposition position 25 is the span descriptor 2
Reference numeral 3 denotes an arrangement start position on the scan line of the target span. For example, in the arrangement position 25 of the span descriptor corresponding to the span Sb shown in FIG.
“Xb” is set.

The span width 26 corresponds to the span descriptor 2
3 indicates the width of the target span. For example, “Lb” is set in the span width 26 of the span descriptor corresponding to the span Sb shown in FIG.

The extension instruction 27 determines whether the span is to be painted with the color designated by the CPU 1 as shown in FIG.
Alternatively, a color designation flag 27a indicating whether the display of the span is in accordance with the bitmap information designated by the source address 24, an alpha value 27b at the time of performing the alpha blending, and whether or not to perform the transparent color processing. And a filter flag 27d indicating whether or not a filter provided in the graphics controller 4 performs the filtering process. still,
To fill the span with the color specified by CPU1,
The color designation flag 27a is turned on, and the fill color is set in the entry of the source address 24 in the span descriptor 23.

The screen descriptor 22 has entries # 1 to #n corresponding to each of the scan lines SL1 to SLn of the display device 5. Each entry # 1 to #n has a line descriptor 2
1-1 to 21-n addresses and line descriptors 21-1 to 2 in graphics command memory 3
The number of span descriptors constituting 1-n is set.

FIG. 5 is a block diagram showing an example of the configuration of the graphics controller 4.
Controller 42 and screen descriptor FIF
O43, a DMA controller 44, a line descriptor FIFO 45, a decoder 46, a DMA controller 47, a pixel FIFO 48, a transparent color processing unit 49, an alpha blending unit 50, a selector 51,
It comprises line buffers 52 and 53 for storing bit map information for one scan line, a selector 54, a line buffer controller 55, a filter 56, and a memory controller 57.

In the register 41, a storage start address of the screen descriptor, a filter coefficient, a color to be subjected to transparent color processing, and the like are set by the CPU 1.

The DMA controller 42 reads the screen descriptor from the graphics command memory 3 in accordance with the storage start address of the screen descriptor set in the register 41 every time the frame is switched, and stores the read screen descriptor in the screen descriptor FIFO 43. Has functions.

The DMA controller 44 has a function of reading a screen descriptor from the screen descriptor FIFO 43, reading a line descriptor from the graphics command memory 3 in accordance with the contents of each entry of the read screen descriptor, and storing the read line descriptor in the line descriptor FIFO 45. Yes, it operates as a line descriptor reading means.

The decoder 46 has a function of reading out line descriptors one line at a time from the line descriptor FIFO 45 in synchronization with the display period of one scan line, and also includes a span descriptor constituting a line descriptor read out for one scan line. It has a function of decoding in order from the one with the largest depth and controlling the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 56 according to the decoding result.

The DMA controller 47 includes a decoder 46
When it is instructed to read the bitmap information by the decoder 46, the bitmap information instructed by the decoder 46 is read from the graphics command memory 3, and
The bitmap information for one scan line including this in the portion designated by the decoder 46 is stored in the pixel FIFO.
48. If the decoder 46 instructs to fill the span with the color designated by the CPU 1, bitmap information for one scan line corresponding to the span painted with the color designated by the CPU 1 is stored in the pixel FIFO 48. .

When it is not instructed by the decoder 46 to perform the transparent color processing, the transparent color processing section 49 reads the bitmap information from the pixel FIFO 48 one scan line at a time, and successively reads the bitmap information from the pixel FIFO 48.
Pass to. If it is instructed to perform the transparent color processing, the bitmap information is read out from the pixel FIFO 48 for one scan line at a time, and is sequentially passed to the alpha blending unit 50. The CPU 1 compares the color of each pixel on the span indicated by <1> with the color to be subjected to the transparent color processing set in the register 41 by the CPU 1, and sets the color indicated by the bitmap information in the transparent color processing set in the register 41. Is instructed to the alpha blending unit 50 to make the alpha value of a pixel corresponding to the target color of the color corresponding to the transparent color.

The line buffer controller 55 synchronizes the display period of one scan line with the line buffer 5.
The selector 51 and the selector 54 are controlled so that the selectors 2 and 53 are alternately selected. However, during the period when the selector 51 selects the line buffer 52, the selector 54 selects the line buffer 53, and during the period when the selector 51 selects the line buffer 53, the selector 54 selects the line buffer 52. To select. Selector 51
The line buffer selected by the selector 54 is for writing, and the line buffer selected by the selector 54 is for display.

The line buffers 52 and 53 store bit map information for one scan line.

The alpha blending unit 50 reads bitmap information for one scan line from the line buffer 52 or the line buffer for writing selected by the selector 51 of the line buffer 53, and transfers the bitmap information from the transparent color processing unit 49. The color of each pixel on the span indicated by the bit map information for one scan line and the span of the color of each pixel indicated by the bit map information for one scan line read from the line buffer for writing Is alpha blended with the color of the pixel corresponding to the alpha value according to the alpha value specified by the decoder 46. Then, the bitmap information for one scan line after the alpha blending is stored again in the write line buffer among the line buffers 52 and 53. For a pixel for which the alpha value is instructed by the transparent color processing unit 49 to be equivalent to a transparent color, the alpha value specified by the transparent color processing unit 49 is used instead of the alpha value specified by the decoder 46. Alpha blending is performed using the value (alpha value 0% corresponding to a transparent color). The alpha blending unit 50, the decoder 46, the DMA controller 47, the pixel FIFO 4
8. The bitmap information storage means is constituted by the transparent color processing section 49.

The filter 56 includes line buffers 52 and 5
3 has a function of reading bitmap information for one scan line from a display line buffer, and transferring the read bitmap information to the display device 5, and operates as an output unit. Note that the decoder 4
In the case where an instruction to perform the filter processing is given by the command number 6, the filter coefficient set by the CPU 1 is read from the register 41, and the filter processing is performed in accordance with the read coefficient.

The memory controller 57 includes CPUs 1 and 2
The access to the graphics command memory 3 of the MA controllers 42, 44, and 47 is arbitrated, and DM is performed.
When data is read from the graphics command memory 3 in accordance with an access request from the A controllers 42, 44, and 47, the data is transferred to the DMA controller that issued the request.

Next, the operation of this embodiment will be described.

Now, if the user of the graphics display device is C
The PU 1 is instructed to activate the graphics display device, and then, as shown in FIG. 6, instructed to display the graphic element 62 on the background screen 61 of the display device 5. It is assumed that the user instructs to superimpose and display the graphic elements 63.

When the CPU 1 is instructed to activate the graphics display device, as shown in the flowcharts of FIGS.
The value of a variable k indicating the number of the scan line to be processed is set to "1", and the value of a variable CNT indicating the number of span descriptors in one scan line is set to "0" (S1). , S2).

Thereafter, the CPU 1 focuses on the graphic element having the largest depth among graphic elements to be displayed on the first scan line SL1 (S3). In this example, since only the background screen 61 is displayed on the first scan line SL1, the CPU 1 pays attention to the background screen 61.

Next, the CPU 1 obtains the X coordinate value of the intersection of the background screen 61 of interest and the first scan line SL1 (S5). In this example, the intersection X
X1 and X6 are obtained as coordinate values. X1, X6
Are X coordinate values at the left end and right end of the screen, respectively.

Thereafter, the CPU 1 calculates the arrangement position and the span width of the span on the scan line SL1 on the background screen 61, and sets them in the entry of the arrangement position and the span width of the span descriptor (S6). In this case,
The arrangement position and span width are respectively X1, X6-X1 + 1
As shown in FIG. 9, the span descriptor 90
Is set in the entry of the arrangement position 92 and the span width 93.

Next, since the graphic element of interest is the background screen 61 and the user has not specified the color, the CPU 1 determines that the first scan line S
The address of the bitmap information of the background screen 61 to be displayed on L1 in the graphics command memory 3 is set in the entry of the source address 91 of the span descriptor 90, and the entry of the color designation flag 94a is set to OFF. (FIG. 8, S7-S9). Here, the bitmap information of the background screen 61 displayed in the odd frame is stored in the address “A1” on the graphics command memory 3 by the CPU 1, and the background screen 61 displayed in the even frame is displayed. Is stored at the address “A2” on the graphics command memory 3. For example, if it is a frame period in which the bitmap information of the background screen 61 to be displayed in the odd frame is stored in the graphics command memory 3, the CPU 1 determines the source address of the span descriptor 90 as shown in FIG. The address "A1" is set in the entry 91.

Thereafter, the CPU 1 determines that the graphic element of interest is the background screen 61 and the user has not specified the alpha value, the transparent color process, and the filter process. The entries of the alpha value 94b, the transparent color flag 94c, and the filter flag 94d of the descriptor 90 are set to 100%, off, and off, respectively (S12, S14, S15, S17, S1).
8, S20).

As described above, as shown in FIG.
When the span descriptor 90 for the span is created (S
21), the CPU 1 increments CNT by 1 (S22), and returns to the processing of S3 in FIG.

In the case of this example, since the graphic element displayed on the first scan line SL1 is only the background screen 61, the judgment result in S4 becomes YES, and the processing in S23 is performed.

In step S23, the line descriptor for one scan line is stored in the graphics command memory 3 by storing the created span descriptor for one scan line in consecutive addresses in the graphics command memory 3 in the order of generation. In this example,
Since only the span descriptor 90 shown in FIG. 9 is created as the span descriptor of the first scan line SL1, one span descriptor 9 is formed.
A line descriptor for one scan line composed of 0 is stored in the graphics command memory 3. Now, for example, it is assumed that the line descriptor 33-1 for one scan line composed of only the span descriptor 90 is stored at the address B1 on the graphics command memory 3, as shown in FIG.

Thereafter, as shown in FIG. 10, the CPU 1 sets the first one of the two screen descriptors 31 (for example, the screen descriptor 31) among the two screen descriptors 31 and 32 prepared on the graphics command memory 3. In the entry # 1, the address “B1” of the line descriptor 33-1 and the number of span descriptors “1” constituting the line descriptor 33-1 are set (S).
24). Here, the screen descriptors 31, 32
The reason for providing two is to enable smooth display by writing information for displaying the next frame in the other screen descriptor while using one screen descriptor for display. is there.

Next, the CPU 1 increments the value of the variable k by one (S25), and performs the same processing as described above for the second scan line SL2. Thereby, as shown in FIG. 10, the line descriptor 33-2 for the second scan line SL2 is stored at the address B2 of the graphics command memory 3, and the second entry # of the screen descriptor 31 is stored. 2
, The address “B2” of the line descriptor 33-2
And the number "1" of span descriptors constituting the line descriptor 33-2 are set.

Hereinafter, the CPU 1 executes the third, fourth,
.., N-th scan line SL3, SL4,.
The same processing as described above is performed on Ln. Thereby, as shown in FIG. 10, the line descriptors 33-3,..., 33-n for the third to n-th scan lines SL3,.
, And n-th entries # 3,..., #N of the screen descriptor 31 are set with information on the line descriptors 33-3,.

Then, all the scan lines SL1 to SL
When the same processing as described above is performed on Ln, the CPU 1
Stores bitmap information necessary for displaying a screen defined by the line descriptors 33-1 to 33-n stored in the graphics command memory 3 in the graphics command memory 3 this time (S2).
7). In the case of this example, the line descriptor 33-1
The only bitmap information required to display the screen defined by .about.33-n is the bitmap information of the background screen 61, and the bitmap information is, as described above, the background to be displayed in the odd frame. Since this is for the screen 61, the CPU 1 stores the bitmap information 35-1 of the background screen 61 at the address "A1" as shown in FIG.

Thereafter, when the display of one frame is completed, the CPU 1 stores the screen descriptor 3 in the register 41 in the graphics controller 4 shown in FIG.
The address “C” of 1 is set.

Further, when the display of the next frame is started, the CPU 1 performs the processing shown in the flowcharts of FIGS. 7 and 8 again. However, in this case, since the screen descriptor 31 used last time is used for display, the same processing as described above is performed using the other screen descriptor 32. As a result, as shown in FIG. 10, the line descriptors 34-
1 to 34-n are stored in the addresses D1 to Dn of the graphics command memory 3, and the addresses "D1 to Dn" of the line descriptors 34-1 to 34-n and the line descriptors 34-1 to 34-n are formed. The number “1” of span descriptors to be set is set in each entry # 1 to #n of the screen descriptor 32.

Thereafter, when the display of one frame ends, the CPU 1 sets the address “E” of the screen descriptor 32 in the register 41 in the graphics controller 4 instead of the address “C” of the screen descriptor 31. As described above, the CPU 1 sets the addresses “C”,
“E” is set alternately in the register 41 every time the display of the frame is completed. If the display content of the next frame is the same as the display content of the previous frame, the CPU 1 executes the processing shown in FIGS.
And the rewriting of the register 41 are not performed.

The CPU 1 repeats the above processing until the user instructs the display of the graphic element 62.

While the CPU 1 is performing the above-described processing, the graphics controller 4 performs the following processing.

The DMA controller 42 refers to the register 41 every time the frame is switched, reads the contents of the screen descriptor indicated by the address from the graphics command memory 3 in accordance with the address of the screen descriptor set therein, and It is stored in the descriptor FIFO 43. Now, for example, assuming that the address “C” of the screen descriptor 31 shown in FIG. 10 is set in the register 41, the DMA controller 42 determines the contents of the entries # 1 to #n of the screen descriptor 31 according to the address “C”. Are read one entry at a time, and the read contents are sequentially read into the screen descriptor FIFO 43.
To be stored.

The DMA controller 44 reads the contents of the screen descriptor 31 stored in the screen descriptor FIFO 43 one entry at a time,
Each scan line SL1 to SL according to the read contents
n corresponding to the line descriptors 33-1 to 33-n
Is read from the graphics command memory 3 and stored in the line descriptor FIFO 45.

For example, a screen descriptor FIF
When the contents of the first entry # 1 of the screen descriptor 31 are read from O43, the line descriptor 33-1 corresponding to the scan line SL1 is stored in the address B1 of the graphics command memory 3 according to the contents, and the line descriptor is read. Since it is found that the number of span descriptors constituting 33-1 is “1”, the DMA controller 44 converts the line descriptor 31-1 constituted by one span descriptor from the address B1 of the graphics command memory 3 to The read-out line descriptor 31-1 is stored in the line descriptor FIFO 45.

The decoder 46 reads line descriptors from the line descriptor FIFO 45 one scan line at a time in synchronization with the display period of one scan line. Then, each of the span descriptors constituting the read line descriptor for one scan line is sequentially analyzed, and the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 5 are analyzed in accordance with the analysis result.
6 is controlled.

If the line descriptor 33-1 composed of only the span descriptor 90 shown in FIG. 9 is read, the decoder 46 performs the following processing.

For the DMA controller 47, since the color designation flag 94a is off, based on the information set in the source address 91 and the span width 93, the address from the address A1 of the graphics command memory 3 is While instructing to read bitmap information for the number of pixels corresponding to the width (X6−X1 + 1),
Based on the information set at the arrangement position 92, the bitmap information read from the graphics command memory 3 is included in the bitmap information corresponding to the arrangement position X1 in one scan line. Is stored in the pixel FIFO 48.

Since the transparent color flag 94c is off, the transparent color processing section 49 is instructed not to perform the transparent color processing.

Since the alpha value 94b is 100%, the alpha blending unit 50 is instructed to set the alpha value at the time of alpha blending to 100%. Also, the arrangement position 92 and the span width 93 are X
1, X6−X1 + 1, the span width (X6−X1) is obtained from the bitmap information of the pixel corresponding to the arrangement position X1 in the bitmap information for one scan line.
+1) indicates that alpha blending is to be performed only for bitmap information corresponding to the number of pixels corresponding to the number of pixels.

For the filter 56, the filter flag 9
Since 4d is off, it indicates that no filtering is to be performed.

Upon receiving the above instruction from the decoder 46, the DMA controller 47, the transparent color processing section 49, the alpha blending section 50, and the filter 56 perform the following processing.

The DMA controller 47 starts from the address A1 of the graphics command memory 3 and sets the span width (X6
−X1 + 1) The bitmap information of the number of pixels corresponding to (X1 + 1) is read, and the read bitmap information is incorporated from the portion corresponding to the arrangement position X1 in the bitmap information of one scan line. Is stored in the pixel FIFO 48.

Since the transparent color processing section 49 is instructed by the decoder 46 not to perform the transparent color processing, the bit map information for one scan line is read from the pixel FIFO 48, and the read bit map information for one scan line is read. The information is passed to the alpha blending unit 50.

The alpha blending unit 50 includes a selector 51
The bitmap information for one scan line is read from the line buffer for writing (referred to as the line buffer 52) selected by (1), and the read bitmap information for one scan line and the one passed from the transparent color processing unit 49 are read. A portion designated by the decoder 46 with the bitmap information for the scan line (the bit width information of the pixel corresponding to the arrangement position X1 is used to determine the span width X6-
Bitmap information for the number of pixels corresponding to X1 + 1)
To the 100% alpha value specified by the decoder 46
And the bitmap information for one scan line after the alpha blending is stored in the line buffer 52 again.

Since the filter 56 is instructed not to perform the filtering process, the filter 56 reads the bitmap information from the line buffer 53 selected by the selector 54 and synchronizes with the dot clock of the display device 5. To transfer the bitmap information.

Next, the operation when the user instructs the CPU 1 to display the graphic element 62 on the background screen 61 shown in FIG. 6 will be described. At this time, it is assumed that the user instructs to paint the graphic element 62 in a predetermined color (for example, red).

After the above-mentioned instruction is issued, when it is time to start displaying the next frame, the CPU 1 performs the processing shown in the flowcharts of FIGS.

In this process, the CPU 1 advances the scan line to be processed one by one in the same manner as described above. When a scan line having only the background screen 61 is to be processed, the same processing as described above is performed. However, when a scan line having the graphic element 62 in addition to the background screen 61 is to be processed, The following processing is performed.

For example, in addition to the background screen 61, the graphic element 6
When the j-th scan line in which the number 2 is present is set as a processing target, the following processing is performed.

The CPU 1 sets the j-th scan line S
Attention is paid to a graphic element having the largest depth among graphic elements to be displayed on Lj (S3). In this example, since the graphic element having the largest depth is the background screen 61,
1 focuses on the background screen 61.

Thereafter, the CPU 1 performs the same processing as described above to create a span descriptor corresponding to the scan line SLj on the background screen 61 (S5 to S2).
1). Now, for example, the scan line SL of the background screen 61
It is assumed that a span descriptor 120 shown in FIG. 11 is created as a span descriptor corresponding to j.

Next, the CPU 1 increments CNT by 1 to set it to "1" (S22), and thereafter, scan line SLj
Attention is paid to the graphic element having the next largest depth among the graphic elements to be displayed at the top. In this example, attention is paid to the graphic element 62.

Next, the CPU 1 determines the X at the intersection of the graphic element 62 of interest and the j-th scan line SLj.
A coordinate value is obtained (S5). In the case of this example, X2 and X4 are obtained as the X coordinate values of the intersection.

Thereafter, the CPU 1 obtains the arrangement position and the span width of the span on the scan line SLj of the graphic element 62, and sets them in the entry of the arrangement position and the span width of the span descriptor (S6). In this case,
The arrangement position and span width are X2, X4-X2 + 1, respectively.
As shown in FIG. 11, the span descriptor 1
30 are set in the entry of the arrangement position 132 and the span width 133.

Next, since the graphic element 62 currently focused on is the graphic element instructed to be painted in red by the user, the CPU 1 sets the graphic element 62 as shown in FIG.
The entry of the source address 131 of the span descriptor 130 is set to red, and the color designation flag 134a is turned on (S7, S10, S11).

Thereafter, the CPU 1 determines that the graphic element 62 of interest at present has an alpha value, transparent color processing,
Since it is a graphic element for which no filtering is specified,
As shown in FIG. 11, the entries of the alpha value 134b, the transparent color flag 134c, and the filter flag 134d of the span descriptor 130 are 100%, off,
Set OFF (S12, S14, S15, S17, S
18, S20).

As described above, as shown in FIG.
Span descriptors 120 for one scan line,
When 130 is created (S21), CPU 1 sets CNT to +
1 is set to "2" (S22), and the process returns to S3 in FIG.

In the case of this example, the graphic elements displayed on the j-th scan line SLj are the background screen 61 and the graphic element 62, and both have already been processed.
The determination result of S4 is YES, and the process of S23 is performed.

In S23, as shown in FIG. 12, the span descriptors 120,
The line descriptors 140-j for one scan line corresponding to the scan line SLj are stored in the graphics command memory 3 by storing 130 in successive addresses of the graphics command memory 3 in the order of creation. Now, for example, as shown in FIG. 12, it is assumed that a line descriptor 140-j for one scan line composed of span descriptors 120 and 130 is stored from the address Bj of the graphics command memory 3.

Thereafter, as shown in FIG. 12, the CPU 1 sets the j-th one of the two screen descriptors 31 (for example, the screen descriptor 31) among the two screen descriptors 31 and 32 prepared on the graphics command memory 3. In the entry #j, the address “Bj” of the line descriptor 33-j and the number of span descriptors “2” constituting the line descriptor 33-j are set (S).
24).

Thereafter, the CPU 1 increments k by +1 and sets the next scan line SL (j + 1) as a processing target (S25).
The same processing as described above is performed.

The CPU 1 repeats the above process until the user instructs the display of the graphic element 63.

While the CPU 1 is performing the above-described processing, the graphics controller 4 performs the following processing.

The DMA controller 42 refers to the register 41 every time the frame is switched, reads the contents of the screen descriptor indicated by the address from the graphics command memory 3 according to the address of the screen descriptor set therein, and It is stored in the descriptor FIFO 43. Now, for example, assuming that the address “C” of the screen descriptor 31 shown in FIG. 12 is set in the register 41, the DMA controller 42 reads the contents of the screen descriptor 31 according to the address “C”, and stores the read contents. The data is sequentially stored in the screen descriptor FIFO 43.

The DMA controller 44 reads the contents of the screen descriptor 31 stored in the screen descriptor FIFO 43 one entry at a time,
Each scan line SL1 to SL according to the read contents
n is read from the graphics command memory 3 and the line descriptor F
It is stored in the IFO 45.

For example, a screen descriptor FIF
O43 to the screen descriptor 31 shown in FIG.
Read the contents of the j-th entry #j of
Since the line descriptor 140-j corresponding to the scan line SLj is stored in the address Bj of the graphics command memory 3 according to the content and the number of span descriptors constituting the line descriptor 140-j is "2", the DMA is determined. Controller 4
4 is an address Bj of the graphics command memory 3
, The line descriptor 140-j constituted by the two span descriptors 120 and 130 is read, and the read line descriptor 140-j is stored in the line descriptor FIFO 45.

The decoder 46 reads line descriptors from the line descriptor FIFO 45 one scan line at a time in synchronization with the display period of one scan line. Then, each of the span descriptors constituting the read line descriptor for one scan line is sequentially analyzed, and the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 5 are analyzed in accordance with the analysis result.
6 is controlled.

Now, for example, the line descriptor FIF
As a line descriptor for one scan line from O45, a line descriptor 140-j shown in FIG.
Is read, the decoder 46 performs the following processing.

The decoder 46 has the line descriptor 1
Of the two span descriptors constituting 40-j,
First, the span descriptor 120 corresponding to the span having a large depth is read, and then the span descriptor 130 is read.

When the span descriptor 120 is read, since the contents of the span descriptor 120 are as shown in FIG. 11, the decoder 46 sends the same instruction as described above to the DMA controller 47, the transparent color processing blend 49, and the alpha blending. This is performed for the unit 50 and the filter 56. The DMA controller 47, the transparent color processing blend 49, the alpha blending unit 50, and the filter 56 that have received this instruction perform the same processing as described above.

Thereafter, when the span descriptor 130 is read, since the contents are as shown in FIG. 11, the decoder 46 performs the following processing.

Since the color designation flag 134a is turned on for the DMA controller 47, the DMA controller 47 corresponds to the arrangement position X2 based on the information set in the source address 131, the arrangement position 132, and the span width 133. Instruct the pixel FIFO 48 to store bitmap information for one scan line that makes the display color of a pixel corresponding to the span width (X4−X2 + 1) from the pixel “red”.

Since the transparent color flag 134c is off, the transparent color processing section 49 is instructed not to perform the transparent color processing.

Since the alpha value 134b is 100%, the alpha blending unit 50 is instructed to set the alpha value at the time of alpha blending to 100%. In addition, since the arrangement position 132 and the span width 133 are X2 and X4−X2 + 1, respectively, the bit width information of the pixel corresponding to the arrangement position X2 in the bit map information for one scan line indicates the span width (X4
-X2 + 1) indicates that alpha blending is to be performed only on bitmap information corresponding to the number of pixels corresponding to (X2 + 1).

Filter flag 1 for filter 56
Since 34d is off, an instruction is given not to perform the filtering process.

Upon receiving the above instruction from the decoder 46, the DMA controller 47, the transparent color processing section 49, the alpha blending section 50, and the filter 56 perform the following processing.

The DMA controller 47 has the arrangement position X2
The pixel FIFO 48 stores bitmap information 150 for one scan line as shown in FIG. 13 in which the display color of the pixel corresponding to the span width (X4−X2 + 1) is set to “red” from the pixel corresponding to.

Since the transparent color processing section 49 is instructed by the decoder 46 not to perform the transparent color processing, the bit map information 150 for one scan line shown in FIG.
The bitmap information 150 for the scan lines is passed to the alpha blending unit 50.

The alpha blending unit 50 includes a selector 51
The bit map information 151 (the background screen 61) for one scan line shown in FIG.
Bit map information) and the read bit map information 151 for one scan line and the transparent color processing unit 4
9, the bitmap information 152 for one scan line obtained by alpha-blending the portion from X2 to X4 with the bitmap information 150 (bitmap information of the graphic element 62) for one scan line passed from 9 using an alpha value of 100%.
Is stored in the line buffer 52.

Since the filter 56 is instructed not to perform the filter processing, the bit map information is read out from the line buffer 53 selected by the selector 54 and is synchronized with the dot clock of the display device 5. To transfer the bitmap information.

Next, the operation when the user instructs the CPU 1 to display the graphic element 63 superimposed on the graphic element 62 shown in FIG. 6 will be described. At this time, the user instructs display in the graphic element 63 in accordance with predetermined bitmap information, and a specific color (for example, blue) among the colors displayed in the graphic element 63 is specified. Assume that the user instructs to perform the transparent color processing.

When the above-mentioned instruction is performed, the CPU 1
“Blue” is set in the register 41 as the target color of the transparent color processing. Then, when the display of the next frame starts, C
The PU 1 performs the processing shown in the flowcharts of FIGS.

In this process, the CPU 1 advances the scan line to be processed one by one in the same manner as described above. When a scan line in which the graphic element 63 does not exist is to be processed, the same processing as described above is performed. However, when a scan line in which the graphic element 63 exists is to be processed, the following processing is performed.

For example, in addition to the background element 61, the graphic element 6
The processing when the j-th scan line SLj displaying 2, 63 is set as the processing target will be described.

The CPU 1 sets the j-th scan line S
Attention is paid to a graphic element having the largest depth among graphic elements to be displayed on Lj (S3). In this example, since the graphic element having the largest depth is the background screen 61,
1 focuses on the background screen 61.

Thereafter, the CPU 1 performs the same processing as described above to create the span descriptor 120 shown in FIG. 11 corresponding to the scan line SLj on the background screen 61 (S5 to S21).

Next, the CPU 1 increments CNT by 1 to set it to "1" (S22), and thereafter, scan line SLj
Attention is paid to the graphic element having the next largest depth among the graphic elements to be displayed at the top. In this case, attention is paid to the graphic element 62.

After that, the CPU 1 performs the same processing as described above, and creates the span descriptor 130 shown in FIG. 11 corresponding to the scan line SLj of the graphic element 62 (S5 to S21).

Next, the CPU 1 increments CNT by 1 to “2” (S22), and thereafter, scan line SLj
Attention is paid to the graphic element having the next largest depth among the graphic elements to be displayed at the top. In this case, attention is paid to the graphic element 63.

Thereafter, the CPU 1 obtains the arrangement position and span width of the span on the scan line SLj of the graphic element 63, and sets them in the entry of the arrangement position and span width of the span descriptor (S6). In this case,
The arrangement position and span width are X3, X5-X3 + 1, respectively.
As shown in FIG. 15, the span descriptor 1
60 are set in the entry of the arrangement position 162 and the span width 163.

Next, since the user has instructed the display according to the bitmap information in the graphic element 63 of interest at present, the CPU 1 sets the span corresponding to the scan line SLj of the graphic element 63. The address (for example, Fj) for storing the bitmap information is set in the entry of the source address 161 of the span descriptor 160 as shown in FIG. 15, and the color designation flag 164a is turned off (S7 to S9). . The bitmap information of the graphic element 63 is, as shown in FIG.
The PU1 stores the bitmap information 36-1 designated by the user at the address F1 of the graphics command memory 3 in the odd frame, and stores the bitmap information 36-1 in the even frame in the odd frame. The bitmap information 3 specified by the user at the address F2 of the graphics command memory 3
6-2 is stored.

Thereafter, the CPU 1 determines that the graphic element 63 of current interest is a graphic element for which transparent color processing has been specified and for which an alpha value and a filter processing have not been specified. 100%, ON, and OFF are set in the entries of the value 164b, the transparent color flag 164c, and the filter flag 164d, respectively (S1).
2, S14, S15, S16, S18, S20).

As described above, the span descriptor 160 corresponding to the scan line SLj of the graphic element 63
Is created (S21), the CPU 1 increments CNT by 1 to “3” (S22), and returns to the processing of S3 in FIG.

In the case of this example, the graphic elements displayed on the j-th scan line SLj are the background screen 61 and the graphic elements 62 and 63, and the processing for them has been completed. The result is YES and S2
Step 3 is performed.

In S23, as shown in FIG. 16, the created span descriptors 120,
By storing 130 and 160 at successive addresses in the graphics command memory 3 in the order of creation, the line descriptor 17 for one scan line corresponding to the scan line SLj is stored in the graphics command memory 3.
0-j is stored. Now, for example, as shown in FIG.
Line descriptor 17 for one scan line composed of span descriptors 120, 130, and 160
0-j is the address B of the graphics command memory 3
Suppose that it is stored from j.

Thereafter, as shown in FIG. 16, the CPU 1 sets the j-th one of the two screen descriptors 31, 32 prepared on the graphics command memory 3 (for example, the screen descriptor 31). In the entry #j, the line descriptor 170-j
Address "Bj" and the line descriptor 170-j
Is set as the number of span descriptors "3" (S24).

Thereafter, the CPU 1 increments k by +1 and sets the next scan line SL (j + 1) as a processing target (S25).
The same processing as described above is performed.

Then, all the scan lines SL1 to SL
If the same processing as described above is performed on Ln (S26: YES), the bitmap information necessary to display the screen defined by the line descriptor stored in the graphics command memory 3 is converted to the graphics It is stored in the command memory 3 (S27). this time,
Since the necessary bitmap information is the bitmap information of the background screen 61 and the bitmap information of the graphic element 63, they are stored in the addresses A1 and F1 of the graphics command memory 3 as shown in FIG. 16 (S2).
7). In the next frame, the CPU 1 stores the bitmap information of the background screen 61 and the graphic element 63 at addresses A2 and F2 of the graphics command memory 3.

The above processing is repeatedly performed by the CPU 1.

While the CPU 1 is performing the above processing,
The graphics controller 4 performs the following processing.

The DMA controller 42 refers to the register 41 every time the frame is switched, reads the contents of the screen descriptor indicated by the address from the graphics command memory 3 in accordance with the address of the screen descriptor set therein, and reads the screen descriptor. It is stored in the descriptor FIFO 43. Now, for example, assuming that the address “C” of the screen descriptor 31 shown in FIG. 16 is set in the register 41, the DMA controller 42 determines the contents of the entries # 1 to #n of the screen descriptor 31 according to the address “C”. Are read one entry at a time, and the read contents are sequentially read in the screen descriptor FIFO4.
3 is stored.

The DMA controller 44 reads the contents of the screen descriptor 31 stored in the screen descriptor FIFO 43 one entry at a time.
Each scan line SL1 to SL according to the read contents
n is read from the graphics command memory 3 and the line descriptor F
It is stored in the IFO 45.

For example, a screen descriptor FIF
O43 to the screen descriptor 31 shown in FIG.
Read the contents of the j-th entry #j of
Since the line descriptor 170-j corresponding to the scan line SLj is stored in the address Bj of the graphics command memory 3 based on the content thereof, it is known that the number of span descriptors constituting the line descriptor 170-j is "3". Controller 4
4 is an address Bj of the graphics command memory 3
From three span descriptors 120, 130, 16
Line descriptor 170 constituted by 0
−j is read, and the read line descriptor 17 is read.
0-j is stored in the line descriptor FIFO45.

The decoder 46 reads line descriptors from the line descriptor FIFO 45 one scan line at a time in synchronization with the display period of one scan line. Then, the respective span descriptors constituting the line descriptor for one read scan line are sequentially analyzed in the reading order, and the DMA controller 47, the transparent color processing unit 49, and the alpha blending unit 5 are analyzed in accordance with the analysis result.
0, controls the filter 56.

Now, for example, the line descriptor FIF
As a line descriptor for one scan line from O45, a line descriptor 170-j shown in FIG.
Is read, the decoder 46 performs the following processing.

The decoder 46 has the line descriptor 1
70-j, three span descriptors 12
0, 130, and 160, the span descriptors 120,
Read in the order of 130 and 160.

When the span descriptors 120 and 130 are read, the span descriptors 120 and 130 are read.
Is the content shown in FIG.
6 sends the same instruction as described above to the DMA controller 47,
The processing is performed for the transparent color processing blend 49, the alpha blending unit 50, and the filter 56. The DMA controller 47, the transparent color processing blend 49, the alpha blending unit 50, and the filter 56 that have received this instruction perform the same processing as described above.

When the span descriptor 160 is read, the contents are as shown in FIG.
The decoder 46 performs the following processing.

For the DMA controller 47, since the color designation flag 164a is off, based on the information set in the source address 161 and the span width 163, the spanning from the address Fj of the graphics command memory 3 is performed. It instructs to read bitmap information for the number of pixels corresponding to the width (X5−X3 + 1), and based on the information set in the arrangement position 162, stores the bitmap information read from the graphics command memory 3 as: 1 incorporated from the portion corresponding to the arrangement position X3 in the bitmap information for one scan line
Bitmap information for scan lines is stored in pixel FIF
Instruct O48 to store.

Since the transparent color flag 164c is ON, the transparent color processing section 49 is instructed to perform the transparent color processing.

Since the alpha value 164b is 100%, the alpha blending unit 50 is instructed to set the alpha value when performing the alpha blending to 100%. Since the arrangement position 162 and the span width 163 are X3 and X5−X3 + 1, respectively, the bit width information of the pixel corresponding to the arrangement position X3 in the bit map information for one scan line indicates the span width (X
5-X3 + 1) is instructed to perform alpha blending only for bitmap information corresponding to the number of pixels corresponding to the number of pixels.

Filter flag 9 for filter 56
Since 4b is turned off, it instructs not to perform filter processing.

Upon receiving the above instruction from the decoder 46, the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 56 perform the following processing.

From the address Fj of the graphics command memory 3, the DMA controller 47 calculates the span width (X
As shown in FIG. 17, bitmap information for the number of pixels corresponding to (5-X3 + 1) is read, and the read bitmap information is incorporated from a portion corresponding to the arrangement position X3 in the bitmap information for one scan line. Bitmap information 180 for one scan line
It is stored in the IFO 48. In addition, in FIG.
Indicates bitmap information of the graphic element 63 read from the graphics command memory 3.

Since the transparent color processing section 49 is instructed to perform the transparent color processing by the decoder 46, the bit map information 180 for one scan line shown in FIG.
1 to the target color for transparent color processing (blue in this example)
Read.

Next, the transparent color processing section 49 sets the register 4
The target color (blue) of the transparent color processing read from No. 1 is compared with the color of each pixel indicated by the bitmap information 180 for one scan line, and the pixel whose display color is “blue” is obtained. Thereafter, the transparent color processing unit 49 converts the obtained alpha value of the pixel into a value corresponding to a transparent color (0
%) To the alpha blending unit 50 and pass the bitmap information 180 to the alpha blending unit 50. Now, for example, the bitmap information 180
If bitmap information for displaying “blue” is stored in a portion 182 in the middle, the transparent color processing unit 49
Instructs the alpha blending unit 50 to set the alpha value of the pixel corresponding to the portion 182 to an alpha value (0%) equivalent to transparency.

The alpha blending unit 50 includes a selector 51
The bitmap information 184 (the bitmap obtained by synthesizing the bitmap information of the background screen 61 and the bitmap information of the graphic element 62) from the line buffer (referred to as the line buffer 52) selected in FIG. Information), and the read bitmap information 184 for one scan line and the bitmap information 18 for one scan line passed from the transparent color processing unit 49.
Of the parts from X3 to X5 with 0 (bitmap information of the graphic element 63), the remaining part excluding the part 182 is alpha-blended with an alpha value of 100%, and the part 182 is alpha-blended with an alpha value of 0%. The bitmap information 185 for one scan line after the blending is stored in the line buffer 52 again.

Since the filter 56 is instructed not to perform the filtering process, the filter 56 reads the bitmap information from the line buffer 53 selected by the selector 54, and synchronizes with the dot clock of the display device 5. To transfer the bitmap information.

[0141]

As described above, in the present invention,
The line descriptor, which is a graphics command created by the CPU, indicates the position on the scan line of the span of the graphic element to be arranged on the scan line, and the like.
Only the span descriptors for each graphic element are arranged in accordance with the order of superposition from the back to the front when displaying the graphic element, and the CPU, as in the prior art,
To divide the display screen into tiles, there is no need to perform complicated processing such as calculating overlapping parts of graphic elements,
A line descriptor, which is a graphics command, can be created by simply performing a simple process of arranging span descriptors in the order in which graphic elements are superimposed, so that the load on the CPU can be reduced.

Further, according to the present invention, according to the alpha value included in the span descriptor, one scan stored in the line buffer for writing by the line buffer controller among the first and second line buffers. Since there is an alpha blending unit that performs alpha blending of the bitmap information for one line and the bitmap information for one scan line indicated by the storage address included in the span descriptor,
Alpha blending can be performed between overlapping graphic elements.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a graphics command created by a CPU 1;

FIG. 3 is a diagram illustrating a span.

FIG. 4 is a diagram showing a configuration example of an extension instruction.

FIG. 5 is a block diagram showing a configuration example of a graphics controller 4.

FIG. 6 is a diagram showing an example of a screen displayed on the display device 5.

FIG. 7 is a flowchart illustrating a processing example of a CPU 1;

FIG. 8 is a flowchart showing a processing example of a CPU 1;

FIG. 9 is a diagram showing an example of the contents of a span descriptor.

FIG. 10 is a diagram showing an example of the contents of a graphics command memory 3;

FIG. 11 is a diagram showing an example of the contents of a span descriptor.

FIG. 12 is a diagram showing an example of the contents of a graphics command memory 3;

FIG. 13 is a diagram showing bit map information for one scan line stored in a pixel FIFO by a DMA controller when a user designates a color.

FIG. 14 is a diagram for explaining processing contents of an alpha blending unit 50;

FIG. 15 is a diagram illustrating an example of contents of a span descriptor.

FIG. 16 is a diagram showing an example of the contents of a graphics command memory 3;

FIG. 17 is a diagram for explaining the processing contents of a transparent color processing unit 49;

FIG. 18 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... System memory 3 ... Graphics command memory 4 ... Graphics controller 5 ... Display device 6 ... CPU bus 21-1 to 21-n ... Line descriptor 22 ... Screen descriptor 23 ... Span descriptor 24 ... Source address 25 ... Arrangement position 26 ... Span width 27 ... Expansion command 27a ... Color designation flag 27b ... Alpha value 27c ... Transparent color flag 27d ... Filter flag 41 ... Register 42 ... DMA controller 43 ... Screen descriptor FIFO 44 ... DMA controller 45 ... Line descriptor FIFO 46 ... Decoder 47 ... DMA controller 48 ... Pixel FIFO 49 ... Transparent color processing unit 50 ... Alpha blending unit 51 ... Selector 52,53 ... Line buffer 54 ... Kuta 55 ... line buffer controller 56 ... filter 57 ... memory controller

Claims (4)

(57) [Claims] 1. A graphics display device for displaying a graphic element on a display device, comprising: a graphics command memory; a position on the scan line of a span of the graphic element to be displayed on the scan line; and a corresponding bit map. Line descriptors in which span descriptors for each graphic element including the storage address of information are arranged for each scan line of the display device, in which line descriptors in which graphic elements to be displayed on a scan line are arranged in descending order of depth. A graph comprising: a CPU that stores a descriptor in the graphics command memory; and a graphics controller that displays a graphic element on the display device based on the line descriptor stored in the graphics command memory. Display device. 2. The graphics display device according to claim 1, wherein the span is obtained by dividing a graphic element into scan line units of the display device. 3. The graphics controller comprises: a line descriptor reading means for reading a line descriptor corresponding to each scan line stored in the graphics command memory; and a bit map information for storing one scan line. The first and second line buffers; and the first and second line buffers in synchronization with the display period of one scan line.
A line buffer controller for switching one of the line buffers from writing to display and for switching the other line buffer from display to writing, and 1 which is read by the line descriptor reading means.
The span descriptors constituting the line descriptors for the scan lines are used in order from the one with the largest depth, and the bitmap information indicated by the storage address included in the span descriptor is stored in the first and second line buffers. A bitmap information storage unit for storing a line buffer written for writing by the line buffer controller in a portion corresponding to an arrangement position included in the bitmap information; Output means for outputting, to the display device, bitmap information for one scan line stored in the line buffer used for display by the line buffer controller among the line buffers. Item 3. The graphics display device according to Item 2. 4. The span descriptor contains an alpha value when performing alpha blending, and the bitmap information storage means stores the first and second bitmap information in accordance with the alpha value included in the span descriptor.
Out of the line buffer, the bit map information for one scan line stored in the line buffer written for by the line buffer controller and the one scan line indicated by the storage address included in the span descriptor. 4. The graphics display device according to claim 3, further comprising: an alpha blending unit for performing alpha blending with the bitmap information of.