JPH0991444A - Graphics display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve a load of a CPU in the graphics display device in which the CPU generates a graphics command and a graphics controller displays a graphic element based on the graphics command. SOLUTION: A CPU generates line descriptors 21-1-21-n each consisting of span descriptors 23 for each graphic element including a position of a span of the graphic element displayed on a scanning line and a storage address of corresponding bit map information arranged sequentially in the order of deeper depth of the graphic element for each scanning line of a display device and stores the generated line descriptors 21-1-21-n in a graphics command memory. Then a graphics controller displays the graphic element onto the display device based on the line descriptors 21-1-21-n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU that creates a graphics command for displaying a graphic element on a display device, and a graphics controller causes the display device to display a graphic element based on the graphics command created by the CPU. The present invention relates to a graphics display device for displaying.

[0002]

2. Description of the Related Art When a graphic element such as a window is displayed on a display device, a graphics command for displaying the graphic element on the display device is CP in order to reduce the load on the CPU and improve the drawing speed.
It is conventional for a graphics controller to display a graphical element on a display device based on a graphics command created by U and created by the CPU.

Examples of such a technique include "Nikkei Electronics, July 14, 1986, No. 399."
No., published by Nikkei McGraw-Hill Company, P124-P128 ”. FIG. 18 is a block diagram for explaining the above-mentioned conventional technique. The display device 108 has two windows 1 in addition to the background screen.
When displaying 09 and 110, the CPU 100 displays the display screen of the display device 108 on the five strips ST1.
To ST5 and further strips ST1 to ST5
Make a tile by dividing the inside horizontally. For example, the strip ST3 is divided into four tiles T1 to T4.

Further, the CPU 100 has the bitmap information 104 and the windows 109 and 11 corresponding to the background screen.
The bitmap information 105 and 106 corresponding to 0 is stored in the bitmap memory 103, and the window descriptor 102 is stored in the memory 101. The window descriptor 102 is a graphics command including the width of each tile, the address of the bitmap memory 103 in which bitmap information to be displayed in each tile is stored, and the like, and is created by the CPU 100 and stored in the memory 101. It is a thing.

The graphics controller 107 displays two windows 109 and 110 on the display device 108 in addition to the background screen by switching the display address according to the display timing while referring to the window descriptor 102. For example, a strip S in which windows 109 and 110 overlap
When the first scan line of T3 is displayed, the display address is changed to the addresses A1, A2, A3, A4 in the bitmap memory 103 at each display timing of the first scan line of the tiles T1, T2, T3, T4. Switch to.

[0006]

As described above, conventionally, it is necessary to divide the display screen of the display device into strips and tiles. In order to perform this processing, the overlapping portion of graphic elements is calculated. However, there is a problem that the load on the CPU becomes large because the processing such as performing is required. In addition, the display screen of the display device is divided into tiles that do not overlap each other in consideration of how the graphic elements to be displayed overlap each other, and when the graphic elements are displayed, the width of each tile and the tiles should be displayed. Since the display address is switched to the start address corresponding to each tile at the display timing of each tile while referring to the window descriptor including the address of the bitmap information etc. There is a problem in that it is not possible to perform synthesis processing such as alpha blending.

Therefore, an object of the present invention is to provide a graphics display device which can reduce the load on the CPU and can perform a synthesis process of graphic elements.

[0008]

SUMMARY OF THE INVENTION To achieve the object of reducing the load on the CPU, the present invention provides a graphics display device for displaying graphic elements on a display device, including a graphics command memory and a scan line. The span descriptor for each graphic element, including the position on the scan line of the span of the graphic element to be displayed in and the corresponding storage address of bitmap information, is displayed in order from the largest depth of the graphic element displayed on the scan line. A CPU that stores line descriptors arranged for each scan line of the display device, stores the generated line descriptor in the graphics command memory, and the display device based on the line descriptor stored in the graphics command memory To shape It is obtained by a graphics controller for displaying the element.

Further, in order to achieve the object of the present invention to enable a compositing process of graphic elements such as alpha blending, the span descriptor includes an alpha value for performing alpha blending, and the bitmap information storing means. Is a bitmap of one scan line stored in a line buffer for writing by the line buffer controller in the first and second line buffers according to the alpha value included in the span descriptor. 1 indicated by the information and the storage address contained in the span descriptor
It is provided with an alpha blending section for performing alpha blending with the bitmap information of scan lines.

A graphic in which the CPU displays on the scan line a span descriptor for each graphic element including the position on the scan line of the span of the graphic element to be displayed on the scan line and the storage address of the corresponding bitmap information. A line descriptor that is arranged in order from the element with the largest depth is created for each scan line of the display device, the created line descriptor is stored in the graphics command memory, and the graphics controller is stored in the graphics command memory. The graphic element is displayed on the display device based on the line descriptor.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a CPU 1 having a function of creating a graphics command for defining a display screen of a display device 5, and the like.
The system memory 2 used by the CPU 1, the graphics command memory 3 in which the graphics commands created by the CPU 1 and the bitmap information of graphic elements to be displayed on the display device 5, and the like are stored. A graphics controller 4 for displaying graphic elements on the display device 5 in accordance with the graphics command and bitmap information stored therein;
It is composed of a PU bus 6.

FIG. 2 is a diagram showing an example of the structure of a graphics command created by the CPU 1. The line descriptors 21- of the number of scan lines of the display device 5 are shown.
1 to 21-n and a screen descriptor 22.

Line descriptors 21-1 to 21-n
Respectively correspond to the first to nth scan lines SL1 to SLn of the display device 5, and the positions on the scan lines of the respective spans of the graphic elements arranged on the corresponding scan lines are shown. It has a configuration in which the span descriptors for each graphic element shown are arranged in order from the one having the largest depth of the graphic element displayed on the scan line. All span descriptors in one line descriptor are stored at consecutive addresses in the graphics command memory 3.

The span of the graphic element is displayed by the display device 5.
The graphic elements displayed on the screen are divided into scan line units of the display device 5. Therefore, as shown in FIG. 3, a background screen (a background screen is also a kind of graphic element) a
When the graphic element b is displayed on the graphic element b and the graphic element c is further displayed on the graphic element b, the line descriptor 21 corresponding to the i-th (1 ≦ i ≦ n) scan line SLi of the display device 5 is displayed. -I is a span descriptor SDa, SDb, SDc that indicates the position on the scan line SLi of each of the spans Sa, Sb, Sc corresponding to the background screen a and the graphic elements b, c, and
It is arranged in the descending order of depth such as SDa, SDb, SDc.

Line descriptors 21-1 to 21-n
The span descriptor 23, which is a component of the above, includes a source address 24, an arrangement position 25, a span width 25, and an extension instruction 27.

The source address 24 indicates an address in the graphics command memory 3 in which the bitmap information of the span targeted by the span descriptor 23 is stored.

The arrangement position 25 is the span descriptor 2
3 shows the arrangement start position on the scan line of the span of interest. For example, at the arrangement position 25 of the span descriptor corresponding to the span Sb shown in FIG.
“Xb” is set.

The span width 26 is defined by the span descriptor 2
3 shows the width of the target span. For example, "Lb" is set to the span width 26 of the span descriptor corresponding to the span Sb shown in FIG.

The extended instruction 27, as shown in FIG. 4, is to fill the span with the color designated by the CPU 1,
Alternatively, a color designation flag 27a indicating whether to display the span according to the bitmap information designated by the source address 24, an alpha value 27b when alpha blending is performed, and whether transparent color processing is performed or not It includes a transparent color flag 27c that indicates and a filter flag 27d that indicates whether or not the filter provided in the graphics controller 4 is to perform filter processing. still,
To fill the span with the color specified by CPU1,
The color designation flag 27a is turned on, and the fill color is set in the entry of the source address 24 in the span descriptor 23.

The screen descriptor 22 has entries # 1 to #n corresponding to the scan lines SL1 to SLn of the display device 5, respectively. The line descriptor 2 is assigned to each of the entries # 1 to #n.
Addresses and line descriptors 21-1 to 21-2 in the graphics command memory 3 of 1-1 to 21-n
The number of span descriptors forming 1-n is set.

FIG. 5 is a block diagram showing a configuration example of the graphics controller 4, which includes a register 41 and a DMA.
Controller 42 and screen descriptor FIF
O43, DMA controller 44, line descriptor FIFO 45, decoder 46, DMA controller 47, pixel FIFO 48, transparent color processing unit 49, alpha blending unit 50, selector 51,
It is composed of line buffers 52 and 53 that store bitmap information for one scan line, a selector 54, a line buffer controller 55, a filter 56, and a memory controller 57.

In the register 41, the storage start address of the screen descriptor, the filter coefficient, the color to be the target of the transparent color processing, etc. are set by the CPU 1.

The DMA controller 42 reads the screen descriptor from the graphics command memory 3 according to the storage start address of the screen descriptor set in the register 41 and stores the read screen descriptor in the screen descriptor FIFO 43 each time the frame is switched. Have a function.

The DMA controller 44 has a function of reading the screen descriptor from the screen descriptor FIFO 43, reading the line descriptor from the graphics command memory 3 according to the contents of each entry of the read screen descriptor, and storing the line descriptor in the line descriptor FIFO 45. Yes, it operates as a line descriptor reading means.

The decoder 46 has a function of reading line descriptors for each scan line from the line descriptor FIFO 45 in synchronization with the display period of one scan line, and a span descriptor constituting a line descriptor for the read one scan line. It has a function of decoding in descending order of depth and controlling the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 56 according to the decoding result.

The DMA controller 47 has a decoder 46.
When it is instructed to read the bitmap information by, the bitmap information instructed by the decoder 46 is read from the graphics command memory 3,
Bit map information for one scan line, which is included in the portion designated by the decoder 46, is stored in the pixel FIFO.
Store in 48. When the decoder 46 instructs the span to be filled with the color designated by the CPU 1, the bitmap information for one scan line corresponding to the span being filled with the color designated by the CPU 1 is stored in the pixel FIFO 48. .

When the decoder 46 has not instructed the transparent color processing to perform the transparent color processing, the transparent color processing section 49 reads out the bitmap information for each one scan line from the pixel FIFO 48 and sequentially performs the alpha blending section 50.
Pass to. When it is instructed to perform the transparent color process, the bitmap information is read from the pixel FIFO 48 for each scan line and sequentially passed to the alpha blending unit 50, and the read bitmap information for one scan line is also read. By comparing the color of each pixel on the span indicated by the target color with the transparent color processing set in the register 41 by the CPU 1, and the color indicated by the bitmap information is set in the register 41 by the transparent color processing. The alpha blending unit 50 is instructed to set the alpha value of the pixel that matches the target color of (1) to a transparent color.

The line buffer controller 55 synchronizes with the line buffer 5 in synchronization with the display period of one scan line.
The selector 51 and the selector 54 are controlled so as to select 2 and 53 alternately. However, while the selector 51 is selecting the line buffer 52, the selector 54 is selecting the line buffer 53, and while the selector 51 is selecting the line buffer 53, the selector 54 is selecting the line buffer 52. To select. Selector 51
The line buffer selected by is for writing, and the line buffer selected by the selector 54 is for displaying.

Bit map information for one scan line is stored in the line buffers 52 and 53.

The alpha blending unit 50 reads the bit map information for one scan line from the writing line buffer selected by the selector 51 in the line buffer 52 or the line buffer 53, and passes it from the transparent color processing unit 49. The span of the color of each pixel on the span indicated by the bitmap information for one scan line and the color of each pixel indicated by the bitmap information for one scan line read from the write line buffer And the color of the pixel corresponding to are blended according to the alpha value instructed by the decoder 46. Then, the alpha-blended bitmap information for one scan line is stored again in the writing line buffer of the line buffers 52 and 53. For the pixel instructed by the transparent color processing unit 49 to make the alpha value equivalent to the transparent color, the alpha instructed by the transparent color processing unit 49 is used instead of the alpha value instructed by the decoder 46. Alpha blending is performed using the value (alpha value 0% corresponding to the transparent color). This alpha blend unit 50, decoder 46, DMA controller 47, pixel FIFO 4
8. The transparent color processing unit 49 constitutes a bitmap information storage means.

The filter 56 includes line buffers 52 and 5
3 has a function of reading bitmap information for one scan line from the display line buffer and transferring the read bitmap information to the display device 5, and operates as an output unit. Incidentally, the decoder 4
When the instruction to perform the filter processing is given by 6, the filter coefficient set by the CPU 1 is read from the register 41, and the filter processing according to the read coefficient is performed.

The memory controller 57 includes CPUs 1 and D.
The arbitration of access to the graphics command memory 3 of the MA controllers 42, 44, 47 is performed, and DM
When the data is read from the graphics command memory 3 in accordance with the access request from the A controllers 42, 44, 47, the data is transferred to the requesting DMA controller.

Next, the operation of this embodiment will be described.

Now, if the user of the graphics display device is C
The PU 1 is instructed to activate the graphics display device, and thereafter, the graphic element 62 is instructed to be displayed on the background screen 61 of the display device 5, as shown in FIG. It is assumed that an instruction is given to display the graphic element 63 in an overlapping manner.

When the activation of the graphics display device is instructed, the CPU 1, as shown in the flow charts of FIGS. 7 and 8,
The value of the variable k indicating the number of the scan line to be processed is set to "1", and the value of the variable CNT indicating the number of span descriptors in one scan line is set to "0" (S1). , S2).

After that, the CPU 1 pays attention to the graphic element having the largest depth among the graphic elements to be displayed on the first scan line SL1 (S3). In this example, since only the background screen 61 is displayed on the first scan line SL1, the CPU 1 pays attention to the background screen 61.

Next, the CPU 1 obtains the X coordinate value of the intersection of the currently noticed background screen 61 and the first scan line SL1 (S5). In the case of this example, X at the intersection
X1 and X6 are obtained as coordinate values. In addition, X1, X6
Are X coordinate values at the left and right ends of the screen, respectively.

After that, the CPU 1 obtains the arrangement position and span width of the span on the scan line SL1 of the background screen 61, and sets them in the entries of the arrangement position and span width of the span descriptor (S6). In this example,
Arrangement position and span width are X1, X6-X1 + 1 respectively
Therefore, as shown in FIG. 9, the span descriptor 90
Is set in the entry of the arrangement position 92 and the span width 93.

Next, since the graphic element of interest is the background screen 61 and the user has not designated a color, the CPU 1 determines that the first scan line S
The address in the graphics command memory 3 of the bitmap information of the background screen 61 to be displayed on L1 is set in the entry of the source address 91 of the span descriptor 90, and further the entry of the color designation flag 94a is set to OFF. (FIG. 8, S7-S9). Here, the bitmap information of the background screen 61 displayed in the odd frame is stored in the address “A1” on the graphics command memory 3 by the CPU 1, and the background screen 61 displayed in the even frame is displayed. The bitmap information of is stored in the address "A2" on the graphics command memory 3. Now, for example, if it is a frame period in which the bitmap information of the background screen 61 displayed in an odd number of frames is stored in the graphics command memory 3, the CPU 1 determines the source address of the span descriptor 90 as shown in FIG. The address “A1” is set in the entry 91.

After that, since the graphic element of interest is the background screen 61, and the alpha value, the transparent color processing, and the filter processing are not designated by the user, the CPU 1 makes a span as shown in FIG. 100%, OFF, and OFF are set in the entries of the alpha value 94b, the transparent color flag 94c, and the filter flag 94d of the descriptor 90 (S12, S14, S15, S17, S1).
8, S20).

As described above, 1 as shown in FIG.
When the span descriptor 90 for the span is created (S
21), the CPU 1 increments CNT by 1 (S22), and returns to the process of S3 of FIG.

In the case of this example, since the graphic element displayed on the first scan line SL1 is only the background screen 61, the determination result of S4 is YES, and the processing of S23 is performed.

In step S23, the created span descriptor for one scan line is stored in consecutive addresses of the graphics command memory 3 in the order of creation, thereby storing the line descriptor for one scan line in the graphics command memory 3. In this example,
Since only the span descriptor 90 shown in FIG. 9 is created as the span descriptor of the first scan line SL1, one span descriptor 9 is created.
A line descriptor for one scan line composed of 0 is stored in the graphics command memory 3. Now, for example, it is assumed that the line descriptor 33-1 for one scan line configured only by the span descriptor 90 is stored at the address B1 on the graphics command memory 3 as shown in FIG.

After that, as shown in FIG. 10, the CPU 1 selects the first one of the two screen descriptors 31 and 32 (for example, the screen descriptor 31) prepared on the graphics command memory 3. The address "B1" of the line descriptor 33-1 and the span descriptor number "1" forming the line descriptor 33-1 are set in the entry # 1 (S).
24). Here, the screen descriptors 31, 32
The reason why two are provided is to enable smooth display by writing information for displaying the next frame in the other screen descriptor while using one screen descriptor for display. is there.

Next, the CPU 1 increments the value of the variable k by 1 (S25) and performs the same processing as described above for the second scan line SL2. As a result, as shown in FIG. 10, the line descriptor 33-2 for the second scan line SL2 is stored at the address B2 of the graphics command memory 3, and the second entry # of the screen descriptor 31 is stored. Two
At the address "B2" of the line descriptor 33-2.
And the number of span descriptors forming the line descriptor 33-2 are set to "1".

Thereafter, the CPU 1 is the third, the fourth,
..., the n-th scan line SL3, SL4, ..., S
The same processing as described above is performed on Ln. As a result, as shown in FIG. 10, the line descriptors 33-3, ..., 33-n for the third to n-th scan lines SL3 ,.
, And the n-th entry # 3, ..., #n of the screen descriptor 31 are set with information about the line descriptors 33-3 ,.

Then, all the scan lines SL1 to S
When the same processing as described above is performed on Ln, the CPU 1
Stores in the graphics command memory 3 the bitmap information necessary for displaying the screen defined by the line descriptors 33-1 to 33-n stored in the graphics command memory 3 this time (S2).
7). In the case of this example, the line descriptor 33-1
The bitmap information necessary to display the screen defined by 33-n is only the bitmap information of the background screen 61, and the bitmap information is the background to be displayed in the odd-numbered frame as described above. Since it is for the screen 61, the CPU 1 stores the bitmap information 35-1 of the background screen 61 at the address "A1" as shown in FIG.

After that, when the display of one frame ends, the CPU 1 causes the screen descriptor 3 to be stored in the register 41 in the graphics controller 4 shown in FIG.
The address "C" of 1 is set.

Further, when the display of the next frame is started, the CPU 1 performs the processing shown in the flowcharts of FIGS. 7 and 8 again. However, in this case, since the previously used screen descriptor 31 is used for display, the same process as described above is performed using the other screen descriptor 32. As a result, as shown in FIG. 10, the line descriptors 34- of the scan lines SL1 to SLn are formed.
1 to 34-n are stored in the addresses D1 to Dn of the graphics command memory 3, and the addresses "D1 to Dn" of the line descriptors 34-1 to 34-n and the line descriptors 34-1 to 34-n are configured. The span descriptor number "1" to be set is set in each entry # 1 to #n of the screen descriptor 32.

After that, when the display of one frame ends, the CPU 1 sets the address "E" of the screen descriptor 32 in the register 41 in the graphics controller 4 instead of the address "C" of the screen descriptor 31. In this way, the CPU 1 causes the address “C” of the screen descriptors 31 and 32,
"E" is alternately set in the register 41 every time the display of the frame is completed. If the display content of the next frame is the same as the display content of the previous frame, the CPU 1 executes the processing shown in FIGS.
The process shown in and the rewriting of the register 41 are not performed.

The CPU 1 repeats the above processing until the user instructs the display of the graphic element 62.

While the CPU 1 is performing the above processing, the graphics controller 4 performs the following processing.

The DMA controller 42 refers to the register 41 every time the frame is switched, reads the contents of the screen descriptor indicated by the above address from the graphics command memory 3 in accordance with the address of the screen descriptor set therein, and the screen descriptor is read. It is stored in the descriptor FIFO 43. Now, assuming that the address “C” of the screen descriptor 31 shown in FIG. 10 is set in the register 41, the DMA controller 42 determines the contents of the entries # 1 to #n of the screen descriptor 31 according to the address “C”. Is read one entry at a time, and the read contents are sequentially read by the screen descriptor FIFO 43.
To be stored.

The DMA controller 44 reads the contents of the screen descriptor 31 stored in the screen descriptor FIFO 43 one entry at a time,
Each scan line SL1 to SL according to the read contents
line descriptors 33-1 to 33-n corresponding to n
Is read from the graphics command memory 3 and stored in the line descriptor FIFO 45.

For example, the screen descriptor FIF
When the content of the first entry # 1 of the screen descriptor 31 is read from O43, the line descriptor 33-1 corresponding to the scan line SL1 is stored in the address B1 of the graphics command memory 3 according to the content, and the line descriptor Since it can be seen that the number of span descriptors configuring 33-1 is “1”, the DMA controller 44 determines the line descriptor 31-1 configured by one span descriptor from the address B1 of the graphics command memory 3. The read line descriptor 31-1 is read and stored in the line descriptor FIFO 45.

The decoder 46 reads the line descriptor for each scan line from the line descriptor FIFO 45 in synchronization with the display period of one scan line. Then, the span descriptors constituting the read line descriptors for one scan line are sequentially analyzed, and the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 5 are analyzed according to the analysis result.
Control 6

Now, for example, if the line descriptor 33-1 constituted only by the span descriptor 90 shown in FIG. 9 is read, the decoder 46 performs the following processing.

For the DMA controller 47, since the color designation flag 94a is turned off, the span from the address A1 of the graphics command memory 3 is spanned based on the information set in the source address 91 and the span width 93. While instructing to read out the bitmap information for the number of pixels corresponding to the width (X6-X1 + 1),
One scan line in which the bitmap information read from the graphics command memory 3 based on the information set in the arrangement position 92 is incorporated from the portion corresponding to the arrangement position X1 in the bitmap information for one scan line. To store the bitmap information of the above in the pixel FIFO 48.

Since the transparent color flag 94c is off, the transparent color processing section 49 is instructed not to perform the transparent color processing.

Since the alpha value 94b is 100%, the alpha blending unit 50 is instructed to set the alpha value at the time of alpha blending to 100%. Further, the arrangement position 92 and the span width 93 are each X
1, X6-X1 + 1, the span width (X6-X1 is calculated from the bitmap information of the pixel corresponding to the arrangement position X1 in the bitmap information for one scan line.
It is instructed to perform alpha blending only on the bitmap information for the number of pixels corresponding to +1).

For the filter 56, the filter flag 9
Since 4d is off, it is instructed not to perform the filtering process.

Upon receiving the above instruction from the decoder 46, the DMA controller 47, the transparent color processing section 49, the alpha blending section 50, and the filter 56 perform the following processing.

The DMA controller 47 operates from the address A1 of the graphics command memory 3 to the span width (X6
-X1 + 1), the bitmap information for the number of pixels corresponding to (X1 + 1) is read, and the read bitmap information is incorporated from the portion corresponding to the arrangement position X1 in the bitmap information for one scan line. Are stored in the pixel FIFO 48.

Since the transparent color processing section 49 is instructed by the decoder 46 not to perform the transparent color processing, the bitmap information for one scan line is read from the pixel FIFO 48, and the bitmap for one scan line thus read is read. The information is passed to the alpha blend unit 50.

The alpha blend unit 50 includes a selector 51.
The bit map information for one scan line is read from the write line buffer (referred to as the line buffer 52) selected by, and the bit map information for the read one scan line and the one passed from the transparent color processing unit 49. A portion of the scan line bitmap information designated by the decoder 46 (from the bitmap information of the pixel corresponding to the arrangement position X1 to the span width X6−
Bitmap information for the number of pixels corresponding to X1 + 1)
100% of the alpha value specified by the decoder 46
The alpha blending is performed and the bitmap information for one scan line that has been alpha blended is stored in the line buffer 52 again.

Since the filter 56 is instructed not to perform the filtering process, the bit map information is read from the line buffer 53 selected by the selector 54, and the display device 5 is synchronized with the dot clock of the display device 5. Transfer the bitmap information to.

Next, the operation when the user instructs the CPU 1 to display the graphic element 62 on the background screen 61 shown in FIG. 6 will be described. At that time, it is assumed that the user instructs to paint the graphic element 62 with a predetermined color (for example, red).

After the above-mentioned instruction is given, when the display of the next frame is started, the CPU 1 performs the processing shown in the flowcharts of FIGS. 7 and 8.

In this process, the CPU 1 advances the scan line to be processed one by one and performs the process, as described above. When the scan line having only the background screen 61 is the processing target, the same processing as described above is performed, but when the scan line having the graphic element 62 in addition to the background screen 61 is the processing target. , Perform the following processing.

For example, in addition to the background screen 61, the graphic element 6
When the j-th scan line in which 2 also exists is set as the processing target, the following processing is performed.

The CPU 1 uses the j-th scan line S
Of the graphic elements displayed on Lj, the graphic element having the largest depth is focused (S3). In the case of this example, the graphic element having the largest depth is the background screen 61.
1 pays attention to the background screen 61.

After that, the CPU 1 performs the same processing as described above to create the span descriptor corresponding to the scan line SLj of the background screen 61 (S5 to S2).
1). Now, for example, the scan line SL of the background screen 61
It is assumed that the span descriptor 120 shown in FIG. 11 is created as the span descriptor corresponding to j.

Next, the CPU 1 increments CNT by 1 to "1" (S22), and then scan line SLj.
Of the graphic elements displayed on the top, pay attention to the graphic element having the next largest depth. In the case of this example, attention is paid to the graphic element 62.

Then, the CPU 1 sets X at the intersection of the graphic element 62 of interest and the j-th scan line SLj.
The coordinate value is obtained (S5). In the case of this example, X2 and X4 are obtained as the X coordinate value of the intersection.

After that, the CPU 1 obtains the arrangement position and span width of the span on the scan line SLj of the graphic element 62, and sets them in the entries of the arrangement position and span width of the span descriptor (S6). In this example,
Arrangement position and span width are X2, X4-X2 + 1 respectively
Therefore, as shown in FIG. 11, the span descriptor 1
It is set in the entry of the arrangement position 132 of 30 and the span width 133.

Next, as shown in FIG. 11, the CPU 1 determines that the graphic element 62 of interest is a graphic element that the user has instructed to paint in red.
Red is set to the entry of the source address 131 of the span descriptor 130, and the color designation flag 134a is turned on (S7, S10, S11).

After that, the CPU 1 causes the graphic element 62, which is currently focused, to be processed by the user for alpha value, transparent color processing,
Since it is a graphic element for which filter processing is not specified,
As shown in FIG. 11, the entries of the alpha value 134b, the transparent color flag 134c, and the filter flag 134d of the span descriptor 130 are 100%, OFF, and
Set off (S12, S14, S15, S17, S
18, S20).

As described above, as shown in FIG.
Span descriptor 120 for one scan line,
When 130 is created (S21), CPU1 adds CNT +
1 is set to "2" (S22), and the process returns to S3 in FIG.

In the case of this example, the graphic elements displayed on the j-th scan line SLj are the background screen 61 and the graphic element 62, both of which have already been processed.
The determination result of S4 is YES, and the process of S23 is performed.

At S23, as shown in FIG. 12, the span descriptors 120 for one scan line created,
By storing 130 at consecutive addresses in the graphics command memory 3 in the order of creation, the line descriptor 140-j for one scan line corresponding to the scan line SLj is stored in the graphics command memory 3. Now, for example, as shown in FIG. 12, it is assumed that one scan line of line descriptor 140-j including span descriptors 120 and 130 is stored from the address Bj of the graphics command memory 3.

Thereafter, as shown in FIG. 12, the CPU 1 selects the j-th one of the two screen descriptors 31 and 32 (for example, the screen descriptor 31) prepared on the graphics command memory 3. In the entry #j, the address “Bj” of the line descriptor 33-j and the span descriptor number “2” that configures the line descriptor 33-j are set (S).
24).

Thereafter, the CPU 1 increments k by 1 and sets the next scan line SL (j + 1) as the processing target (S25),
The same processing as described above is performed.

The CPU 1 repeats the above processing until the user instructs the display of the graphic element 63.

While the CPU 1 is performing the above processing, the graphics controller 4 performs the following processing.

The DMA controller 42 refers to the register 41 every time the frame is switched, reads the contents of the screen descriptor indicated by the above address from the graphics command memory 3 in accordance with the address of the screen descriptor set in the register 41, and It is stored in the descriptor FIFO 43. Now, assuming that the address “C” of the screen descriptor 31 shown in FIG. 12 is set in the register 41, the DMA controller 42 reads the contents of the screen descriptor 31 according to the address “C”, and reads the read contents. The data is sequentially stored in the screen descriptor FIFO 43.

The DMA controller 44 reads the contents of the screen descriptor 31 stored in the screen descriptor FIFO 43 one entry at a time,
Each scan line SL1 to SL according to the read contents
The line descriptor corresponding to n is read from the graphics command memory 3 and the line descriptor F
Store in IFO45.

For example, the screen descriptor FIF
Screen descriptor 31 shown in FIG. 12 from O43
If the contents of the j-th entry #j of
Since the line descriptor 140-j corresponding to the scan line SLj is stored at the address Bj of the graphics command memory 3 and the number of span descriptors forming the line descriptor 140-j is "2" according to the contents, the DMA Controller 4
4 is the address Bj of the graphics command memory 3
To read the line descriptor 140-j composed of the two span descriptors 120 and 130, and store the read line descriptor 140-j in the line descriptor FIFO 45.

The decoder 46 reads the line descriptor for each scan line from the line descriptor FIFO 45 in synchronization with the display period of one scan line. Then, the span descriptors constituting the read line descriptors for one scan line are sequentially analyzed, and the DMA controller 47, the transparent color processing unit 49, the alpha blending unit 50, and the filter 5 are analyzed according to the analysis result.
Control 6

Now, for example, the line descriptor FIF
As a line descriptor for one scan line from O45, the line descriptor 140-j shown in FIG.
, The decoder 46 performs the following processing.

The decoder 46 uses the line descriptor 1
Of the two span descriptors that make up 40-j,
First, the span descriptor 120 corresponding to a span having a large depth is read, and then the span descriptor 130 is read.

When the span descriptor 120 is read, since the contents of the span descriptor 120 are as shown in FIG. 11, the decoder 46 issues the same instruction as described above to the DMA controller 47, the transparent color processing blend 49, and the alpha blend. This is performed for the unit 50 and the filter 56. The DMA controller 47, the transparent color processing blend 49, the alpha blending unit 50, and the filter 56 that received this instruction also perform the same processing as described above.

After that, when the span descriptor 130 is read, since the content is as shown in FIG. 11, the decoder 46 performs the following processing.

For the DMA controller 47, since the color designation flag 134a is turned on, it corresponds to the arrangement position X2 based on the information set in the source address 131, the arrangement position 132, and the span width 133. The pixel FIFO 48 is instructed to store the bitmap information for one scan line that makes the display color of the pixel of the span width (X4-X2 + 1) from the pixel "red".

Since the transparent color flag 134c is off, the transparent color processing section 49 is instructed not to perform the transparent color processing.

Since the alpha value 134b is 100%, the alpha blending unit 50 is instructed to set the alpha value at the time of alpha blending to 100%. Further, since the arrangement position 132 and the span width 133 are respectively X2, X4-X2 + 1, the span width (X4 is calculated from the bitmap information of the pixel corresponding to the arrangement position X2 in the bitmap information for one scan line.
It is instructed to perform alpha blending only on the bitmap information corresponding to the number of pixels corresponding to (-X2 + 1).

Filter flag 1 for filter 56
Since 34d is turned off, it instructs not to perform the filtering process.

Upon receiving the above instruction from the decoder 46, the DMA controller 47, the transparent color processing section 49, the alpha blending section 50 and the filter 56 perform the following processing.

The DMA controller 47 has an arrangement position X2.
The pixel FIFO 48 stores one scan line worth of bitmap information 150 as shown in FIG. 13 in which the display color of the pixel corresponding to the span width (X4−X2 + 1) is changed to “red”.

Since the transparent color processing section 49 has been instructed by the decoder 46 not to perform the transparent color processing, the bitmap information 150 for one scan line shown in FIG.
The bitmap information 150 for the scan lines is passed to the alpha blending unit 50.

The alpha blend unit 50 includes a selector 51.
Bit map information 151 (background screen 61) for one scan line shown in FIG.
(Bitmap information of) and the read-in bitmap information 151 for one scan line and the transparent color processing unit 4
Bit map information 152 for one scan line obtained by alpha blending the part from X2 to X4 with the bit map information 150 for one scan line (bitmap information of the graphic element 62) passed from 9
Are stored in the line buffer 52.

Since the filter 56 is instructed not to perform the filtering process, the bitmap information is read from the line buffer 53 selected by the selector 54, and the display device 5 is synchronized with the dot clock of the display device 5. Transfer the bitmap information to.

Next, the operation when the user instructs the CPU 1 to display the graphic element 63 on the graphic element 62 shown in FIG. 6 will be described. At that time, the user instructs the graphic element 63 to perform display according to predetermined bitmap information, and regarding a specific color (for example, blue) among the colors displayed in the graphic element 63. It is assumed that the transparent color processing is instructed.

When the above instruction is given, the CPU 1
“Blue” is set in the register 41 as the target color of the transparent color processing. After that, when it is time to start displaying the next frame, C
PU1 performs the processing shown in the flowcharts of FIGS.

In this process, the CPU 1 advances the scan line to be processed one by one, and executes the process, as described above. When the scan line in which the graphic element 63 does not exist is the processing target, the same processing as described above is performed, but when the scan line in which the graphic element 63 exists is the processing target, the following processing is performed.

For example, in addition to the background element 61, the graphic element 6
Processing when the j-th scan line SLj displaying 2, 63 is the processing target will be described.

The CPU 1 uses the j-th scan line S
Of the graphic elements displayed on Lj, the graphic element having the largest depth is focused (S3). In the case of this example, the graphic element having the largest depth is the background screen 61.
1 pays attention to the background screen 61.

After that, the CPU 1 performs the same processing as described above to create the span descriptor 120 shown in FIG. 11 corresponding to the scan line SLj of the background screen 61 (S5 to S21).

Next, the CPU 1 increments CNT by 1 to "1" (S22), and thereafter, scan line SLj.
Of the graphic elements displayed on the top, pay attention to the graphic element having the next largest depth. In this case, attention is paid to the graphic element 62.

After that, the CPU 1 performs the same processing as described above to create the span descriptor 130 shown in FIG. 11 corresponding to the scan line SLj of the graphic element 62 (S5 to S21).

Next, the CPU 1 increments CNT by 1 to "2" (S22), and then the scan line SLj.
Of the graphic elements displayed on the top, pay attention to the graphic element having the next largest depth. In this case, attention is paid to the graphic element 63.

After that, the CPU 1 obtains the arrangement position and span width of the span of the graphic element 63 on the scan line SLj, and sets them in the entries of the arrangement position and span width of the span descriptor (S6). In this example,
Arrangement position and span width are X3, X5-X3 + 1 respectively
Therefore, as shown in FIG. 15, the span descriptor 1
It is set in the entry of 60 arrangement positions 162 and span width 163.

Next, since the CPU 1 has been instructed by the user to perform the display according to the bitmap information in the graphic element 63 of interest, the span of the graphic element 63 corresponding to the scan line SLj. 15, an address (for example, Fj) for storing the bitmap information of that is set in the entry of the source address 161 of the span descriptor 160, and the color designation flag 164a is turned off (S7 to S9). . Note that the bitmap information of the graphic element 63 is C as shown in FIG.
The PU1 stores it in the graphics command memory 3, and in the odd frame, the bitmap information 36-1 designated by the user is stored in the address F1 of the graphics command memory 3, and in the even frame. The bitmap information 3 designated by the user at the address F2 of the graphics command memory 3
6-2 is stored.

After that, the CPU 1 determines that the graphic element 63 of interest is a graphic element for which transparent color processing has been specified but no alpha value or filter processing has been specified, so that as shown in FIG. 100%, ON, and OFF are set in the entry of the value 164b, the transparent color flag 164c, and the filter flag 164d, respectively (S1).
2, S14, S15, S16, S18, S20).

As described above, the span descriptor 160 corresponding to the scan line SLj of the graphic element 63.
(S21), the CPU 1 increments CNT to "3" (S22), and returns to the process of S3 in FIG.

In the case of this example, the graphic elements displayed on the j-th scan line SLj are the background screen 61 and the graphic elements 62 and 63, and all the processing for them has been completed, so the determination in S4 is made. The result is YES and S2
Process 3 is performed.

At S23, as shown in FIG. 16, the span descriptors 120 for one scan line created,
By storing 130 and 160 at consecutive addresses in the graphics command memory 3 in the order of creation, the line descriptor 17 for one scan line corresponding to the scan line SLj is stored in the graphics command memory 3.
Store 0-j. Now, for example, as shown in FIG.
A line descriptor 17 for one scan line composed of span descriptors 120, 130, 160
0-j is the address B of the graphics command memory 3
It is assumed that the data is stored from j.

Thereafter, as shown in FIG. 16, the CPU 1 selects one of the two screen descriptors 31 and 32 prepared on the graphics command memory 3 (for example, the screen descriptor 31) to the j-th position. The line descriptor 170-j is added to the entry #j.
Address "Bj" and line descriptor 170-j
The number of span descriptors constituting the above is set to "3" (S24).

Thereafter, the CPU 1 increments k by 1 and sets the next scan line SL (j + 1) as the processing target (S25),
The same processing as described above is performed.

Then, all the scan lines SL1 to S
When the same processing as described above is performed on Ln (YES in S26), the bitmap information necessary for displaying the screen defined by the line descriptor stored in the graphics command memory 3 this time is displayed. It is stored in the command memory 3 (S27). this time,
Since the necessary bitmap information is the bitmap information of the background screen 61 and the bitmap information of the graphic element 63, they are stored in the addresses A1 and F1 of the graphics command memory 3 as shown in FIG. 16 (S2).
7). In the next frame, the CPU 1 stores the bitmap information of the background screen 61 and the graphic element 63 at the addresses A2 and F2 of the graphics command memory 3.

The CPU 1 repeats the above processing.

While the CPU 1 is performing the above processing,
The graphics controller 4 performs the following processing.

The DMA controller 42 refers to the register 41 every time the frame is switched, reads the contents of the screen descriptor indicated by the above address from the graphics command memory 3 in accordance with the address of the screen descriptor set therein, and It is stored in the descriptor FIFO 43. Now, assuming that the address “C” of the screen descriptor 31 shown in FIG. 16 is set in the register 41, the DMA controller 42 determines the contents of the entries # 1 to #n of the screen descriptor 31 according to the address “C”. For each entry, and sequentially read the contents of the screen descriptor FIFO4
Store in 3.

The DMA controller 44 reads the contents of the screen descriptor 31 stored in the screen descriptor FIFO 43 one entry at a time,
Each scan line SL1 to SL according to the read contents
The line descriptor corresponding to n is read from the graphics command memory 3 and the line descriptor F
Store in IFO45.

For example, the screen descriptor FIF
Screen descriptor 31 shown in FIG. 16 from O43
If the contents of the j-th entry #j of
Since the line descriptor 170-j corresponding to the scan line SLj is stored at the address Bj of the graphics command memory 3 and the number of span descriptors forming the line descriptor 170-j is "3", the DMA can be known. Controller 4
4 is the address Bj of the graphics command memory 3
To three span descriptors 120, 130, 16
Line descriptor 170 composed of 0s
-J is read, and the read line descriptor 17
0-j is stored in the line descriptor FIFO 45.

The decoder 46 reads line descriptors one scan line at a time from the line descriptor FIFO 45 in synchronization with the display period of one scan line. Then, the span descriptors forming the line descriptors for the read one scan line are sequentially analyzed in the order of reading, and the DMA controller 47, the transparent color processing unit 49, and the alpha blending unit 5 are analyzed according to the analysis result.
0, the filter 56 is controlled.

Now, for example, the line descriptor FIF
As a line descriptor for one scan line from O45, the line descriptor 170-j shown in FIG.
, The decoder 46 performs the following processing.

The decoder 46 uses the line descriptor 1
Three span descriptors 12 forming 70-j
0, 130, 160 to the span descriptor 120,
Read in the order of 130 and 160.

When the span descriptors 120 and 130 have been read, the span descriptors 120 and 130 are read.
Since the contents of the above are shown in FIG. 11, the decoder 4
6, the DMA controller 47,
The transparent color processing blend 49, the alpha blending unit 50, and the filter 56 are performed. The DMA controller 47, the transparent color processing blend 49, the alpha blending unit 50, and the filter 56 that received this instruction also perform the same processing as described above.

When the span descriptor 160 is read, the contents are as shown in FIG.
The decoder 46 performs the following processing.

With respect to the DMA controller 47, since the color designation flag 164a is turned off, the span from the address Fj of the graphics command memory 3 to the span based on the information set in the source address 161 and the span width 163. The bitmap information read from the graphics command memory 3 is instructed based on the information set in the arrangement position 162, while instructing to read the bitmap information for the number of pixels corresponding to the width (X5-X3 + 1). 1 incorporated from the portion corresponding to the arrangement position X3 in the bitmap information for one scan line
Bit map information for scan line is set to pixel FIF
Instruct to store in O48.

Since the transparent color flag 164c is turned on, the transparent color processing section 49 is instructed to perform the transparent color processing.

Since the alpha value 164b is 100%, the alpha blend unit 50 is instructed to set the alpha value at the time of alpha blending to 100%. Further, since the arrangement position 162 and the span width 163 are respectively X3, X5-X3 + 1, the span width (X is calculated from the bitmap information of the pixel corresponding to the arrangement position X3 in the bitmap information for one scan line.
5-X3 + 1) is instructed to perform alpha blending only for the bitmap information corresponding to the number of pixels.

For the filter 56, the filter flag 9
Since 4b is off, it is instructed not to perform the filtering process.

Upon receiving the above instruction from the decoder 46, the DMA controller 47, the transparent color processing section 49, the alpha blending section 50, and the filter 56 perform the following processing.

The DMA controller 47 receives the span width (X
5-X3 + 1), the bit map information corresponding to the number of pixels is read, and the read bit map information is incorporated from the portion corresponding to the arrangement position X3 in the bit map information for one scan line, as shown in FIG. Bitmap information 180 for one scan line is set to pixel F
Store in IFO48. Incidentally, in FIG.
Indicates the bitmap information of the graphic element 63 read from the graphics command memory 3.

Since the transparent color processing section 49 is instructed to perform the transparent color processing by the decoder 46, the bitmap information 180 for one scan line shown in FIG.
1 to the target color for transparent color processing (blue in this example)
Read.

Next, the transparent color processing section 49 causes the register 4
The transparent color processing target color (blue) read from 1 is compared with the color of each pixel indicated by the bitmap information 180 for one scan line, and the pixel whose display color is "blue" is obtained. After that, the transparent color processing unit 49 sets the alpha value of the pixel thus obtained to the one corresponding to the transparent color (0
%) Is instructed to the alpha blending unit 50, and the bitmap information 180 is passed to the alpha blending unit 50. Now, for example, bitmap information 180
If the bitmap information for displaying "blue" is stored in the portion 182 in the inside, the transparent color processing unit 49
Will instruct the alpha blending section 50 to set the alpha value of the pixel corresponding to the portion 182 to the alpha value (0%) corresponding to transparency.

The alpha blend unit 50 includes a selector 51.
Bit map information 184 (bit map information of the background screen 61 and bitmap information of the graphic element 62) for one scan line shown in FIG. (Information), and the bitmap information 184 for one scan line read and the bitmap information 18 for one scan line passed from the transparent color processing unit 49.
Of 0 (bitmap information of graphic element 63), from X3 to X5, the remaining part excluding the part 182 is alpha-blended with an alpha value of 100%, and the part 182 is alpha-blended with an alpha value of 0%. The blended bitmap information 185 for one scan line is stored in the line buffer 52 again.

Since the filter 56 is instructed not to perform the filter processing, the bit map information is read from the line buffer 53 selected by the selector 54, and the display device 5 is synchronized with the dot clock of the display device 5. Transfer the bitmap information to.

[0141]

As described above, according to the present invention,
A line descriptor, which is a graphics command created by the CPU, indicates the position on the scan line of the span of the graphic element to be arranged on the scan line,
The span descriptor for each graphic element is simply arranged according to the stacking order from the back to the front when the graphic element is displayed.
In order to divide the display screen into tiles, there is no need to perform complicated processing such as calculating the overlapping parts of graphic elements,
The line descriptor, which is a graphics command, can be created only by performing a simple process of arranging the span descriptors according to the superposition order of the graphic elements, so that the load on the CPU can be reduced.

Further, according to the present invention, one scan stored in the line buffer for writing by the line buffer controller among the first and second line buffers according to the alpha value included in the span descriptor. Since it has an alpha blending unit that performs alpha blending of the bitmap information for one line and the bitmap information for one scan line indicated by the storage address included in the span descriptor,
Alpha blending can be performed between overlapping graphic elements.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a graphics command created by the CPU 1.

FIG. 3 is a diagram for explaining a span.

FIG. 4 is a diagram showing a configuration example of an extension instruction.

FIG. 5 is a block diagram showing a configuration example of a graphics controller 4.

FIG. 6 is a diagram showing an example of a screen displayed on the display device 5.

FIG. 7 is a flowchart showing a processing example of the CPU 1.

FIG. 8 is a flowchart showing a processing example of the CPU 1.

FIG. 9 is a diagram showing an example of the contents of a span descriptor.

FIG. 10 is a diagram showing an example of contents of a graphics command memory 3.

FIG. 11 is a diagram showing an example of the contents of a span descriptor.

FIG. 12 is a diagram showing an example of the contents of a graphics command memory 3.

FIG. 13 is a diagram showing bitmap information for one scan line stored in the pixel FIFO 48 by the DMA controller 47 when a color is designated by the user.

FIG. 14 is a diagram for explaining the processing content of an alpha blending unit 50.

FIG. 15 is a diagram showing an example of the contents of a span descriptor.

16 is a diagram showing an example of the contents of a graphics command memory 3. FIG.

FIG. 17 is a diagram for explaining processing contents of a transparent color processing unit 49.

FIG. 18 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 1 ... CPU 2 ... System memory 3 ... Graphics command memory 4 ... Graphics controller 5 ... Display device 6 ... CPU bus 21-1 to 21-n ... Line descriptor 22 ... Screen descriptor 23 ... Span descriptor 24 ... Source address 25 ... Arrangement position 26 ... Span width 27 ... Extended command 27a ... Color designation flag 27b ... Alpha value 27c ... Transparent color flag 27d ... Filter flag 41 ... Register 42 ... DMA controller 43 ... Screen descriptor FIFO 44 ... DMA controller 45 ... Line descriptor FIFO 46 Decoder 47 DMA controller 48 Pixel FIFO 49 Transparent color processing unit 50 Alpha blending unit 51 Selectors 52, 53 Line buffer 54 Kuta 55 ... line buffer controller 56 ... filter 57 ... memory controller

Claims (4)

[Claims] 1. A graphics display device for displaying a graphic element on a display device, a graphics command memory, a position on a scan line of a span of a graphic element to be displayed on a scan line, and a corresponding bit map. A line descriptor is created for each scan line of the display device by creating a line descriptor in which the span descriptor for each graphic element including the storage address of information is arranged in order from the largest depth of the graphic element displayed on the scan line. A graph comprising: a CPU for storing descriptors in the graphics command memory; and a graphics controller for displaying graphic elements on the display device based on the line descriptors stored in the graphics command memory. Six display device. 2. The graphics display device according to claim 1, wherein the span is formed by dividing a graphic element into scan line units of the display device. 3. The graphics controller includes line descriptor reading means for reading a line descriptor corresponding to each scan line stored in the graphics command memory, and bit map information for one scan line. First and second line buffers, and the first and second line buffers in synchronization with the display period of one scan line
Line buffer controller for switching one of the line buffers from write to display and the other line buffer from display to write, and 1 read by the line descriptor reading means.
The span descriptors forming the line descriptors for the scan lines are used in order from the largest depth, and the bitmap information indicated by the storage address included in the span descriptor is used for the first and second line buffers. Bitmap information storage means for storing in a portion of the line buffer for writing by the line buffer controller, which corresponds to an arrangement position included in the bitmap information, An output unit for outputting the bit map information for one scan line stored in the line buffer for display by the line buffer controller to the display device, among the line buffers. Item 2. A graphics display device according to item 2. 4. The span descriptor includes an alpha value at the time of performing alpha blending, and the bitmap information storage means stores the first and second values according to the alpha value included in the span descriptor.
1 scan line bit map information stored in the line buffer for writing by the line buffer controller, and 1 scan line indicated by the storage address included in the span descriptor. 4. The graphics display device according to claim 3, further comprising an alpha blending unit for performing an alpha blending with the bitmap information of.