JPH0682802A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH0682802A
JPH0682802A JP23107692A JP23107692A JPH0682802A JP H0682802 A JPH0682802 A JP H0682802A JP 23107692 A JP23107692 A JP 23107692A JP 23107692 A JP23107692 A JP 23107692A JP H0682802 A JPH0682802 A JP H0682802A
Authority
JP
Japan
Prior art keywords
semiconductor chip
glass substrate
transparent glass
liquid crystal
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23107692A
Other languages
Japanese (ja)
Inventor
Masafumi Enomoto
雅文 榎本
Toshio Futami
利男 二見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Consumer Electronics Co Ltd
Japan Display Inc
Original Assignee
Hitachi Device Engineering Co Ltd
Hitachi Ltd
Hitachi Consumer Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Device Engineering Co Ltd, Hitachi Ltd, Hitachi Consumer Electronics Co Ltd filed Critical Hitachi Device Engineering Co Ltd
Priority to JP23107692A priority Critical patent/JPH0682802A/en
Publication of JPH0682802A publication Critical patent/JPH0682802A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To inspect an electric connection state right after a semiconductor chip is mounted by providing patterns for connection resistance measurement which are mutually connected on the top surface of a transparent glass substrate and the reverse surface of the semiconductor chip. CONSTITUTION:Two electrodes 2a and a pattern 2 for connection resistance measurement which connects them are provided at each of the four corner parts on the reverse surface of the semiconductor chip 4 separately from an electrode 9 for connection, and an electrode 1a which is connected to the electrode 2a of the semiconductor chip 4, a pattern 1 for connection resistance measurement which is connected thereto, and an electrode 1b at its end part are provided on the top surface of the lower transparent glass substrate 3 at the positions corresponding to the electrodes and patterns. The probe of a resistance measuring instrument is applied to two adjacent electrodes (terminal) 1b of the lower transparent glass substrate 3 positioned nearby each corner part of the mounted semiconductor chip 4 and the connection resistance is measured. When the resistance value is larger than a specific value, the semiconductor chip 4 is defective, so it is removed and a new chip is mounted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶表示素子の透明ガ
ラス基板の電極上に、液晶駆動用半導体チップを直接実
装したCOG(チップ オン グラス(Chip On G
lass))方式の液晶表示装置に係り、特に、該半導
体チップの実装直後、その電気的接続状態を確認するこ
とができる技術に関する。
BACKGROUND OF THE INVENTION The present invention relates to a COG (Chip On Glass (Chip On Glass) in which a liquid crystal driving semiconductor chip is directly mounted on an electrode of a transparent glass substrate of a liquid crystal display element.
lass)) type liquid crystal display device, and more particularly to a technique capable of confirming an electrical connection state of the semiconductor chip immediately after mounting.

【0002】[0002]

【従来の技術】COG方式の液晶表示装置は、透明導電
膜からなる電極と配向膜等を積層した面がそれぞれ対向
するように所定の間隔を隔てて上部透明ガラス基板と下
部透明ガラス基板とを重ね合わせ、該両基板間の縁周囲
に設けたシール材により、両基板を貼り合わせるととも
に両基板間に液晶を封止し、さらに両基板の外側に偏光
板を貼り付けてなる液晶表示素子を有し、上部透明ガラ
ス基板が重ね合わされていない該上部透明ガラス基板周
囲の駆動配線が形成された下部透明ガラス基板上に複数
個の液晶駆動用半導体チップが直接実装されている。半
導体チップと下部透明ガラス基板とは、対向する半導体
チップの下面と下部透明ガラス基板面のいずれか一方に
形成された突起電極(バンプ)を介して電気的に接続さ
れている。このような接続方式をフェースダウン方式と
いう。
2. Description of the Related Art In a COG type liquid crystal display device, an upper transparent glass substrate and a lower transparent glass substrate are separated by a predetermined distance so that the surfaces on which electrodes made of a transparent conductive film and an alignment film are laminated face each other. A liquid crystal display element is obtained by stacking and sealing the liquid crystal between both substrates by bonding both substrates with a sealing material provided around the edge between the both substrates, and further bonding a polarizing plate on the outside of both substrates. A plurality of liquid crystal driving semiconductor chips are directly mounted on the lower transparent glass substrate having the drive wiring around the upper transparent glass substrate, which is not overlapped with the upper transparent glass substrate. The semiconductor chip and the lower transparent glass substrate are electrically connected to each other via a protruding electrode (bump) formed on one of the lower surface of the semiconductor chip and the surface of the lower transparent glass substrate which face each other. Such a connection method is called a face-down method.

【0003】このような技術は、例えば特開昭52−3
5548号公報や特開平3−18826号公報等に記載
されている。
Such a technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 52-3.
It is described in JP-A-5548, JP-A-3-18826 and the like.

【0004】[0004]

【発明が解決しようとする課題】従来の技術において
は、透明ガラス基板の電極上に半導体チップを実装した
あとの該半導体チップの電気的接続状態の確認について
配慮されていなかった。すなわち、半導体チップ実装直
後の電気的接続状態の検査はできず、液晶表示装置の製
品が完成したあとの点燈検査によらなければ、半導体チ
ップが正常に接続されたかどうかは判断することができ
ず、半導体チップの接続不良を発見することができない
という問題があった。
In the prior art, no consideration was given to the confirmation of the electrical connection state of the semiconductor chip after mounting the semiconductor chip on the electrodes of the transparent glass substrate. That is, it is not possible to inspect the electrical connection state immediately after the semiconductor chip is mounted, and it is possible to determine whether the semiconductor chip is normally connected without a lighting inspection after the product of the liquid crystal display device is completed. Therefore, there is a problem in that it is impossible to find a defective connection of the semiconductor chip.

【0005】本発明の目的は、半導体チップ実装直後に
電気的接続状態を検査することができ、接続信頼性の高
い液晶表示装置を提供することにある。
An object of the present invention is to provide a liquid crystal display device capable of inspecting an electrical connection state immediately after mounting a semiconductor chip and having high connection reliability.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、透明ガラス基板の上面および半導体チッ
プの下面に、実装された半導体チップの電極と透明ガラ
ス基板の電極との電気的接続状態を検査するために、半
導体チップを実装すると互いに接続される接続抵抗測定
用パターンをそれぞれ設けた液晶表示装置を提供する。
In order to achieve the above object, the present invention provides an electrical connection between an electrode of a semiconductor chip and an electrode of a transparent glass substrate mounted on the upper surface of a transparent glass substrate and the lower surface of a semiconductor chip. Provided is a liquid crystal display device provided with connection resistance measurement patterns, which are connected to each other when a semiconductor chip is mounted, for inspecting a connection state.

【0007】[0007]

【作用】本発明では、半導体チップの実装直後、接続抵
抗測定用パターンの接続抵抗を測定し、その接続抵抗の
大小により、半導体チップの電極と透明ガラス基板の電
極との電気的接続状態を検査、判断することができる。
抵抗値が所定の値より大きい接続不良の半導体チップを
取り除いたあと、半導体チップを再実装することによ
り、すべての半導体チップが正常に接続された接続信頼
性の高い液晶表示装置を提供することができる。
In the present invention, the connection resistance of the connection resistance measuring pattern is measured immediately after the semiconductor chip is mounted, and the electrical connection state between the electrode of the semiconductor chip and the electrode of the transparent glass substrate is inspected according to the magnitude of the connection resistance. , You can judge.
It is possible to provide a liquid crystal display device with high connection reliability in which all semiconductor chips are normally connected by removing a semiconductor chip with a connection failure having a resistance value larger than a predetermined value and then re-mounting the semiconductor chips. it can.

【0008】[0008]

【実施例】図3は、COG方式の液晶表示装置の一実施
例の分解斜視図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is an exploded perspective view of an embodiment of a COG type liquid crystal display device.

【0009】13は金属製の上シールドケース、14は
上シールドケース13に一体に形成された固定用爪、1
5はゴム等から成る各部品固定用スペーサ、5は液晶表
示素子、6は液晶表示素子5を構成する上部透明ガラス
基板、3は液晶表示素子5を構成する下部透明ガラス基
板である。下部透明ガラス基板3上には上部透明ガラス
基板6が重ねられ、両基板間にはここでは図示しない液
晶が両基板の縁周囲に設けられたシール材により封止さ
れている。下部透明ガラス基板3は図示のように上部透
明ガラス基板6より外周が大きく、上部透明ガラス基板
6の4辺の外周部が液晶表示素子5の駆動配線形成用領
域となる。4は液晶駆動用半導体チップ、7は下部透明
ガラス基板3の外周部上に形成された半導体チップ4の
駆動用入力配線パターン、8は下部透明ガラス基板3の
外周部上に形成された駆動用出力配線パターン、16
a、16b、16c、16dはそれぞれ駆動回路を有
し、下部透明ガラス基板3の4辺の周囲に接続されるF
PC(フレキシブル プリンティド サーキット)、17
は金属製の下シールドケース、18は下シールドケース
17に設けられ、上シールドケース13の固定用爪14
が挿入され、かしめられる固定用穴である。
Reference numeral 13 denotes a metallic upper shield case, 14 denotes a fixing claw integrally formed with the upper shield case 13, and 1
Reference numeral 5 is a spacer for fixing each component made of rubber or the like, 5 is a liquid crystal display element, 6 is an upper transparent glass substrate which constitutes the liquid crystal display element 5, and 3 is a lower transparent glass substrate which constitutes the liquid crystal display element 5. An upper transparent glass substrate 6 is superposed on the lower transparent glass substrate 3, and a liquid crystal (not shown here) is sealed between the two substrates by a sealing material provided around the edges of both substrates. The lower transparent glass substrate 3 has a larger outer circumference than the upper transparent glass substrate 6 as shown in the drawing, and the outer peripheral portions of the four sides of the upper transparent glass substrate 6 are drive wiring formation regions of the liquid crystal display element 5. Reference numeral 4 is a liquid crystal driving semiconductor chip, 7 is a driving input wiring pattern for the semiconductor chip 4 formed on the outer peripheral portion of the lower transparent glass substrate 3, and 8 is a driving input wiring pattern formed on the outer peripheral portion of the lower transparent glass substrate 3. Output wiring pattern, 16
Each of a, 16b, 16c, and 16d has a driving circuit, and is connected to the periphery of the four sides of the lower transparent glass substrate 3 F
PC (Flexible Printed Circuit), 17
Is a metal lower shield case, 18 is provided in the lower shield case 17, and fixing claws 14 of the upper shield case 13 are provided.
Is a fixing hole into which is inserted and caulked.

【0010】図1(a)は、本発明の一実施例の液晶表
示装置の液晶表示素子の要部平面図であり、下部透明ガ
ラス基板面上に設けた接続抵抗測定用パターンを示す図
である。
FIG. 1A is a plan view of a main part of a liquid crystal display element of a liquid crystal display device according to an embodiment of the present invention, showing a connection resistance measuring pattern provided on a lower transparent glass substrate surface. is there.

【0011】一方、図1(b)は、図1(a)に示す下
部透明ガラス基板上に実装する液晶駆動用半導体チップ
の下面の平面図であり、該半導体チップの下面に設けた
接続抵抗測定用パターンを示す図である。
On the other hand, FIG. 1 (b) is a plan view of the lower surface of the liquid crystal driving semiconductor chip mounted on the lower transparent glass substrate shown in FIG. 1 (a), showing the connection resistance provided on the lower surface of the semiconductor chip. It is a figure which shows the pattern for a measurement.

【0012】また、図2(a)は、図1(b)に示した
半導体チップを、図1(a)に示した下部透明ガラス基
板上に実装した状態を示す要部平面図である。図2
(b)は、図2(a)のA−A′切断線における断面図
である。
FIG. 2 (a) is a plan view of relevant parts showing a state in which the semiconductor chip shown in FIG. 1 (b) is mounted on the lower transparent glass substrate shown in FIG. 1 (a). Figure 2
2B is a sectional view taken along the line AA ′ in FIG.

【0013】図1(a)において、5は液晶表示素子、
6は上部透明ガラス基板、3は下部透明ガラス基板、7
は半導体チップ(ここでは図示せず)の駆動用入力配線
パターン、7aは駆動用入力配線パターン7の電極(外
部からの信号電圧、電源電圧の入力端子)、7bは半導
体チップの電極(図1(b)の突起電極(バンプ)9)
と接続される駆動用入力配線パターン7の電極(出力端
子)、8は駆動用出力配線パターン、8aは半導体チッ
プの電極(図1(b)の突起電極(バンプ)9)と接続
される駆動用出力配線パターン8の電極(入力端子)、
1は透明ガラス基板3の上面に形成された接続抵抗測定
用パターン、1aは接続抵抗測定用パターン1の電極で
ある。
In FIG. 1A, 5 is a liquid crystal display element,
6 is an upper transparent glass substrate, 3 is a lower transparent glass substrate, 7
Is a drive input wiring pattern of a semiconductor chip (not shown here), 7a is an electrode of the drive input wiring pattern 7 (input terminal for external signal voltage, power supply voltage), and 7b is an electrode of the semiconductor chip (FIG. 1). (B) protruding electrode (bump) 9)
An electrode (output terminal) of the drive input wiring pattern 7 connected to the drive electrode, 8 a drive output wiring pattern, and 8a a drive connected to the electrode of the semiconductor chip (protruding electrode (bump) 9 in FIG. 1B) Electrode (input terminal) of the output wiring pattern 8 for
Reference numeral 1 is a connection resistance measurement pattern formed on the upper surface of the transparent glass substrate 3, and 1a is an electrode of the connection resistance measurement pattern 1.

【0014】図1(b)において、4は液晶駆動用半導
体チップ、9は図1(a)の下部透明ガラス基板3の電
極7b、8aに対応して、半導体チップ4の下面に形成
された電極(突起電極(バンプ))、2は半導体チップ
4の下面に形成された接続抵抗測定用パターン、2aは
接続抵抗測定用パターン2の電極(電極9と同様の突起
電極)である。
In FIG. 1B, 4 is a liquid crystal driving semiconductor chip, and 9 is formed on the lower surface of the semiconductor chip 4 corresponding to the electrodes 7b and 8a of the lower transparent glass substrate 3 of FIG. 1A. Electrodes (protrusion electrodes (bumps)), 2 are connection resistance measurement patterns formed on the lower surface of the semiconductor chip 4, and 2a are electrodes of the connection resistance measurement pattern 2 (protrusion electrodes similar to the electrodes 9).

【0015】図2(b)において、10は半導体チップ
4と下部透明ガラス基板3との間に設けられ、図1
(a)、(b)に示す半導体チップ4の電極9、2aと
下部透明ガラス基板3の電極7b、8a、1aとをそれ
ぞれ接続し、電気的に導通させるための異方性導電接着
剤、11は上部透明ガラス基板6と下部透明ガラス基板
3との間に封入された液晶、12は上部透明ガラス基板
6と下部透明ガラス基板3との縁周囲に設けられ、両基
板を貼り合わせるとともに、両基板間に液晶11を封止
するシール材である。
In FIG. 2B, 10 is provided between the semiconductor chip 4 and the lower transparent glass substrate 3, and
An anisotropic conductive adhesive for connecting the electrodes 9 and 2a of the semiconductor chip 4 and the electrodes 7b, 8a and 1a of the lower transparent glass substrate 3 shown in FIGS. 11 is a liquid crystal sealed between the upper transparent glass substrate 6 and the lower transparent glass substrate 3, 12 is provided around the edge of the upper transparent glass substrate 6 and the lower transparent glass substrate 3, and both substrates are bonded together, It is a sealing material that seals the liquid crystal 11 between both substrates.

【0016】液晶駆動用半導体チップ4の下面に形成さ
れた各電極9は、液晶表示素子5の下部透明ガラス基板
3の上面に形成された各電極7b、8aと異方性導電接
着剤10を介して電気的に接続され、駆動用入力配線パ
ターン7から入力された信号電圧、電源電圧は半導体チ
ップ4を通って駆動用出力パターン8、液晶表示素子5
に出力される。従来は、半導体チップ4の電極9と下部
透明ガラス基板3の電極7b、8aとが電気的に良好に
接続されているかどうか判断することができなかった。
本実施例では、半導体チップ4の下面の4つのコーナー
部に、接続用の電極9とは別にそれぞれ2個の電極2a
およびこれらを導通させる接続抵抗測定用パターン2を
設け、かつ、下部透明ガラス基板3の上面にもこれらに
対応する位置に、半導体チップ4の電極2aと接続され
る電極1a、これに接続される接続抵抗測定用パターン
1、およびその端部に電極1bを設けた。
The electrodes 9 formed on the lower surface of the liquid crystal driving semiconductor chip 4 include the electrodes 7b and 8a formed on the upper surface of the lower transparent glass substrate 3 of the liquid crystal display element 5 and the anisotropic conductive adhesive 10. The signal voltage and the power supply voltage, which are electrically connected via the drive input wiring pattern 7, pass through the semiconductor chip 4 and the drive output pattern 8 and the liquid crystal display element 5.
Is output to. Conventionally, it has not been possible to judge whether the electrode 9 of the semiconductor chip 4 and the electrodes 7b and 8a of the lower transparent glass substrate 3 are electrically connected well.
In this embodiment, two electrodes 2a are provided on each of the four corners of the lower surface of the semiconductor chip 4 in addition to the connecting electrodes 9.
Also, a connection resistance measuring pattern 2 for conducting these is provided, and an electrode 1a connected to the electrode 2a of the semiconductor chip 4 is connected to the electrode 2a of the lower transparent glass substrate 3 at a position corresponding thereto. The connection resistance measuring pattern 1 and the electrode 1b were provided on the end portion thereof.

【0017】半導体チップ4の下部透明ガラス基板3上
への実装が完了したあと、下部透明ガラス基板3の電極
7b、8aと半導体チップ4の電極9との電気的接続状
態の検査を行なう。半導体チップ4が実装されると、半
導体チップ4の接続抵抗測定用パターン2と下部透明ガ
ラス基板3の接続抵抗測定用パターン1とは、半導体チ
ップ4の電極2aと下部透明ガラス基板3の電極1aを
介して導通する。したがって、実装された半導体チップ
4の各コーナー部近傍に位置する下部透明ガラス基板3
の隣接する2個の電極(端子)1bに、図示しない2本
の抵抗測定器のプローブを当て、接続抵抗を測定する。
抵抗値が所定の値より大きい場合、この半導体チップ4
の接続は不良なので、この半導体チップ4を取り除き、
半導体チップ4の再実装を行なう。再実装後、上記と同
様に再検査を行ない、電気的接続状態を確認する。半導
体チップ4のコーナー部に位置するダミーの電極1aと
2aとの電気的接続状態は、その内側に位置する正規の
接続用の電極7b、8aと9との電気的接続状態とほぼ
同等であるから、後者の電極どうしの電気的接続状態を
確認することができる。この結果、すべての半導体チッ
プ4を正常に接続することができ、接続信頼性の高い液
晶表示装置を提供することができる。また、本実施例に
よれば、所定の値より抵抗値が大きい半導体チップ4を
除去するので、半導体チップ4の接続抵抗を安定化させ
ることができる。さらに、半導体チップ4の実装直後に
限らず、その後、上記と同様に接続抵抗を測定すること
によって、修理すべき半導体チップ4を判別することも
できる。
After the semiconductor chip 4 is mounted on the lower transparent glass substrate 3, the electrical connection between the electrodes 7b and 8a of the lower transparent glass substrate 3 and the electrode 9 of the semiconductor chip 4 is inspected. When the semiconductor chip 4 is mounted, the connection resistance measuring pattern 2 of the semiconductor chip 4 and the connection resistance measuring pattern 1 of the lower transparent glass substrate 3 correspond to the electrode 2a of the semiconductor chip 4 and the electrode 1a of the lower transparent glass substrate 3. Conducts through. Therefore, the lower transparent glass substrate 3 located near each corner of the mounted semiconductor chip 4
The probes of two resistance measuring devices (not shown) are applied to the two adjacent electrodes (terminals) 1b of 1 to measure the connection resistance.
If the resistance value is larger than a predetermined value, this semiconductor chip 4
Since the connection of is bad, remove this semiconductor chip 4,
The semiconductor chip 4 is remounted. After remounting, reinspection is performed in the same manner as above, and the electrical connection state is confirmed. The electrical connection state of the dummy electrodes 1a and 2a located at the corners of the semiconductor chip 4 is almost the same as the electrical connection state of the regular connection electrodes 7b, 8a and 9 located inside thereof. From this, it is possible to confirm the electrical connection state of the latter electrodes. As a result, all the semiconductor chips 4 can be normally connected, and a liquid crystal display device with high connection reliability can be provided. Further, according to this embodiment, the semiconductor chip 4 having a resistance value larger than a predetermined value is removed, so that the connection resistance of the semiconductor chip 4 can be stabilized. Furthermore, the semiconductor chip 4 to be repaired can be determined not only immediately after mounting the semiconductor chip 4 but also by measuring the connection resistance in the same manner as described above.

【0018】以上本発明を実施例に基づいて具体的に説
明したが、本発明は上記実施例に限定されるものではな
く、その要旨を逸脱しない範囲において種々変更可能で
あることは勿論である。例えば、本発明は、単純マトリ
クス方式の液晶表示装置でもTFT(薄膜トランジス
タ)等をスイッチング素子に使用したアクティブ・マト
リクス方式の液晶表示装置にも適用することができる。
また、接続抵抗測定用パターン1、2およびその電極1
a、1b、2aの形状、位置等は上記実施例に示したも
のに限定されず、その他の形状、位置にしてもよいこと
は言うまでもない。
Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention. . For example, the present invention can be applied to both a simple matrix type liquid crystal display device and an active matrix type liquid crystal display device using a TFT (thin film transistor) or the like as a switching element.
Also, the connection resistance measurement patterns 1 and 2 and the electrode 1 thereof.
Needless to say, the shapes, positions, etc. of a, 1b, 2a are not limited to those shown in the above embodiment, and other shapes and positions may be used.

【0019】[0019]

【発明の効果】以上説明したように、本発明によれば、
液晶駆動用半導体チップの透明ガラス基板上への実装
後、半導体チップの電極と透明ガラス基板の電極との接
続状態を電気的に測定することができるので、接続不良
の半導体チップを検出し、排除することができる。その
結果、接続信頼性の高い液晶表示装置を提供することが
できる。
As described above, according to the present invention,
After mounting the LCD driving semiconductor chip on the transparent glass substrate, the connection state between the semiconductor chip electrode and the transparent glass substrate electrode can be electrically measured, so the defective semiconductor chip can be detected and eliminated. can do. As a result, a liquid crystal display device with high connection reliability can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は、本発明の一実施例の液晶表示装置の
液晶表示素子の要部平面図、(b)は、(a)の液晶表
示素子に実装される液晶駆動用半導体チップの下面の平
面図である。
1A is a plan view of a main part of a liquid crystal display element of a liquid crystal display device according to an embodiment of the present invention, and FIG. 1B is a semiconductor chip for driving a liquid crystal mounted on the liquid crystal display element of FIG. 2 is a plan view of the lower surface of FIG.

【図2】(a)は、図1(b)の半導体チップを、図1
(a)の下部透明ガラス基板上に実装した状態を示す要
部平面図、(b)は、(a)のA−A′線断面図であ
る。
FIG. 2A is a view showing the semiconductor chip of FIG.
FIG. 7A is a plan view of relevant parts showing a state of being mounted on the lower transparent glass substrate of FIG. 7A, and FIG. 9B is a sectional view taken along the line AA ′ of FIG.

【図3】COG方式の液晶表示装置の一実施例の分解斜
視図である。
FIG. 3 is an exploded perspective view of an embodiment of a COG type liquid crystal display device.

【符号の説明】[Explanation of symbols]

1、2…接続抵抗測定用パターン、1a、1b、2a…
電極、3…下部透明ガラス基板、4…液晶駆動用半導体
チップ、5…液晶表示素子、6…上部透明ガラス基板、
7…駆動用入力配線パターン、7a、7b、8a…電
極、8…駆動用出力配線パターン、9…電極(バンプ) 10…異方性導電接着剤、11…液晶、12…シール材 13…上シールドケース、14…固定用爪、15…固定
用スペーサ、16a、16b、16c、16d…FP
C、17…下シールドケース、18…固定用穴。
1, 2 ... Connection resistance measurement patterns 1a, 1b, 2a ...
Electrodes, 3 ... Lower transparent glass substrate, 4 ... Liquid crystal driving semiconductor chip, 5 ... Liquid crystal display element, 6 ... Upper transparent glass substrate,
7 ... Driving input wiring pattern, 7a, 7b, 8a ... Electrode, 8 ... Driving output wiring pattern, 9 ... Electrode (bump) 10 ... Anisotropic conductive adhesive, 11 ... Liquid crystal, 12 ... Sealing material 13 ... Top Shield case, 14 ... Fixing claw, 15 ... Fixing spacer, 16a, 16b, 16c, 16d ... FP
C, 17 ... Lower shield case, 18 ... Fixing hole.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】液晶表示素子の透明ガラス基板の電極上
に、液晶駆動用半導体チップを直接実装してなるCOG
方式の液晶表示装置において、上記透明ガラス基板の上
面および上記半導体チップの下面に、実装された上記半
導体チップの電極と上記透明ガラス基板の電極との電気
的接続状態を検査するために、上記半導体チップを実装
すると互いに接続される接続抵抗測定用パターンをそれ
ぞれ設けたことを特徴とする液晶表示装置。
1. A COG in which a liquid crystal driving semiconductor chip is directly mounted on an electrode of a transparent glass substrate of a liquid crystal display element.
In the liquid crystal display device of the method, in order to inspect the electrical connection state between the electrode of the semiconductor chip and the electrode of the transparent glass substrate mounted on the upper surface of the transparent glass substrate and the lower surface of the semiconductor chip, the semiconductor A liquid crystal display device, wherein each of the liquid crystal display devices is provided with a connection resistance measuring pattern which is connected to each other when the chip is mounted.
JP23107692A 1992-08-31 1992-08-31 Liquid crystal display device Pending JPH0682802A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23107692A JPH0682802A (en) 1992-08-31 1992-08-31 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23107692A JPH0682802A (en) 1992-08-31 1992-08-31 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH0682802A true JPH0682802A (en) 1994-03-25

Family

ID=16917915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23107692A Pending JPH0682802A (en) 1992-08-31 1992-08-31 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH0682802A (en)

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JP2002229053A (en) * 2001-01-31 2002-08-14 Matsushita Electric Ind Co Ltd Liquid crystal display module
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JP2008151892A (en) * 2006-12-15 2008-07-03 Oki Electric Ind Co Ltd Display driving circuit
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002229053A (en) * 2001-01-31 2002-08-14 Matsushita Electric Ind Co Ltd Liquid crystal display module
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JP2006038988A (en) * 2004-07-23 2006-02-09 Seiko Epson Corp Electrooptical apparatus, electronic device and mounting structural body
US7245143B2 (en) 2004-07-23 2007-07-17 Seiko Epson Corporation Electro-optical device, electronic apparatus, and mounting structure
JP2007004019A (en) * 2005-06-27 2007-01-11 Sanyo Epson Imaging Devices Corp Inspection method of electrooptical apparatus and manufacturing method of electrooptical apparatus
JP2008151892A (en) * 2006-12-15 2008-07-03 Oki Electric Ind Co Ltd Display driving circuit
JP2008241917A (en) * 2007-03-26 2008-10-09 Toshiba Matsushita Display Technology Co Ltd Liquid crystal display
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JP2010003986A (en) * 2008-06-23 2010-01-07 Toshiba Corp Semiconductor integrated circuit and semiconductor device
KR101491161B1 (en) * 2008-12-09 2015-02-06 엘지이노텍 주식회사 Method of testing for connection condition between display panel and driver ic and display device using the same
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JP2017181985A (en) * 2016-03-31 2017-10-05 株式会社ジャパンディスプレイ Display device
US10529744B2 (en) 2016-03-31 2020-01-07 Japan Display Inc. Display device
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