JPH06152192A - Mounting method for semiconductor chip - Google Patents

Mounting method for semiconductor chip

Info

Publication number
JPH06152192A
JPH06152192A JP4301458A JP30145892A JPH06152192A JP H06152192 A JPH06152192 A JP H06152192A JP 4301458 A JP4301458 A JP 4301458A JP 30145892 A JP30145892 A JP 30145892A JP H06152192 A JPH06152192 A JP H06152192A
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring film
lead
substrate
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4301458A
Other languages
Japanese (ja)
Inventor
Shinichi Kasahara
愼一 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4301458A priority Critical patent/JPH06152192A/en
Publication of JPH06152192A publication Critical patent/JPH06152192A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Supply And Installment Of Electrical Components (AREA)
  • Wire Bonding (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE:To make a semiconductor chip mounting equipment small-sized. CONSTITUTION:When a board 3 is bonded to the surface of a board 2, electrode terminals are formed on the surface of a protruding part of the board 2 which part protrudes from the board 3. When a semiconductor chip 5 to be connected with the electrode terminals is mounted, input leads 24 and output leads 23 are formed on a flexible wiring film 21. Inner end potions of the input leads 24 and the output leads 23 are connected with an I/O pad of the semiconductor chip 5. After the outer end portions of the output leads 23 are connected with the electrode terminals, the wiring film 21 is so bent that the section is U-shaped. Thereby the semiconductor chip 5 is positioned on the surface of the protruding part of the board 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体チップの実装方
法、特に、段付き基板の中段面に半導体チップを実装す
る方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor chip, and more particularly to a method for mounting a semiconductor chip on the middle surface of a stepped substrate.

【0002】例えば液晶表示装置において、一対のガラ
ス基板を重ね合わせた間隙に液晶を充填した表示パネル
は、一方のガラス基板より他方のガラス基板の一部が突
出し、ガラス基板の合わせ面かつ他方のガラス基板より
突出する部分に、駆動ICチップを実装または接続する
端子を形成するが、
For example, in a liquid crystal display device, in a display panel in which liquid crystal is filled in a gap formed by stacking a pair of glass substrates, part of the other glass substrate protrudes from one glass substrate, and the other surface of the glass substrate is aligned with the other. A terminal for mounting or connecting a driving IC chip is formed on a portion protruding from the glass substrate.

【0003】[0003]

【従来の技術】表示パネルに駆動用の半導体チップを接
続する主な方法として、COG(Chipon Glass) 技術を
利用して表示パネルに実装する方法と、TAB(Tape Au
tomatid Bonding)技術を利用して接続する方法がある。
2. Description of the Related Art As a main method of connecting a driving semiconductor chip to a display panel, a method of mounting on a display panel by using COG (Chipon Glass) technology and a method of mounting TAB (Tape Au
There is a method to connect using tomatid Bonding) technology.

【0004】図6は半導体チップをCOG実装した従来
の表示パネルの説明図、図7は半導体チップをTAB接
続した従来の表示パネルの説明図であり、液晶表示パネ
ル1および11は一対のガラス基板2,3をシール材4で
接合し、シール材4で囲われたガラス基板2と3の間隙
に液晶が充填され、ガラス基板3を接合したガラス基板
2の表面には駆動用半導体チップ5に接続する端子6が
形成されている。
FIG. 6 is an explanatory view of a conventional display panel in which semiconductor chips are mounted by COG, and FIG. 7 is an explanatory view of a conventional display panel in which semiconductor chips are connected by TAB. Liquid crystal display panels 1 and 11 are a pair of glass substrates. 2 and 3 are joined with a sealing material 4, liquid crystal is filled in a gap between the glass substrates 2 and 3 surrounded by the sealing material 4, and the driving semiconductor chip 5 is attached to the surface of the glass substrate 2 to which the glass substrate 3 is joined. A terminal 6 to be connected is formed.

【0005】図6において、表示パネル1のガラス基板
2の表面には、表示領域に連通し半導体チップ5の出力
パッド8に接続する端子6と、半導体チップ5の入力パ
ッド9に接続する端子7を形成し、出力パッド8と接続
端子6との電気的接続および入力パッド9と接続端子7
との電気的接続は、ガラス基板2と半導体チップ5との
間に充填した接着材10によって維持する。
In FIG. 6, on the surface of the glass substrate 2 of the display panel 1, a terminal 6 connected to the output pad 8 of the semiconductor chip 5 and a terminal 7 connected to the input pad 9 of the semiconductor chip 5 are connected to the display area. To form an electrical connection between the output pad 8 and the connection terminal 6 and the input pad 9 and the connection terminal 7.
The electrical connection with the is maintained by the adhesive 10 filled between the glass substrate 2 and the semiconductor chip 5.

【0006】図7において、一般にポリイミドにてなる
フレキシブル配線フィルム12には、半導体チップ5の出
力パッド8を接続するリード13と、半導体チップ5の入
力パッド9を接続するリード14を形成し、半導体チップ
5と配線フィルム12とを樹脂15で接着したのち、出力パ
ッド8を接続したリード13は、ガラス基板2の表面に形
成した端子6に接続させる。
In FIG. 7, a lead 13 for connecting the output pad 8 of the semiconductor chip 5 and a lead 14 for connecting the input pad 9 of the semiconductor chip 5 are formed on the flexible wiring film 12 generally made of polyimide. After bonding the chip 5 and the wiring film 12 with the resin 15, the lead 13 to which the output pad 8 is connected is connected to the terminal 6 formed on the surface of the glass substrate 2.

【0007】[0007]

【発明が解決しようとする課題】液晶表示パネルにおい
て、ガラス基板2に半導体チップ5をCOG方式で実装
する方法は、半導体チップ5を実装する領域と、その周
囲に例えば3mm幅程度の半導体チップ実装用導体パター
ン形成領域が、表示領域の延長上に必要であり、ガラス
基板2が大形になると共に、実装する半導体チップ5に
はリードが接続されてないため、実装前の電気的チェッ
クができないという問題点があった。
In the liquid crystal display panel, a method of mounting the semiconductor chip 5 on the glass substrate 2 by the COG method is a semiconductor chip mounting area of the semiconductor chip 5 and a semiconductor chip mounting around the area of, for example, about 3 mm. A conductive pattern forming area is required for extension of the display area, the glass substrate 2 becomes large in size, and the semiconductor chip 5 to be mounted has no leads connected to it, so electrical check before mounting cannot be performed. There was a problem.

【0008】他方、TAB技術を利用するためフレキシ
ブル配線フィルム12を使用し、実装前の電気的チェック
が可能な半導体チップ5の実装方法において、配線フィ
ルム12は表示パネル1の側方に突出し、装置の小型化の
ため配線フィルム12をコ字形に屈曲させてもその屈曲部
が表示パネルより突出するため、表示パネル収容筐体が
大きくなると共に、配線フィルム12に形成した出力リー
ドが微細ピッチであるため、そのリードを利用して搭載
半導体チップ5の電気的チェックができないという問題
点があった。
On the other hand, in the mounting method of the semiconductor chip 5 in which the flexible wiring film 12 is used to utilize the TAB technology and the electrical check can be performed before mounting, the wiring film 12 is projected to the side of the display panel 1, Even if the wiring film 12 is bent in a U-shape for downsizing, the bent portion protrudes from the display panel, so that the display panel housing is enlarged and the output leads formed on the wiring film 12 have a fine pitch. Therefore, there is a problem that the mounted semiconductor chip 5 cannot be electrically checked using the lead.

【0009】[0009]

【課題を解決するための手段】上記問題点の解決を目的
とする本発明方法は、その主要工程を示す図1によれ
ば、基板2の表面に基板3を接合したとき基板3より突
出する基板2の突出部の表面に電極端子を形成し、該電
極端子に接続する半導体チップ5を実装するに際し、フ
レキシブル配線フィルム21には半導体チップ5に接続す
る入力リード24と出力リード23とを形成し、入出力リー
ド23,24 の内端部を半導体チップ5の入出力パッドに接
続し、出力リード23の外端部を該電極端子に接続したの
ち配線フィルム21を断面コ字形に折り曲げし、半導体チ
ップ5が基板2の突出部の表面上に位置するように構成
する。
According to the method of the present invention for solving the above-mentioned problems, according to FIG. 1 showing the main steps, when the substrate 3 is bonded to the surface of the substrate 2, it projects from the substrate 3. When an electrode terminal is formed on the surface of the protruding portion of the substrate 2 and the semiconductor chip 5 connected to the electrode terminal is mounted, an input lead 24 and an output lead 23 connected to the semiconductor chip 5 are formed on the flexible wiring film 21. Then, the inner ends of the input / output leads 23, 24 are connected to the input / output pads of the semiconductor chip 5, the outer ends of the output leads 23 are connected to the electrode terminals, and then the wiring film 21 is bent into a U-shaped cross section. The semiconductor chip 5 is arranged on the surface of the protruding portion of the substrate 2.

【0010】さらに配線フィルム21には、その入出力リ
ードに接続する試験用端子を設けることで、搭載半導体
チップ5の電気試験が可能とし、そのような端子は電気
試験終了後に切り離すことで、配線フィルム21を基板3
に接続する際の障害物にならないようにする。
Further, the wiring film 21 is provided with a test terminal to be connected to the input / output lead thereof, so that the mounted semiconductor chip 5 can be electrically tested. By disconnecting such a terminal after the electrical test is completed, wiring is performed. Film 21 on substrate 3
Do not become an obstacle when connecting to.

【0011】[0011]

【作用】上記手段によれば、半導体チップ5を搭載した
配線フィルム21を折り曲げし、基板2と3との段差部に
半導体チップ5を収容する構成である。
According to the above means, the wiring film 21 on which the semiconductor chip 5 is mounted is bent and the semiconductor chip 5 is housed in the step portion between the substrates 2 and 3.

【0012】従来の液晶表示装置において、表示パネル
のかかる段差部は単なる空域となっており、本発明方法
ではその空域に半導体チップ5を収容することなる。従
って、基板3に対する基板2の突出量は配線フィルム21
の接続に必要な寸法(例えば5mm程度) または半導体チ
ップ5の厚さ程度で済むようになり、その値は従来方法
で配線フィルムを使用する実装方法のそれと同等または
同等以下になる。
In the conventional liquid crystal display device, the stepped portion of the display panel is simply an empty area, and the semiconductor chip 5 is accommodated in the empty area in the method of the present invention. Therefore, the protrusion amount of the substrate 2 with respect to the substrate 3 depends on the wiring film 21.
The size required for connection (for example, about 5 mm) or the thickness of the semiconductor chip 5 is sufficient, and the value is equal to or less than that of the mounting method using the wiring film in the conventional method.

【0013】そのため、半導体チップ5をCOG方式で
実装するものより基板2は小さくなり、配線フィルムを
使用した従来のものに比べたとき半導体チップ5が基板
2より突出しないため、液晶表示パネルを収容する筐体
の小型化を可能にする。
Therefore, the substrate 2 is smaller than that in which the semiconductor chip 5 is mounted by the COG method, and the semiconductor chip 5 does not protrude from the substrate 2 as compared with the conventional one using the wiring film, and thus the liquid crystal display panel is accommodated. It enables downsizing of the housing.

【0014】[0014]

【実施例】図1は本発明による半導体チップ実装方法の
主要工程図、図2は本発明方法に係わる半導体チップ搭
載用の第1の配線フィルムの説明図、図3は本発明方法
に係わる半導体チップ搭載用の第2の配線フィルムの説
明図、図4は本発明方法に係わる半導体チップ搭載用の
第3の配線フィルムの説明図、図5は本発明方法に係わ
る半導体チップ搭載用の第4の配線フィルムの説明図で
ある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a main process diagram of a semiconductor chip mounting method according to the present invention, FIG. 2 is an explanatory view of a first wiring film for mounting a semiconductor chip according to the present invention method, and FIG. 3 is a semiconductor according to the present invention method. FIG. 4 is an explanatory view of a second wiring film for mounting a chip, FIG. 4 is an explanatory view of a third wiring film for mounting a semiconductor chip according to the method of the present invention, and FIG. 5 is a fourth drawing for mounting a semiconductor chip according to the method of the present invention. It is explanatory drawing of the wiring film of.

【0015】図1(イ) において、半導体チップ5は入出
力リードを形成したフレキシブル配線フィルム21に搭載
したのち、図1(ロ) に示す如く、ガラス基板2に配線フ
ィルム21を接続する。
In FIG. 1 (a), the semiconductor chip 5 is mounted on a flexible wiring film 21 having input / output leads formed thereon, and then the wiring film 21 is connected to the glass substrate 2 as shown in FIG. 1 (b).

【0016】次いで、図1(ハ) に示す如く、半導体チッ
プ5を包み込むように配線フィルム21を曲げ、その先端
部を接着剤または粘着テープ22にてガラス基板3の上面
に接着する。なお、図中の符号23は半導体チップ5の出
力パッドに接続するリード、24は半導体チップ5の入力
パッドに接続するリード、25は共通のリード24を接続す
るリード、26は半導体チップ5の側面を配線フィルム21
に接着する接着剤である。
Next, as shown in FIG. 1C, the wiring film 21 is bent so as to enclose the semiconductor chip 5, and the tip end thereof is adhered to the upper surface of the glass substrate 3 with an adhesive or an adhesive tape 22. In the figure, reference numeral 23 is a lead connected to the output pad of the semiconductor chip 5, 24 is a lead connected to the input pad of the semiconductor chip 5, 25 is a lead for connecting a common lead 24, and 26 is a side surface of the semiconductor chip 5. Wiring film 21
It is an adhesive that adheres to.

【0017】図1(ニ) において、27は例えばばね性金属
板にてなる断面コ字形フレームであり、半導体チップ5
と配線フィルム21およびそれらの接続部を保護するフレ
ーム27は、それ自体が有するばね弾性により、表示装置
1の端部に挟着するようになる。
In FIG. 1D, 27 is a U-shaped cross-section frame made of, for example, a spring metal plate.
The frame 27 that protects the wiring film 21 and the connecting portions thereof is clamped to the end portion of the display device 1 by the spring elasticity of itself.

【0018】一般に、ガラス基板3の厚さtは1.1mm程
度であり、配線フィルム21を接続するためガラス基板2
がガラス基板3より突出する量aは2〜3mm程度であ
る。そこで、半導体チップ5として幅wが1mm程度 (そ
の時の高さhは0.5mm程度になる) のものを使用する
と、半導体チップ5は、ガラス基板2と3の段差で構成
する断面角形の領域内に収まり、ガラス基板2の端面お
よびガラス基板3の上面より出っ張らないようになる。
Generally, the thickness t of the glass substrate 3 is about 1.1 mm, and the glass substrate 2 is used for connecting the wiring film 21.
The amount a protruding from the glass substrate 3 is about 2 to 3 mm. Therefore, when the semiconductor chip 5 having a width w of about 1 mm (the height h at that time is about 0.5 mm) is used, the semiconductor chip 5 has a rectangular cross-sectional area formed by the steps between the glass substrates 2 and 3. It does not protrude beyond the end surface of the glass substrate 2 and the upper surface of the glass substrate 3 within the inside.

【0019】図2において、(イ) は平面図,(ロ) は短手
方向の側面図であり、図1の配線フィルム21に相当する
配線フィルム31の表面には、半導体チップ5の出力パッ
ドを接続する複数本の出力リード32と、半導体チップ5
の入力パッドを接続する複数本の入力リード33とを形成
する。
In FIG. 2, (a) is a plan view and (b) is a lateral side view. The surface of a wiring film 31 corresponding to the wiring film 21 of FIG. A plurality of output leads 32 for connecting to the semiconductor chip 5
And a plurality of input leads 33 for connecting the input pads of.

【0020】リード32と33の内端部は、配線フィルム31
に明けた角形透孔34の内側に突出し、半導体チップ5の
出力パッドまたは入力パッドを圧着するようになる。配
線フィルム31の裏面には、一端がビヤホール35を介して
リード32に接続し他端がガラス基板2の電極端子に他端
が接続するようになるリード23と、ビヤホール36を介し
て中間部にリード33が接続し一端が駆動回路装置に接続
するリード25を形成する。
The inner ends of the leads 32 and 33 are connected to the wiring film 31.
Then, it projects into the inside of the square through hole 34 that has been opened, and the output pad or the input pad of the semiconductor chip 5 is pressure bonded. On the back surface of the wiring film 31, one end is connected to the lead 32 through the via hole 35, and the other end is connected to the electrode terminal of the glass substrate 2 at the other end. The lead 33 is connected and one end of the lead 25 is connected to the drive circuit device.

【0021】かかる配線フィルム31は、半導体チップ5
を搭載し、リード32を液晶表示パネル1の電極端子に接
続したのち、配線フィルム21と同様に半導体チップ5
を、ガラス基板2の端面およびガラス基板3の上面より
出っ張ることなく収容可能にする。
The wiring film 31 is used for the semiconductor chip 5
After mounting the lead 32 and connecting the lead 32 to the electrode terminal of the liquid crystal display panel 1, the semiconductor chip 5 is formed in the same manner as the wiring film 21.
Can be accommodated without protruding from the end surface of the glass substrate 2 and the upper surface of the glass substrate 3.

【0022】図3において、(イ) は平面図,(ロ) は短手
方向の側面図であり、図1の配線フィルム21に相当する
配線フィルム41の表面には、半導体チップ5の出力パッ
ドを接続する複数本の出力リード32と、半導体チップ5
の入力パッドを接続する複数本の入力リード33とを形成
し、リード32と33の内端部には半導体チップ5の入出力
パッドを接続する端子42および43を形成する。
In FIG. 3, (a) is a plan view, (b) is a lateral side view, and the surface of the wiring film 41 corresponding to the wiring film 21 of FIG. A plurality of output leads 32 for connecting to the semiconductor chip 5
A plurality of input leads 33 for connecting the input pads are formed, and terminals 42 and 43 for connecting the input / output pads of the semiconductor chip 5 are formed on the inner ends of the leads 32 and 33.

【0023】配線フィルム41の裏面には、一端がビヤホ
ール35を介してリード32に接続し他端がガラス基板2の
電極端子に他端が接続するようになるリード23と、ビヤ
ホール36を介して中間部にリード33が接続し一端が駆動
回路装置に接続するリード25を形成する。
On the back surface of the wiring film 41, one end is connected to the lead 32 through the via hole 35, and the other end is connected to the electrode terminal of the glass substrate 2 at the other end. The lead 33 is connected to the intermediate portion and one end is formed with the lead 25 connected to the drive circuit device.

【0024】かかる配線フィルム41は、半導体チップ5
を搭載し、リード32を液晶表示パネル1の電極端子に接
続したのち、配線フィルム21と同様に半導体チップ5
を、ガラス基板2の端面およびガラス基板3の上面より
出っ張ることなく収容可能にする。
The wiring film 41 is used for the semiconductor chip 5
After mounting the lead 32 and connecting the lead 32 to the electrode terminal of the liquid crystal display panel 1, the semiconductor chip 5 is formed in the same manner as the wiring film 21.
Can be accommodated without protruding from the end surface of the glass substrate 2 and the upper surface of the glass substrate 3.

【0025】図4は平面図であり、図1の配線フィルム
21に相当する配線フィルム51の表面には、出力リード3
2, 入力リード33, パッド接続端子42および43を形成
し、裏面にはリード23と25を形成する。
FIG. 4 is a plan view showing the wiring film of FIG.
On the surface of the wiring film 51 corresponding to 21, the output lead 3
2, input lead 33, pad connection terminals 42 and 43 are formed, and leads 23 and 25 are formed on the back surface.

【0026】そして、複数個 (図は5個)の半導体チッ
プ5を搭載する配線フィルム51は、長さ方向の端面に欠
所52と53を設け、下辺からは搭載した半導体チップ5の
境界に対応しリード23,32 を分割する切込み54を設け
る。ただし切込み54には、一対の欠所52を結ぶ直線と重
なる部分に膨らみ55を形成する。
The wiring film 51 on which a plurality of (five in the figure) semiconductor chips 5 are mounted is provided with notches 52 and 53 on the end face in the lengthwise direction, and from the lower side is the boundary of the mounted semiconductor chips 5. Correspondingly, a notch 54 for dividing the leads 23, 32 is provided. However, in the notch 54, a bulge 55 is formed at a portion overlapping with a straight line connecting the pair of recesses 52.

【0027】かかる配線フィルム51は、欠所52と53, 切
込み54および膨らみ55を設けたことにより、図1に示す
如き断面コ字形の折り曲げを容易にすると共に、切込み
54は配線フィルム51を断面コ字形に折り曲げたとき、リ
ード23とガラス基板2の電極端子との接続部に剥離方向
の応力が懸からないようにする。
The wiring film 51 is provided with the notches 52 and 53, the notch 54 and the bulge 55 to facilitate bending of the U-shaped cross section as shown in FIG.
Reference numeral 54 prevents stress in the peeling direction from being applied to the connection between the lead 23 and the electrode terminal of the glass substrate 2 when the wiring film 51 is bent in a U-shaped cross section.

【0028】図5において、(イ) は平面図,(ロ) は拡大
し一部分のみ示す裏面図あり、図1の配線フィルム21に
相当する配線フィルム61の表面には、半導体チップ5の
出力パッドを接続する複数個の端子42と、半導体チップ
5の入力パッドを接続する複数個の端子43および端子43
に接続するリード33を形成する。
In FIG. 5, (a) is a plan view and (b) is an enlarged back view showing only a part. On the surface of the wiring film 61 corresponding to the wiring film 21 of FIG. 1, the output pad of the semiconductor chip 5 is formed. A plurality of terminals 42 for connecting the input pads of the semiconductor chip 5 and a plurality of terminals 43 and 43 for connecting the input pads of the semiconductor chip 5.
Forming a lead 33 connected to the.

【0029】他方、配線フィルム61の裏面には、ビヤホ
ール35を介して一端が端子42に接続するリード23と、リ
ード23の他端に接続する第1の試験端子62と、ビヤホー
ル36を介してリード33に接続するリード25と、リード25
の外端部が接続する第2の試験端子63と、試験端子62を
切り離すためのマーク64を形成する。
On the other hand, on the back surface of the wiring film 61, the lead 23 having one end connected to the terminal 42 via the via hole 35, the first test terminal 62 connected to the other end of the lead 23, and the via hole 36 are provided. Lead 25 to connect to lead 33, and lead 25
A mark 64 for disconnecting the second test terminal 63 to which the outer end of the second test terminal 63 is connected and the test terminal 62 is formed.

【0030】かかる配線フィルム61は、半導体チップ5
を搭載したときその電気試験 (例えば導通テスト) が、
端子62,63 に検査用プローブを当接して可能であり、半
導体チップ5をガラス基板2の電極端子に接続するとき
邪魔になる端子62は、配線フィルム61の長さ方向の端部
に形成した一対のマーク64を結ぶ直線に沿って配線フィ
ルム61を切断し切り離されるようになる。
The wiring film 61 is used for the semiconductor chip 5
When equipped with, the electrical test (for example continuity test)
The terminals 62, 63 can be brought into contact with a probe for inspection, and the terminals 62 that interfere with the connection of the semiconductor chip 5 to the electrode terminals of the glass substrate 2 are formed at the end portions in the length direction of the wiring film 61. The wiring film 61 is cut and separated along a straight line connecting the pair of marks 64.

【0031】さらに、端子63も邪魔のときは、マーク64
をそのために必要な位置、例えばマーク64を図示位置よ
り適当に左側に寄せてに形成し、端子62を切り離すと共
に、その切り離し線に直角方向かつマーク64に従って切
断すればよい。
Further, when the terminal 63 is also in the way, a mark 64
Is formed at a position necessary for that purpose, for example, the mark 64 is appropriately shifted to the left side from the illustrated position, the terminal 62 is cut off, and it is cut in the direction perpendicular to the cutting line and according to the mark 64.

【0032】[0032]

【発明の効果】以上説明したように本発明方法によれ
ば、従来の空域に半導体チップが収容可能となり、液晶
表示装置に本発明方法を適用したとき、表示パネルの収
容筐体を小型化する。
As described above, according to the method of the present invention, the semiconductor chip can be accommodated in the conventional air space, and when the method of the present invention is applied to the liquid crystal display device, the housing for the display panel can be miniaturized. .

【0033】さらに、配線フィルムのリードに試験用端
子を接続形成することにより、配線フィルムに搭載した
半導体チップの電気試験を可能とし、かかる端子は搭載
半導体チップの電気試験終了後に切り離すことで、配線
フィルムを基板に接続する際の障害物にならないように
できる。
Further, by connecting and forming a test terminal to the lead of the wiring film, an electric test of the semiconductor chip mounted on the wiring film becomes possible, and such a terminal is cut off after the electric test of the mounted semiconductor chip is completed, so that the wiring is wired. It can be an obstacle when connecting the film to the substrate.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明による半導体チップ実装方法の主要工
程図
FIG. 1 is a main process diagram of a semiconductor chip mounting method according to the present invention.

【図2】 本発明方法に係わる半導体チップ搭載用の第
1の配線フィルムの説明図
FIG. 2 is an explanatory view of a first wiring film for mounting a semiconductor chip according to the method of the present invention.

【図3】 本発明方法に係わる半導体チップ搭載用の第
2の配線フィルムの説明図
FIG. 3 is an explanatory view of a second wiring film for mounting a semiconductor chip according to the method of the present invention.

【図4】 本発明方法に係わる半導体チップ搭載用の第
3の配線フィルムの説明図
FIG. 4 is an explanatory view of a third wiring film for mounting a semiconductor chip according to the method of the present invention.

【図5】 本発明方法に係わる半導体チップ搭載用の第
4の配線フィルムの説明図
FIG. 5 is an explanatory view of a fourth wiring film for mounting a semiconductor chip according to the method of the present invention.

【図6】 半導体チップをCOG実装した従来の表示パ
ネルの説明図
FIG. 6 is an explanatory view of a conventional display panel in which a semiconductor chip is COG-mounted.

【図7】 半導体チップをTAB接続した従来の表示パ
ネルの説明図
FIG. 7 is an explanatory diagram of a conventional display panel in which semiconductor chips are connected by TAB.

【符号の説明】[Explanation of symbols]

2はガラス基板(一方の基板) 3はガラス基板(他方の基板) 5は半導体チップ 6はガラス基板の電極端子 21,31,41,51,61はフレキシブル配線フィルム 23,32 は出力リード 24,25,33は入力リード 27は保護部材 35,36 はビヤホール 62,63 は検査用プローブ当接用試験端子 2 is a glass substrate (one substrate) 3 is a glass substrate (the other substrate) 5 is a semiconductor chip 6 is a glass substrate electrode terminal 21,31,41,51,61 is a flexible wiring film 23,32 is an output lead 24, 25 and 33 are input leads 27 are protective members 35 and 36 are via holes 62 and 63 are inspection probe contact test terminals

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一方の基板(2) の表面に他方の基板(3)
を接合したとき該他方の基板より突出する該一方の基板
の突出部の表面に電極端子(6) を形成し、該電極端子に
接続する半導体チップ(5) の実装に際し、フレキシブル
配線フィルム(21,31,41,51,61)には該半導体チップに接
続する入力リード(24,33) と出力リード(23,32) とを形
成し、該入出力リードの内端部を該半導体チップの入出
力パッドに接続し、該出力リードの外端部を該電極端子
に接続したのち該配線フィルムを断面コ字形に折り曲げ
し、該半導体チップが該一方の基板の突出部の表面上に
位置するようにすること、を特徴とする半導体チップの
実装方法。
1. A substrate (3) on the surface of one substrate (2)
When the semiconductor chip (5) connected to the electrode terminal is mounted on the surface of the protruding portion of the one substrate protruding from the other substrate when the flexible wiring film (21 , 31, 41, 51, 61) are formed with input leads (24, 33) and output leads (23, 32) connected to the semiconductor chip, and the inner ends of the input / output leads are connected to the semiconductor chip. After connecting to the input / output pad and connecting the outer end of the output lead to the electrode terminal, the wiring film is bent into a U-shaped cross section, and the semiconductor chip is located on the surface of the protruding portion of the one substrate. A method for mounting a semiconductor chip, comprising:
【請求項2】 前記配線フィルム(61)の表面には、前記
半導体チップ(5) の入力パッドに接続する入力リード(3
3)と該半導体チップの出力パッドに接続する出力リード
(32)とを形成し、該配線フィルムの裏面には、一端がビ
ヤホール(35)を介して該出力リードに接続し他端に検査
用プローブが当接する第1の試験端子(62)を有するリー
ド(23)と、中間にはビヤホール(36)を介して前記入力リ
ードに接続し外端部に検査用プローブが当接する第2の
試験端子(63)を有するリード(25)を形成し、該第1,第
2の試験端子を用いて該半導体チップの電気試験を実施
し、少なくとも該第1の試験端子を切り離すように該配
線フィルムを切断したのち、該配線フィルムの出力リー
ドを前記電極端子に接続させること、を特徴とする請求
項1記載の半導体チップの実装方法。
2. The surface of the wiring film (61) has an input lead (3) connected to an input pad of the semiconductor chip (5).
3) and an output lead connected to the output pad of the semiconductor chip
(32) is formed, and the rear surface of the wiring film has a first test terminal (62), one end of which is connected to the output lead through the via hole (35) and the other end of which is in contact with the inspection probe. The lead (23) and the lead (25) having the second test terminal (63) connected to the input lead through the via hole (36) and contacting the inspection probe at the outer end portion are formed in the middle, An electrical test of the semiconductor chip is performed using the first and second test terminals, the wiring film is cut so as to disconnect at least the first test terminal, and then the output lead of the wiring film is connected to the electrode. The method for mounting a semiconductor chip according to claim 1, wherein the method is to connect to a terminal.
【請求項3】 前記半導体チップ(5) を包むような断面
コ字形に折り曲げした前記配線フィルム(21,31,41,51,6
1)の折り曲げ先端部を前記他方の基板(3) に接着したの
ち、開口部が前記一方の基板(2) と該一方の基板に接合
した該他方の基板とを挟み該配線フィルムを覆う断面コ
字形の保護部材(27)を挿着することを特徴とする請求項
1記載の半導体チップの実装方法。
3. The wiring film (21, 31, 41, 51, 6) bent in a U-shaped cross section so as to wrap the semiconductor chip (5).
A cross section covering the wiring film after the bent tip of (1) is bonded to the other substrate (3), and the opening sandwiches the one substrate (2) and the other substrate bonded to the one substrate. The semiconductor chip mounting method according to claim 1, wherein a U-shaped protection member (27) is inserted.
JP4301458A 1992-11-12 1992-11-12 Mounting method for semiconductor chip Withdrawn JPH06152192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4301458A JPH06152192A (en) 1992-11-12 1992-11-12 Mounting method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4301458A JPH06152192A (en) 1992-11-12 1992-11-12 Mounting method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPH06152192A true JPH06152192A (en) 1994-05-31

Family

ID=17897142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4301458A Withdrawn JPH06152192A (en) 1992-11-12 1992-11-12 Mounting method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPH06152192A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959709A (en) * 1997-08-11 1999-09-28 Nec Corporation Display unit with flexible printed circuit board
JP2001311962A (en) * 2000-03-17 2001-11-09 Samsung Electronics Co Ltd Driving module for liquid crystal display panel and liquid crystal display device having the same
JP2004287059A (en) * 2003-03-20 2004-10-14 Fujitsu Display Technologies Corp Liquid crystal display
CN101779530A (en) * 2008-07-25 2010-07-14 松下电器产业株式会社 Component mounting device and method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959709A (en) * 1997-08-11 1999-09-28 Nec Corporation Display unit with flexible printed circuit board
US5963287A (en) * 1997-08-11 1999-10-05 Nec Corporation Display unit with flexible printed circuit board
JP2001311962A (en) * 2000-03-17 2001-11-09 Samsung Electronics Co Ltd Driving module for liquid crystal display panel and liquid crystal display device having the same
JP2004287059A (en) * 2003-03-20 2004-10-14 Fujitsu Display Technologies Corp Liquid crystal display
CN101779530A (en) * 2008-07-25 2010-07-14 松下电器产业株式会社 Component mounting device and method
US8074351B2 (en) 2008-07-25 2011-12-13 Panasonic Corporation Part mounting device and part mounting method

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Effective date: 20000201