JPH0681510B2 - Reference signal creation circuit for synchronous PWM inverter - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit for digitally generating a reference signal of a PWM inverter.

[Prior art]

An ignition pulse of a synchronous PWM inverter, for example, an inverter whose switching element is a gate turn-off thyristor, is generated by comparing a reference triangular wave signal Vc and a sine wave signal Vs as shown in FIG. Vp indicates an output pulse. In the case of the synchronous type, the number N of output pulses Vp included in one cycle is always an integer, but the number N of pulses is limited because the switching frequency of the switching element of the inverter is limited. As fo increases, it is necessary to reduce it correspondingly. That is, modulation reference frequency = fo
It is necessary to prevent × N from exceeding the maximum switching frequency fm. However, if the inverter load is an AC motor, it is better that the value of fo × N is as large as possible in order to reduce the torque pulsation of the motor.
As shown in the figure, the number of pulses N is changed according to the output frequency fo, but as a result, the modulation reference frequency f changes discontinuously as shown in the figure.

For this reason, in the conventional PWM control circuit using the microcomputer, as shown in FIG. 3, the modulation reference frequency f which changes discontinuously is stored as a function in the ROM indicated by reference numeral 1 and is called by D The signal is converted into an analog signal by the / A converter 2 and then guided to the voltage / frequency converter 3 to obtain a PWM reference signal having a modulation reference frequency.

As described above, in the conventional computer-controlled PWM reference signal generating circuit, it is necessary to restore the digital output of the ROM corresponding to the modulation reference frequency to the analog signal, so that the circuit is complicated and expensive.

[Outline of Invention]

The present invention has been made in order to eliminate the above-mentioned conventional drawbacks. In a PWM control circuit using a microcomputer, the frequency of the reference clock of the microcomputer is calculated from the first programmable divider, which is the inverter output frequency x the number of output pulses. To a PWM reference signal, and the output of the PLL circuit is divided by a second programmable divider to generate a PWM reference signal. The second programmable divider circuit is used as a feedback input of the PLL circuit. A frequency obtained by dividing the output of the divider by the third divider is applied, and the frequency division number of the second programmable divider is switched at the same timing as the frequency division number of the first programmable divider. It is possible to digitally create the PWM reference signal, and therefore cheaper than conventional ones. That proposes a reference signal generating circuit of the synchronous PWM inverter.

Example of Invention

 FIG. 4 is a block diagram showing an embodiment of the present invention.

In the figure, reference numerals 10, 20, 30, 40 denote programmable dividers (hereinafter abbreviated as frequency dividers), the frequency division numbers of which are controlled by the microcomputer 100. 50 is PLL
A circuit that performs a frequency multiplier operation.

The reference clock of the microcomputer 100 is input to the frequency divider 10. The frequency divider (frequency divider M1) 10 divides the frequency fc of the reference clock into a frequency obtained by multiplying the output frequency fo of the inverter by the least common multiple X of the pulse number. For example, fc = 2MHz,
If X = 135 and fo = 0, the frequency division number M1 is sufficiently large 247
Therefore, the output accuracy of the frequency divider 10 is sufficiently high. Divider
20 is the frequency fo × X frequency-divided by the frequency divider 10 and the frequency division number M2 = X /
Divide by N. N is the number of output pulses described above. When N = 45, if X = 135, the frequency division number M2 =
Therefore, the frequency division number output from the frequency divider 20 is fo × 45.
This frequency division number fo × 45 becomes the frequency reference of the PLL circuit 50. The output of the PLL circuit 50 is input to a frequency divider (frequency division number M3) 30, and the frequency division number M3 of the frequency divider 30 is the same as the frequency division number M2 of the frequency divider 20. The modulation reference frequency f output from the frequency divider 30
Is fed back to the PLL circuit 50 through a frequency divider (frequency division number M4) 40.

For convenience of explanation, the frequency division number of the frequency divider 30, M3 = 3 (frequency divider 20
Frequency division number M2) and the frequency division number M4 of the frequency divider 40 = 256, the frequencies appearing at the output points 51, 31, 41 are 256 × 3 × N × fo and 256, respectively, due to the nature of the PLL circuit 50. Xfo and fo × N. The frequency reference = fo × N of the PLL circuit 50 and the frequency of the feedback input = fo × N change discontinuously with respect to the pulse number N. However, the frequency division numbers M2 and M3 of the frequency dividers 20 and 30 are Since they are the same, and since these changes are simultaneous, there is no phase change and the operation of the PLL circuit 50 is stable. Also, the PLL circuit
The frequency M4.times.M3.times.N.times.fo given by 50 to the division period 30 continuously changes in proportion to the output frequency fo, so that the operation delay of the circuit can be ignored.

In this embodiment, as described above, the frequency of M4 times the modulation reference frequency f = fo × N is taken out from the frequency divider 30 as an output, so that the reference triangular wave Vc of FIG. 1 is digitally generated. In that case, the count number of one cycle may be set to M4.

The frequency dividers 10 and 20 in the above embodiment can be integrated.

Further, the frequency divider 40 may be a fixed divider.

〔The invention's effect〕

As described above, since the present invention has a pure digital configuration using a programmable divider and a PLL circuit,
Compared with the conventional one, there is an effect that the cost can be reduced and the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a waveform diagram of a synchronous PWM signal, FIG. 2 is a diagram showing a relationship between a modulation reference frequency and an inverter output frequency, FIG. 3 is a block diagram of a conventional PWM reference signal generating circuit, and FIG.
The figure is a block diagram of an embodiment of the present invention. In the figure, 10 to 40 are programmable dividers, 50 ...
PLL circuit, 100 ... Microcomputer.

Claims (1)

[Claims] 1. A first programmable divider which divides a reference clock to be inputted by controlling a dividing number by a microcomputer and divides it by an output frequency of an inverter × output pulse number, and an output of the first programmable divider. PLL circuit which inputs as a command value, the microcomputer switches the frequency division number at the same timing as the frequency division number of the first programmable divider, divides the output of the PLL circuit, and outputs the PWM reference signal of the inverter. A reference signal generating circuit for a synchronous PWM inverter, comprising: a second programmable divider for outputting; and a third programmable divider for dividing the output of the second programmable divider and feeding back to the PLL circuit.