SU828360A1 - Frequency converter control device - Google Patents

Description

oscillator, two frequency dividers, outputs connected to the inputs of shapers of control of power thyristors, a disjunctor connected by an input to the outputs of the frequency dividers, and output via a serially connected counter and decoder to the installation inputs of a controlled frequency splitter, shaper of control of thyristors of a reverse bridge connected by the input to the output of the counter, is controlled by an adjustable generator and a pulse adder, and the inputs of the pulse adder are connected correspondingly It is connected to the outputs of the master oscillator and the counter and through a controlled divider to the output of the adjustable oscillator, and the outputs to the inputs of the frequency dividers.

FIG. 1 shows a schematic diagram of a device, its device; in fig. 2 is a schematic diagram of a device for controlling a frequency converter; in fig. 6 is a timing diagram of the operation of individual units of the device for controlling the frequency converter.

11reform, its device contains inverters 1 and 2, transformers 3 and 4, controlled reversing bridge 5 on thyristors 6-9 and load 10.

A device for controlling a frequency converter contains a master oscillator II, an adjustable oscillator 12, a controlled frequency divider 13, frequency divisors 14 and 15, a pulse adder 16, a decryptor G /, a counter 18, a disjunctor 19, shapers 20 and 21 of control pulses of inverters 1 and 2 accordingly, the driver 22 of the thyristor control pulses of the reversing bridge 5. 23-29 - pulses at the outputs of the device elements.

The device works as follows.

The pulses from the generator 11 through the adder 1b are fed to two frequency division channels on dividers 14 and 15, the pulses from the outputs of which are fed to the shapers 20 and 21 of the thyristor control pulses of inverters 1 and 2, respectively.

The pulses from the intermediate outputs of the dividers 14 and 1 frequency arrive at the disjunctor 19. From the output of the disjunctor 19, the pulses 23 of the difference frequency arrive at a five-digit counter 18, the output pulses of which are fed to the decoder G /, in which a switching code is generated (pulses 26, 27, 28) the division factor of the frequency divider 13.

The pulses of the generator 12 through the frequency divider 13 arrive at the second input of the adder 16. Since the slope of the direct modulation law of the pulse-width output voltage and the transducer is determined by the frequency difference between the first and second division channels (Fig. 3, 29), for In order to obtain a quasi-sinusoidal construction function, it is necessary in the first section to choose such a slope of the construction function so that this line intersects the sinusoidal construction function at a value of 0.5 Lx. In sections II and III, the division factor of the frequency divider 13 is chosen to be respectively smaller. The pulses 24 from the fourth (the penultimate) discharge of the counter 18 arrive at the control input of the adder 15. The presence of the logical 16 at the control input of the adder 16 (Fig. 3, 24, 2y) during / 4 the output voltage period, leads to summation pulses with a frequency sor / Hu.d with pulses of the generator 11, having a frequency co. on the first frequency division channel (frequency divider 14), with Ku.d being the divider division factor

13, the frequency is changed in accordance with the algorithm defined by the decoder 17.

Due to the difference in frequencies on the output of the dividers 14 and 15, the frequency of the phase of the pulse sequence with a higher frequency

slips in time with respect to the phase of the pulse sequence of the second channel, which leads to the modulation of the pulses of the output voltage of the converter.

During the second part of the half-cycle of the output voltage of the converter (Fig. 3, 24, 29), the adder 16 is set to the summing mode of the pulses of the driver 11 and the controlled oscillators with frequencies 00 and d) p // Su.d over the second frequency division channel (divider 15 frequencies).

In this case, the frequency of the pulse sequence of the first channel on the output of the frequency divider 14 is less than the frequency of the pulse sequence of the second channel at the output of the frequency divider 15. This leads to a change in the phase difference between them in the opposite direction, and consequently, to a change in the pulse duration of the output voltage of the converter.

A change in the frequency of the generator 12 leads to a change in the rate of increase of the phase shift between the n. Pulses at the outputs of frequency dividers 14 and 15, i.e., the change in the slope of the quasi sinusoidal envelope 29 of the output voltage of the converter, and hence the regulation of the average value of the output voltage.

The control of the reversible rectifying bridge 5 connected at the output of the converter is carried out through the pulse shaper 22, to which the pulses 25 are fed from the fifth digit of the counter 18.

Thus, the use of new elements in the device (adjustable generator and pulse adder) makes it possible to adjust the amplitude of the first harmonic of the output voltage of the converter, i.e., to expand the functional capabilities of the device.

Claims (2)

1. USSR author's certificate No. 551795, cl. H 02 R 3/16, 1976. 2. USSR author's certificate JYo 570181, cl. H 02P 13/18, 1977 (prototype). FIG. one fJ 2t 25 28 L FIG. 3