JPH0679272B2 - Instruction fetch controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] An instruction fetch method in a microprogram type computer system, in which a macro instruction is read from a main storage device based on firmware in a calculation type system,
In order to solve the enormous hardware configuration of the instruction fetch address holding means for setting the logical address at the time of microinstruction operation for fetching a plurality of macro instructions, the instruction fetch address holding means is set to a few lower bits. By configuring with a counter and having the remaining high-order bits in a register group used for other purposes, a small-capacity hardware configuration is possible without imposing a large burden on the firmware.

[Industrial application field]

The present invention relates to an instruction fetch method in a microprogram type computer system.

In general, macro instructions in a microprogram type computer system are assigned to consecutive memory addresses in the main memory.

On the other hand, the micro instruction fetches the macro instructions one by one, interprets the meaning of the macro instruction, and executes the corresponding process.

After processing one macro instruction, the micro instruction increments the macro instruction logical address by 1 to fetch the next macro instruction.

The +1 macro instruction logical address is checked for the occurrence of a page cross. If a page cross occurs, the index table is indexed by the +1 logical address, and the correct physical address is obtained. After that, macro instruction fetch is performed.

Since the in-page address is logical address = physical address (memory address of the main storage device), the logical address obtained by adding 1 is used.

All of these processes are performed by micro-instructions, and it is definitely required to be processed in a short number of steps.

[Conventional technology]

FIG. 4 shows a block diagram for explaining a conventional example. FIG. 4 shows a central processing unit (hereinafter referred to as CPU) 1 and a main storage device 2.
2 shows a computer system that includes the above and controls a data processing operation based on a microprogram stored in a control program memory (not shown).

CPU 1 is an arithmetic logic unit (hereinafter referred to as ALU) 3 that performs fixed-point arithmetic operations and logical operations, and the contents selected by MPX6c under the control of selection signal (1) (addresses for accessing the memory in main memory 2). ) Storing an address register (hereinafter referred to as SAR) 4, a plus 1 circuit 5 for sending data for adding 1 to the address calculation to the ALU 3, and a selected one of a plurality of input data and sending it. Multiplexers (hereinafter referred to as MPX) 6a to 6c and a flip-flop (hereinafter referred to as FF) 7 that fetches a page cross output from the ALU3 and sends a page cross signal when a predetermined micro instruction is instructed (3). And an instruction fetch address register (hereinafter referred to as iA) 8 for holding an instruction fetch address.

Note that the code (a) indicates other ALU outputs, and the codes (b) and (c)
Indicates the outputs of the registers storing the data transferred from others.

In a microprogram type computer system as shown in FIG. 4, when a macro instruction (an instruction in a source language that can be replaced by a series of instruction statements written in the same source language) is read from the main memory 2. The following instructions are required in the micro instruction. That is, (a) An instruction to set the contents of iA8 in SAR4. (Signal (1) or command in the figure) (b) Instruction to count up iA8 with ALU3.
(Signal (2) or command in the figure) (C) Instruction for checking page cross (described later) when counting up iA8 with ALU3. (Signal (3) or instruction in the figure) In the operation of the micro instruction, iA8 means an address register dedicated to the macro instruction address.

In addition, in the above-mentioned microinstruction, the microinstruction operation of (a) is that the content of iA8 is an address register (SA
R) This is an operation to set to 4.

The output data of SAR4 becomes the address of the main storage device 2, and therefore data other than iA8 (for example, the first operand address) is also set in SAR4, so the input signal is the data of multiple registers (b) etc. With MPX6c,
It will be taken out.

That is, in order to read the macroinstruction data (instruction) from the main memory 2, the iA8 data is selected by the MPX6c and the SAR4
Will indicate a microinstruction indicating that it is set to.

The microinstruction operation (b) is an operation for counting up using the general-purpose ALU in order to set the value of iA8 to the next macroinstruction address.

In this operation, macro instructions are generally assigned to consecutive memory addresses.
Since it is only necessary to count up one by one, general-purpose AL
Processing is performed using U.

In addition, (c) microinstruction operation is used to detect the carry flag of ALU3 output during page cross detection during ALU3 operation (b).
This is the operation to set to F.F7.

This is because the addition process using ALU3 etc. is used for other calculations as described above, so at any calculation process page cross detection (that is, instruction address addition is performed) is detected.
Is an operation to instruct whether or not to perform, and this is performed by a dedicated micro instruction.

An index table (not shown) that associates the main memory address with the logical address is prepared in the fixed area in the CPU 1 or the main memory device 2.

In this index table (not shown), main memory addresses (physical addresses) and logical addresses are associated in page units.

Generally, the address of a macro instruction becomes the next macro instruction address by adding 1 to the main storage address (physical address) currently being executed as described above.

However, if the address added by 1 exceeds the specified page unit (for example, 2 kilobytes, 4 kilobytes, etc.), the main memory address (physical address) reads a completely different logical address. Become.

Therefore, at this point, refer to the index table (not shown) again and check the correct main memory address (physical address).
Need to ask.

From this logical address to the main memory address (physical address)
The conversion operation to is called address conversion.

If the address added by 1 exceeds the predetermined page unit, it is called a page cross. If this page cross occurs, the instruction address currently being executed plus 1
It is necessary to discard the main memory address (physical address) of the above and newly obtain the main memory address (physical address) by referring to an index table (not shown).

It should be noted that page cross may be generally determined to occur depending on the condition when the main memory address (physical address) is incremented by 1.

[Problems to be solved by the invention]

In the conventional example as shown in FIG. 4, a general-purpose ALU is used for the operation in (b), and this general-purpose ALU uses other arithmetic processing (for example, addition and subtraction of first and second operants, addition of general-purpose register). , Subtraction, bit manipulation, etc.)
At the time of counting up 8, there arises a problem that the above-mentioned arithmetic processing cannot be performed.

Further, there is a variety of problems such that the micro-instruction of a predetermined number of steps is required even for the processing such as (c) that only performs simple detection, and the number of micro-steps increases accordingly.

[Means for solving problems]

 FIG. 1 shows a block diagram illustrating the principle of the present invention.

The principle block diagram of the present invention shown in FIG. 1 is composed of the main memory 2 described in FIG. 4 and a CPU 10 described below.

That is, the present invention comprises a main memory device 2 whose capacity is divided into page units each having a predetermined byte, and a central processing unit 10 which controls a data processing operation based on a microprogram stored in a predetermined memory. In the computer system, a microinstruction for fetching a macroinstruction is defined in the execution instructions generated from the central processing unit 10, the upper logical address for fetching the macroinstruction is held, and the arithmetic logic operation unit 3 Register group 11 that is incremented by a macro instruction using, and a register dedicated to the macro instruction address, which holds the lower part of the logical address that is configured to include the address in the physical page, and fetches the macro instruction. Has an automatic count-up circuit that counts up the logical address by micro instruction Instruction fetch address holding means 12, page cross detection means 13 for detecting a page cross from the uppermost digit of the physical page address included in the logical address held in the instruction fetch address holding means 12, and the instruction fetch address holding means Overflow detection means 14 for detecting an overflow from the uppermost digit of the logical address held in 12, the logical address held in the register group 11 and the logical address held in the instruction fetch address holding means 12 are set An address register 40, and when the macro instruction is fetched, the page cross detection means
When the page cross is not detected by 13, the physical page address held in the instruction fetch address holding means 12 counted up by the microinstruction is set to the corresponding digit of the page address of the address register 40. When the page cross detecting means 13 detects a page cross, the logical address held in the register group 11 and the instruction fetch counted up by the micro instruction The logical address held in the address holding means 12 is set in the address register 40, the logical page address included in the set logical address is converted into a physical address of a predetermined page in the main memory 2, and the page cross is performed. While detecting the page cross by the detecting means 13, When an overflow is detected by the overflow detection means 14, the logical address held in the register group 11 counted up by the microinstruction using the arithmetic logic operation unit 3 and the instruction counted up by the microinstruction A logical address held in the fetch address holding means 12 is set in the address register 40, and a physical page address included in the set logical address is converted into a logical address of a predetermined page of the main storage device 2. .

[Action]

The lower several bits of the instruction fetch address stored in SAR40 are in the iA8 internal counter (not shown), and the remaining upper several bits are in the register group 11 which is also used for other purposes. An iA8 internal counter (not shown) and a register group 11 are configured to carry (add one plus) to the upper several bits when a carry-out (carry) signal is output from (not shown).

The value of this counter (not shown) is incremented when a memory request for instruction fetch is output.
By configuring the address within the page to SAR40 and further counting up to detect whether the logical address is causing a page cross carry out, a simple hardware configuration ensures shorter processing. It will be feasible in time.

〔Example〕

The gist of the present invention will be specifically described below with reference to the embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating processing operations in the embodiment of the present invention.

The same reference numerals denote the same objects throughout the drawings.

The iA unit 12 in the embodiment of the present invention sequentially adds the contents of iA8 to iA8, which is a register dedicated to a macro instruction address, by 1
It is configured by adding a plus 1 circuit 12a.

Also, page cross detection means 13 and overflow detection means
14 includes a page cross detection circuit 13a and F.F13b, and an overflow detection circuit 14a and F.F14b, respectively.

Further, in the register group 11 used in the embodiment of the present invention, when the register number is designated by the address line (d), the data corresponding to the register number is output from the output line (e).

In general, such a register group 11 has one chip (IC1
) Or one macro (one functional block in LSI).

That is, since the register group 11 is composed of an IC random access memory (RAM), the number of used elements is small, but in order to count up, it must be performed by a microprogram using ALU, and microsteps increase.

On the other hand, since the iA8 has the plus 1 circuit 12a, it does not need microinstructions, but it must be of a counter type composed of a large number of flip-flops, and the number of elements per bit is larger than that of the register 11.

The iA8 in the iA unit 12 of the present embodiment is a register that sets lower bits of the logical address of the macro instruction fetch.

Therefore, the in-page address is included in this iA8.

Next, the operation of the hardware in the CPU 10 will be described below according to the execution order of the microinstructions.

(B): When performing a macro instruction fetch, a logical address corresponding to the main memory address in the main memory device 2 (for example,
Of the 32 bits), the logical address (32
Multiple upper bits (16 bits, for example) are SAR40
, IA8 sets the lower bits (for example, 16 bits) of the logical address (32 bits) in the SAR 40.

Logical address (1
6 bits) is the logical page address (eg 21 bits)
It consists of the upper digit (16 bits).

Logical address set in iA8 to SAR40 (16 bits)
Are registers within the logical page address (21 bits)
It is composed of the remaining lower digits (5 bits) excluding the upper digit (16 bits) set in SAR40 from 11 and the logical page address (11 bits).

If this set operation is the first, the same operation as at the time of page cross detection described later is performed, and the logical page address (21 bits) of the logical address (32 bits) set in SAR40 is stored in the CPU1 or in the main memory. It is converted into a physical page address by an index table (not shown) prepared in a fixed area in the device 2, and is set in the SAR 40 again.

This operation is also performed by the conventional device and is not peculiar to the present invention.

In this operation, the micro instruction is a macro instruction fetch micro instruction (this micro instruction is called RQF).
And issue a microinstruction for selecting the main memory page address and instructing the SAR 40 to set. (The in-page address in iA8 is set to SAR40 by the RQF instruction.) This physical page address (21 bits) and the logical page address initially set, that is, the physical page address (11 bits) The address of main memory 2 (32
Bit) is indicated.

After that, when the macro instruction is fetched, the address within the logical page to which the address value is incremented by 1, i.e., the address within the physical page (11 bits) is set in the SAR 40 from the iA8, and the addresses within the page are sequentially updated.

(B): The RQF instruction causes iA8 to count up at the end of the instruction.

When a page cross occurs as a result of counting up iA8, the logical page address (5 bits) in iA8 is updated.

That is, first, the value (address value) of iA8 is counted up by the plus 1 circuit 12a.

The page cross detection is performed by the page cross detection circuit 13a in the page cross detection means 13, and the detection result is F.F13.
Latched to b.

In this page cross detection, the carry from the iA8 is only detected as shown in FIGS. 3B and 3C.

For example, if the page size is 4 Kbytes, see Fig. 3 (2).
When all the lower 12 bits of iA8 corresponding to the logical page address shown in (1) are '1', the page cross is detected by the page cross detection circuit 13a.

The page cross signal indicating that this page cross has occurred is set to F.F13b at the end of the RQF instruction.

When the page cross signal is set due to the occurrence of page cross and F.F13b is turned on, the upper bit (16 bits) of the logical address is set from register group 11 to SAR40, and the lower bit of the logical address from iA8 ( 16 bits) is set in SAR40.

As described above, the logical address (16 bits) set in register group 11 to SAR40 is the high-order digit of the logical page address (21 bits), and the logical address (16 bits) set in iA8 to SAR40 is the logical page. The remaining lower digits (5 bits) of the address and the logical page address (11 bits).

Next, the logical address set in SAR40 (32 bits)
The logical page address (21 bits) is converted into a physical page address.

The conversion to the physical page address is performed by a predetermined micro instruction, and, for example, an index table (not shown) prepared in a fixed area in the main memory 2 or a conversion table (not shown) provided separately. ) Is accessed by the logical page address (21 bits) of SAR40 and converted into a physical page address (21 bits).

The converted physical page address is output to, for example, another register (b) and set again in the SAR 40 via the MPX6d.

The physical page address (21 bits) set again in the SAR 40 becomes a physical address (32 bits) that instructs the main storage device 2 together with the already set physical page address (11 bits).

When one macro instruction fetch is completed, the address value is incremented by 1 in iA8, which means that the address value of the physical page address (11 bits) is counted up.

Therefore, after this, the physical page address (21 bits) that has already been set remains unchanged, and the physical page address counted up by iA8 each time the macro instruction is fetched is the digit of the corresponding physical page address of SAR40. (11
Bit).

This operation is performed until the next page cross occurs.

(C): iA at the same time as page cross by the RQF instruction in (b)
When a carry from the most significant bit of the unit 12 occurs, an overflow signal is output from the overflow detection unit 14, whereby the upper bits of the instruction fetch logical address of the register group 11 are updated by the microinstruction using the ALU3.

In this case, it takes more time to execute the microinstruction compared to the update using the iA8 plus 1 circuit 12a, but an overflow signal is rarely output, and it is very small compared to the overall processing time. Therefore, the processing efficiency does not decrease.

The processing in such a case is as follows.

That is, the carry from the most significant bit of the iA section 12 occurs when all the bits are all "1" (the state of FIG. 3 (4)) before the iA section 12 is counted up.

The carry from the most significant bit is F.F1 in the overflow detection means 14 at the end of the RQF instruction, similar to the page cross carry.
It is set to 4b.

Subsequent operations are performed by microinstructions.

This microinstruction reads the state of F.F14b, and if it is on, the logical page address obtained by adding 1 to the upper logical address read from the register group 11 is added to the new main memory page address (physical address). Convert to.

(D): SAR4 when not in the states of (b) and (c)
Main memory page address (physical address) in 0 and R
The main page memory 2 is accessed by the in-page address set in the SAR 40 and updated in the iA8 by the QF instruction.

〔The invention's effect〕

As described above, according to the present invention, data processing based on a micro program can be reliably performed with a simple hardware configuration.
Moreover, there is an effect that it can be realized in a shorter time.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating processing operations in the embodiment of the present invention, and FIG. A block diagram for explaining a conventional example is shown respectively. In the figure, 1,10 is CPU, 2 is main memory, 3 is ALU, 4,40 is SAR, 5,12a is plus 1 circuit, 6a-6d is MPX, 7,13b, 14b is FF, 8 is iA , 11 is a register group, 12 is an iA unit 13, 13 is a page cross detecting means, 13a is a page cross detecting circuit, 14 is an overflow detecting means, and 14a is an overflow detecting circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Abo 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Masayoshi Takei, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Kazuyasu Nonomura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Yoshimachi Nishimachi, 1015, Ueodaanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Yasutomi Sakurai 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP-A-60-51947 (JP, A)

Claims (1)

[Claims] 1. A main storage device (2) whose capacity is divided into pages each consisting of a predetermined byte, and a central processing unit (10) for controlling a data processing operation based on a microprogram stored in a predetermined memory. In a computer system including: a microinstruction for fetching a macroinstruction in an execution instruction generated from the central processing unit (10) is defined, and a higher logical address for fetching the macroinstruction is held. , A register group (11) that is counted up by a macro instruction using the arithmetic and logic unit (3) and a register dedicated to the macro instruction address, which is lower than a logical address configured to include an address within a physical page. An automatic counting in which the logical address is counted up by a micro instruction for holding and fetching a macro instruction Instruction fetch address holding means (12) having an up circuit, and page cross detection means for detecting page cross from the uppermost digit of the physical page address included in the logical address held by the instruction fetch address holding means (12) (1
3), overflow detection means (14) for detecting an overflow from the most significant digit of the logical address held in the instruction fetch address holding means (12), the logical address held in the register group (11) and the instruction A case in which a page cross is not detected by the page cross detection means (13) at the time of macro instruction fetch, comprising an address register (40) in which the logical address held in the fetch address holding means (12) is set. In the main memory by setting the physical page address held in the instruction fetch address holding means (12) counted up by the micro instruction to the corresponding digit of the page address in the address register (40). The physical address for designating the device (2) is used, and the page cross detection means (13) is used for page , The logical address held in the register group (11) and the logical address held in the instruction fetch address holding means (12) counted up by the microinstruction are set in the address register (40). And a logical page address included in the set logical address is converted into a physical address of a predetermined page of the main storage device (2), and a page cross is detected by the page cross detection means (13). When an overflow is detected by the overflow detection means (14), the logical address held in the register group (11) counted up by the microinstruction using the arithmetic logic operation unit (3) and the microinstruction are detected by the microinstruction. Logical address held in incremented instruction fetch address holding means (12) Is set in the address register (40), and a logical page address included in the set logical address is converted into a physical address of a predetermined page of the main storage device (2).