JPH0677248A - Manufacture of amorphous silicon thin film transistor - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing an amorphous silicon thin film transistor, which keeps cleanly the surface of a non-doped amorphous silicon layer and is capable of obtaining a good contact. CONSTITUTION:(A) A gate electrode 12 is formed on an insulative substrate 11 into a prescribed form and thereafter, a gate insulating layer 13 and a non- doped amorphous silicon layer 14 are formed in order and a photoresist layer 15 is formed. (B) A protective insulating layer 16 is formed. (C) The layer 15 and the layer 16 on the layer 15 are removed by a lift-off method and an insular structure consisting of the layer 16 is formed. (D) An impurity-doped amorphous silicon layer 17 is formed. (E) Source/drain electrodes 18 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an amorphous silicon thin film transistor.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example and is an explanatory view showing a manufacturing process of an amorphous silicon thin film transistor. Hereinafter, the manufacturing process will be described with reference to FIGS.

(A) A gate electrode 32 on an insulating substrate 31
Then, a gate insulating layer 33, a non-doped amorphous silicon layer 34, and a protective insulating layer 36 are sequentially formed, and a photoresist layer 35 is formed on the protective insulating layer 36.

(B) The protective insulating layer 36 is etched using the photoresist layer 35 as a mask to form an island structure of the protective insulating layer 36.

(C) After forming the impurity-doped amorphous silicon layer 37, the non-doped amorphous silicon layer 34 and the impurity-doped amorphous silicon layer 37
Is patterned into a predetermined shape.

(D) After forming the source / drain electrode 38, the impurity-doped amorphous silicon layer 37 is removed using the source / drain electrode 38 as a mask.

[0007]

In the above conventional example, since the surface of the non-doped amorphous silicon layer 34 is also etched when the island structure of the protective insulating layer 36 is formed in the step (B), the non-doped amorphous layer is formed. Silicon layer 34
Surface becomes rough. Therefore, it was difficult to obtain good contact between the non-doped amorphous silicon layer 34 and the impurity-doped amorphous silicon layer 37.

An object of the present invention is to provide a manufacturing method capable of keeping the surface of a non-doped amorphous silicon layer clean and obtaining good contacts.

[0009]

A method of manufacturing an amorphous silicon thin film transistor according to the present invention comprises a step of forming a gate electrode on an insulating substrate and a step of forming a gate insulating layer on the insulating substrate and on the gate electrode. 1 forming an insulating layer, forming a non-doped amorphous silicon layer on the first insulating layer, and forming a resist layer having an opening above the gate electrode on the non-doped amorphous silicon layer. A step of forming a second insulating layer on the resist layer and the non-doped amorphous silicon layer, and removing the resist layer and the second insulating layer on the resist layer by a lift-off method to correspond to the opening. Forming an island-shaped structure of the second insulating layer in the formed region, and exposing the island structure by the lift-off method. And a step of forming an impurity-doped amorphous silicon layer on the emission-doped amorphous silicon layer.

[0010]

EXAMPLE FIG. 1 shows an example and is an explanatory view showing a manufacturing process of an amorphous silicon thin film transistor.

Reference numeral 11 denotes an insulating substrate, 12 denotes a gate electrode, and 1
3 is a gate insulating layer using silicon nitride or the like, 14 is a non-doped (intrinsic) amorphous silicon layer,
Reference numeral 15 is a photoresist layer, 16 is a protective insulating layer using silicon nitride or the like, 17 is an impurity-doped amorphous silicon layer in which an appropriate amount of n-type impurities are doped, and 18 is a source / drain electrode.

Hereinafter, according to FIGS. 1 (A) to 1 (E),
The manufacturing process will be described.

(A) Gate electrode 12 on insulating substrate 11
After forming the gate insulating layer 11 into a predetermined shape, the gate insulating layer 13 is formed on the insulating substrate 11 and the gate electrode 12, and the gate insulating layer 1 is formed.
A non-doped amorphous silicon layer 14 is sequentially formed on the surface 3. This non-doped amorphous silicon layer 14
A photoresist layer 15 having an opening 15a is formed thereon.

(B) Plasma CV is formed on the photoresist layer 15 and the non-doped amorphous silicon layer 14.
The protective insulating layer 16 is formed by using the D method or the like.

(C) The photoresist layer 15 and the protective insulating layer 16 on the photoresist layer 15 by the lift-off method.
Is removed to form an island structure of the protective insulating layer 16 in the region corresponding to the opening 15a. In this way, since the island structure of the protective insulating layer 16 is formed by the lift-off method,
The surface of the non-doped amorphous silicon layer 14 is not etched, and the surface of the non-doped amorphous silicon layer 14 is kept clean.

(D) After the impurity-doped amorphous silicon layer 17 is formed on the non-doped amorphous silicon layer 14 and the protective insulating layer 16, the non-doped amorphous silicon layer 14 and the impurity-doped amorphous silicon layer 17 are patterned into a predetermined shape. To do. Since the surface of the non-doped amorphous silicon layer 14 is clean, good contact can be obtained between the non-doped amorphous silicon layer 14 and the impurity-doped amorphous silicon layer 17.

(E) After forming the source / drain electrode 18, the impurity-doped amorphous silicon layer 17 is removed by using the source / drain electrode 18 as a mask, and the source / drain of the impurity-doped amorphous silicon layer 17 is removed. Form the drain.

[0018]

According to the present invention, since the island structure of the protective insulating layer is formed by the lift-off method, the surface of the non-doped amorphous silicon layer is not etched unlike the conventional example, and the non-doped amorphous silicon is not formed. The surface of the layer is kept clean. Therefore, good contact can be obtained between the non-doped amorphous silicon layer and the impurity-doped amorphous silicon layer.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an embodiment of the present invention and showing a manufacturing process of an amorphous silicon thin film transistor.

FIG. 2 shows a conventional example and is an explanatory view showing a manufacturing process of an amorphous silicon thin film transistor.

[Explanation of symbols]

 11 ... Insulating substrate 12 ... Gate electrode 13 ... Gate insulating layer (first insulating layer) 14 ... Non-doped amorphous silicon layer 15 ... Photoresist layer 15a ... Opening 16 ... Protection Insulating layer (second insulating layer) 17 ... Impurity doped amorphous silicon layer

Claims (1)

[Claims] 1. A step of forming a gate electrode on an insulating substrate, a step of forming a first insulating layer to be a gate insulating layer on the insulating substrate and on the gate electrode, and on the first insulating layer. A step of forming a non-doped amorphous silicon layer on the non-doped amorphous silicon layer, a step of forming a resist layer having an opening above the gate electrode on the non-doped amorphous silicon layer, and a second step on the resist layer and the non-doped amorphous silicon layer. Forming an insulating layer, and removing the resist layer and the second insulating layer on the resist layer by a lift-off method to form an island-shaped structure of the second insulating layer in a region corresponding to the opening. Process and forming an impurity-doped amorphous silicon layer on the non-doped amorphous silicon layer exposed by the lift-off method And a method for manufacturing an amorphous silicon thin film transistor.