JPH0675825A - Computer system - Google Patents

Abstract

PURPOSE:To provide the computer system provided with a means for recording various information at the time when a time-out error is generated, so that its recorded data can be referred to at any time. CONSTITUTION:In the computer system constituted by connecting mutually plural electronic circuit boards by a system bus 11, this system is provided with an access time measuring circuit 3 for outputting a time-out error signal, in the case there is no response reaction within a prescribed time form an accessed electronic circuit board with respect to an access to the electronic circuit board, and a time-out resistor 4 for recording a state of a system bus at the time when a time-out error is generated, so that it can be read out at any time. In such a way, since various information at the time when the time- out error is generated can be recorded and referred to at any time, the cause at the when the time-out error is generated is analyzed quickly and easily, and the measures can be performed surely to the time-out error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which a plurality of electronic circuit boards such as memories and I / O ports which are shared resources are interconnected by a system bus, and more particularly, it is connected to the system bus. The present invention relates to a recording means for recording the state of a system bus when a time-out error occurs in an electronic circuit board.

[0002]

2. Description of the Related Art A timeout error means that there is no response reaction to a shared resource such as a memory or an I / O port connected to a system bus from the accessed shared resource within a predetermined time. .

Conventionally, there are few examples in which a time-out error is detected in a computer system adopting a system bus system. Further, even in a system which detects a time-out error, the occurrence of the time-out error is only reported to each accessed board. However,
Regarding the occurrence of a timeout error when accessing the internal bus, if a method that enables the interrupt signal with the highest priority when a timeout error occurs is adopted, software processing can only know the target address where the timeout error occurred. It is possible, but the detection including the error situation was not considered. Therefore, a computer system that records various bus information when a timeout occurs and tries to use it for error analysis is
Virtually none.

[0004]

In the conventional system, there is no consideration for recording various kinds of information regarding a timeout error that occurs when accessing the shared resource connected to the system bus, and what kind of cause occurs when the timeout error occurs. There was no way to find out if the error occurred in.

An object of the present invention is to provide a computer system equipped with means for recording various information when a time-out error occurs so that the recorded data can be referred to at any time.

[0006]

The above object can be achieved by providing a time-out register for recording various information of the system bus when a time-out error occurs.

That is, in order to achieve the above object, the present invention provides a computer system in which a plurality of electronic circuit boards such as memories and I / O ports which are shared resources are interconnected by a system bus. Access time measurement means that outputs a time-out error signal when there is no response from the accessed electronic circuit board within a predetermined time from the accessed electronic circuit board, and the status of the system bus when a time-out error occurs can be read at any time The present invention proposes a computer system provided with a time-out error recording means for recording.

The state of the system bus recorded when a time-out error occurs is as follows. Board with timeout error b. Address on system bus c. Board that has acquired the system bus d. It is at least one of the control signals (read signal, write signal, etc.).

[0009]

In the present invention, when a time-out error occurs, various information is recorded in the time-out register at the first edge of the time-out error. Once a timeout error occurs, a secondary timeout error may occur. Therefore, once the timeout error register is set, the data is not updated until it is reset. The data recorded in the time-out register is read out and referred to at any time.

[0010]

1 is a block diagram showing the configuration of an embodiment of a computer system including a time-out error occurrence state recording device for a system bus according to the present invention. CP
The address signal used by U1 is the local address bus 5
And is input to the system bus 11 via the buffer 8 and the system bus 11. The data signal of the CPU 1 is output to the system bus 11 or input from the system bus 11 via the local data bus 6 and the buffer 9. The control signal of CPU1 is
It is output to the system bus 11 or input from the system bus 11 via the local control bus 7 and the bus control circuit 10. A decoder 13 is connected to a part of the local address bus 5. The decoder 13
In response to the address signal on the local address bus 5, the system request signal 13a, the timeout register selection signal 13b, etc. are output. The arbitration circuit 2 accesses the system arbitration bus 12 in response to the system request signal 13 a output from the CPU 1 via the decoder 13.
When the access right is output and the access right is obtained from the system arbitration bus 12, the buffer 8
Access valid signal 2a to buffer 9 and bus control circuit 10
Is output. The access time measuring circuit 3 includes a decoder 13
System request signal 13a from system and system arbitration bus 12
When the time from the system request to the completion of the response is longer than a predetermined time, it is determined that a time-out error has occurred, and the time-out error signal 3a is output to the time-out register 4.

The CPU 1 outputs an address signal to the local address bus 5 and the local control bus 7 in order to issue a read request to the electronic circuit board as a shared resource which is considered to be on the system bus 11. Decoder 1
3 inspects the address signal on the local address bus 5, and when it determines that the address is allocated on the system bus, it enables the system request signal 13a.
When the system request signal 13a becomes valid, the arbitration circuit 2
Outputs the access request signal 12a and continues to wait until the access permission signal 12b becomes valid. On the other hand, at the same time that the access request signal 12a becomes valid, the access time measuring circuit 3 also starts operating. When the access permission signal 12b becomes valid, the arbitration circuit 2 outputs the access valid signal 2a, and the local address bus 5, local data bus 6, and local control bus 7 are connected to the system bus 11. After that, when the response completion signal 11a from the target shared resource, that is, the accessed electronic circuit board is taken into the access time measuring circuit 3, the CPU 1 reads the data and ends the operation. At this point, the arbitration circuit 2
Invalidates the access request signal 12a. The access time measuring circuit 3 finishes the measurement and resets the measured time.

Although the above is the case where the access is normally completed, in the above description, when the access permission signal 12b is not valid within a predetermined time after the access request signal 12a is valid, or If the response completion signal 11a is not valid within a predetermined time after the valid signal 2a is valid, a time-out error occurs. When a time-out error occurs, the access time measurement circuit 3
Outputs the timeout error signal 3a to the timeout register 4. The timeout register 4 records the information of the system bus 11 at the timing of the first edge of the timeout error signal 3a. Although not shown here, since the time-out error signal 3a is connected to the interrupt line having the highest priority, the time-out error occurrence is C
Reported to PU1. When the CPU 1 detects from this report that a time-out error has occurred, it reads the contents of the time-out register 4, obtains various information when the time-out error occurs, issues an alarm for necessary treatment, issues a treatment instruction, or Treat yourself.

[0013]

According to the present invention, various kinds of information when a time-out error occurs can be recorded and referred to at any time, so that the cause of time-out error can be analyzed quickly and easily.
It is possible to take reliable measures against a timeout error.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a computer system including a system bus timeout error occurrence state recording device according to the present invention.

[Explanation of symbols]

 1 CPU 2 Arbitration circuit 2a Access valid signal 3 Access time measurement circuit 3a Timeout error signal 4 Timeout register 5 Local address bus 6 Local data bus 7 Local control bus 8 Buffer 9 Buffer 10 Bus control circuit 11 System bus 11a Response completion signal 12 System Arbitration bus 12a Access request signal 12b Access permission signal 13 Decoder 13a System request signal 13b Timeout register selection signal

Claims (2)

[Claims] 1. A computer system comprising a plurality of electronic circuit boards such as memories and I / O ports, which are shared resources, interconnected by a system bus, and access to any one of the electronic circuit boards is accessed. Access time measuring means for outputting a time-out error signal when there is no response reaction from the electronic circuit board within a predetermined time, and time-out error recording means for recording the state of the system bus at the time of occurrence of the time-out error in a readable manner at any time. A computer system comprising: 2. The computer system according to claim 1, wherein the state of the system bus recorded when the time-out error occurs comprises: a. Board with timeout error b. Address on system bus c. Board that has acquired the system bus d. A computer system characterized by being at least one of control signals (read signal, write signal, etc.).