JPH0338753A - System using bus - Google Patents

Abstract

PURPOSE:To improve the throughput of a system by detecting the access of an area having no address assigned by a processor as an error and ending a bus cycle in a short time. CONSTITUTION:A comparator 3 holds the address assignment information, and the address of an access given from a processor 2 is supplied to the comparator 3 together with a strobe signal AS showing that the address is valid. Thus the comparator 3 compares the address assignment information on a memory 5 with the address outputted onto a bus by the timing of the strobe signal. When the address of the area except the address assigned area of the memory 5 is produced, the comparator 3 outputs a signal ADE showing an access error to the processor 2. Then the processor 2 ends the relevant cycle and carries out an error process. Thus a bus cycle is ended in a short time. Thus, the system throughput is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus cycle control technology and a technology that is effective when applied to a method of forming a bus cycle end signal in a system using an asynchronous bus. For example, it relates to technology that is effective when used in processors and microcomputer system boards that can serve as bus masters.

[Prior Art] Memory and Ilo access methods based on processor control in a system using a bus include periodic access in which the access cycle ends in a fixed period, and semiconductor memory to be accessed. There is an asynchronous access that waits for a response from a device or input/output device and completes the cycle.

By the way, in asynchronous access, when an area to which no address has been allocated by the processor is accessed, there is no device to respond to the access from the processor, and as a result, the processor cannot complete the cycle.

As a countermeasure, conventionally, a bus monitoring device with a timer that is sufficiently slower than the access time of the device connected to the processor is installed on the bus, and if there is no response for a certain period of time, the cycle is forcibly terminated. The bus cycle was terminated using methods such as bus timeout.

Regarding the monitoring method of asynchronous buses,
rVMEbu published by VME MEMBER on October 20th
s Architecture Manual Revision C,
It is described on pages 35 and 36 of IJ.

[Problems to be Solved by the Invention] In asynchronous access, when accessing an area to which no address has been assigned by the processor, a method in which a bus monitoring device generates a bus timeout and forcibly terminates the cycle does not allow the processor to access the area. The time from the start of the process until the bus monitoring device finishes it must be made sufficiently larger than the response time of the device with the slowest access time of all the devices connected to the processor, so the system throughput is There was a problem with the decline.

An object of the present invention is to provide a bus cycle control technique that can detect an access by a processor to an area to which no address has been assigned as an error, complete the bus cycle in a short time, and improve system throughput. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In systems where peripheral devices are not allocated across the entire area that the processor can access, all or part of the area is accessed during initial settings such as reset, and address allocation is performed by acquiring information and setting it in registers. , Address assignment is performed by providing information from ROM or by initial setting by a program, and the set address assignment is determined by comparing the information with the address accessed under the control of the processor and determining whether the address assignment has not been done. A control means is provided which detects access to the area and instructs the microprocessor to complete the bus cycle.

The above control means may or may not be included in the processor, but if the control means is not included in the processor, the response signal input terminal and the error information input terminal of the processor are used for cycle termination and error indication. This can be achieved by supplying a control signal.

[Operation] According to the above-mentioned means, when the processor accesses an area to which no address has been assigned, the control means detects that there is no device to respond to, sends a response to the processor, and terminates the cycle. By indicating an error, the above-mentioned access error can be detected within a fixed short period of time, regardless of the access time of various peripheral circuits.

[Embodiment] FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a microcomputer system board using an asynchronous bus. Although not particularly limited here, a relatively small-scale system consisting of a microprocessor and memory is taken as an example.

In FIG. 1, l is a microprocessor, which includes a processor 2 that performs the operations of a conventional microprocessor, and a comparison circuit 3 that stores address allocation information 5 of the processor 2 and compares it with addresses on the bus when accessed by the processor. The comparator circuit 3 responds to the processor 2 with an error based on the result of the comparison and ends the cycle.
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A memory 5 is connected to the microprocessor 1 via an address bus ADR, and the upper addresses of the address buses A and DR are connected to a memory interface circuit 6, which receives a strobe signal AS indicating that the address buses A and D R are valid. Based on this, a memory selection signal C8 is formed. Furthermore, the memory interface circuit 6 receives response signals DTACK and BE when the processor 2 accesses the memory 5.
An RR is created and returned to the processor 2.

Furthermore, a bus monitoring controller 4 is connected to the address bus ADR and the data bus, and it determines whether the bus cycle is executed normally and returns a bus error signal BERR and error information to the microprocessor 1 when there is an abnormality. It has become.

In the system shown in FIG. 1, there are signals necessary for memory access such as a data bus and a read/write signal indicating the direction of data, but these are omitted here because they are not directly related to the present invention.

Next, the operation of the above system will be explained.

When the processor 2 accesses the memory 5, it first outputs an address assigned to the memory to the address bus ADR, and then outputs a strobe signal AS indicating that the address is valid to the memory 5 and the memory interface circuit 6. .

Then, the memory interface circuit 6 generates a selection signal C8 to the memory 5 and supplies it to the memory 5, while sending a response signal DA to the processor 2 when the operation of the memory 5 is completed.
It outputs TCK or BERR to request completion of this access cycle.

This response indicates that when the access cycle is completed normally, DTACK is returned.By returning BERR when the access cycle is completed, the processor 2 can determine whether the access cycle is normal or abnormal.

Therefore, in this embodiment, in accessing the memory 5 from the processor 2, when the processor 2 accesses an area of the memory 5 to which no address has been allocated, the memory interface circuit 6 does not generate the selection signal C8, and the processor 2 DTACK and BE, which are response signals for
RR will not be output. Therefore, the processor 2 does not know when the cycle has ended, and this cycle is extended forever. However, in general, a bus monitoring controller monitors the bus and forcibly terminates the bus cycle if there is no access response for a long period of time. It has a timeout function and is designed to terminate the cycle via BERR.

7 In contrast, in this embodiment, since the comparison circuit 3 that holds information regarding address allocation is provided, the address accessed by the processor 2 and the slobe signal AS indicating that the address is valid are compared. The address assignment of the memory 5 compares the information with the address output on the bus at the timing of the signal supplied to the circuit 3, and when an address outside the area occurs, the address assignment of the memory 5 is compared. The circuit 3 outputs a signal ADE indicating an access error to the processor 2. Then, processor 2 ends the cycle and executes error handling.

Figure 2 shows the timing. After the address is output from the processor 2, when the address strobe signal AS is changed to low level, the comparator circuit 3 outputs the address from the address bus A.
The address on the DR is fetched and the internal address assignment is compared with the information. If they match, the detection signal ADE is changed to low level to notify the processor 2 of an access error.

According to this embodiment, when the microprocessor 1 accesses, the comparator circuit 3 detects the access of the processor 2 to an area to which no address is assigned, and requests the processor 2 to complete the cycle and handle the error in a lost time. It can be done without.

Although there are no particular restrictions on the information regarding the address allocation in the comparator circuit 3 that is compared with the address on the bus, the processor 2 may store all or part of devices such as memory at the time of initialization such as reset, that is, at the time of initialization. The address assignment may be accessed to obtain information and set in a register in the comparator circuit 3, or may be set by an initialization program. Alternatively, it may be provided as a non-volatile ROM. The first method provides the most flexibility when the system is expanded.

As the address allocation number information, the upper few bits of the address indicating the unallocated address area of the memory may be used.

Furthermore, in the above embodiment, the address allocation was explained in which the information comparison circuit 3 was provided in the processor 2.
The comparison circuit 3 may be configured as a circuit external to the processor 2. In that case, it is preferable to provide a comparison circuit for address allocation information in the bus monitoring controller 4, and to return a bus error signal BERR if an access violation is detected.

As explained above, in the above embodiment, in a system in which no peripheral devices are assigned to the entire area accessible by the processor, all or part of the area is accessed during initial settings such as reset, and address assignment is performed using information. For address assignment, information is provided by ROM or initialized by a program, and the set address assignment is used to connect information and addresses accessed under the control of the processor. In comparison, we have provided a control means that detects access to an area to which no address has been assigned and instructs the microprocessor when to end the bus cycle, so if the processor accesses an area to which no address has been assigned, it should respond. The control means detects the absence of the device, responds to the processor, terminates the cycle, and instructs an error, so that the above access can be performed in a fixed short period of time, regardless of the access time of various peripheral circuits. This has the effect that errors can be detected and system performance is improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the system of the above embodiment, only the memory is connected to the microprocessor via a bus, but an I10 device, a slave processor, etc. may also be connected.

Also, the bus monitoring controller can be built into the microprocessor.

In the above explanation, the invention made by the present inventor was mainly applied to a single board computer, which is the background field of application, but the invention is not limited thereto, It can be used in general systems connected to hardware called a backplane and other systems using a synchronous bus.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a system where no devices are assigned to the periphery of the entire area that can be accessed by the processor, it is possible to detect an access error in an area to which no address has been assigned by the processor, and terminate the bus cycle in a short time, thereby increasing system throughput. can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a microcomputer system, and FIG. 2 is a timing diagram showing an example of the operation when accessing a memory. 1... Microprocessor, 2... Processor, 3... Comparison circuit, 4... Bus monitoring controller, 5... Memory, 6... Memory interface circuit, ADR. ...Address bus, C8...Memory selection signal, AS...Address valid signal, DAT
GK: Normal access response signal, BERR: Abnormal access response signal, ADE: Address error signal.

Claims (1)

[Claims] 1. In a system using an asynchronous bus, the system includes address allocation information setting means, and compares an address output when accessed by a processor with preset address allocation information, A system using a bus, characterized by comprising control means for detecting access to an area to which no address has been assigned and for instructing a processor to terminate a bus cycle. 2. The bus according to claim 1, wherein the address allocation information setting means acquires and sets accessible area information by the processor accessing all or part of the address area during initial setting. system using. 3. A system using a bus according to claim 1, wherein said address allocation information setting means is constituted by a non-volatile memory.