JPH067385Y2 - Interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an interface circuit, and more particularly to an interface circuit for performing mutual conversion between a serial digital modulation signal and a parallel digital signal.

[Conventional technology]

Conventionally, there is a memory card that stores information such as game software and can be removed from a personal computer or the like.

As shown in FIG. 4, the conventional memory card has a plurality of control terminals 10, a plurality of address terminals 11, and a plurality of data terminals 1.
2 and the like, these terminals are connected to the memory 13, and the terminals 10 to 12 are used by connecting to the bus line of the personal computer.

[Problems to be solved by the invention]

In the configuration of FIG. 4, many terminals are required on the memory card,
There is a problem that a multi-pin connector is required for a personal computer equipped with a memory card.

In order to reduce the number of pins of the memory card, it is possible to serially transmit control signal, address, and data information. In this case, in order to block and transmit the information, synchronization information is added to the beginning of each block as shown in FIG. 5 (A), digital modulation is performed, and a signal as shown in FIG. 5 (B) is transmitted. .

In FIG. 5 (A), 2 for synchronization are provided at the beginning of each block.
An initial frame composed of an initial bit and a start bit and a control bit R / of 1 bit for read / write instruction is provided, and then a data frame composed of an address of 12 bytes and data of 128 bytes is provided. . The above block is NRZ-modulated to obtain the waveform shown in FIG.

However, as shown in FIG. 5, if the same bit pattern as that of the initial frame is generated in the data frame when the entire blocked information is transmitted by NRZ modulation, the bit of the initial frame in the data frame is received on the receiving side. When a pattern is detected, it is erroneously discriminated as the beginning of a block, and there is a problem that erroneous synchronization occurs.

The present invention has been made in view of the above points, and an object of the present invention is to provide an interface circuit that prevents mutual synchronization from occurring and performs mutual conversion between a serial digital modulation signal and a parallel digital signal.

[Means for solving problems]

In the present invention, the first conversion circuit performs NRZ modulation so that a predetermined number of bytes of an address or a data frame of address and data is inverted at the center of a bit after a signal in which an initial frame for synchronization is NRZ modulated for each block. A second modulated signal different from that is supplied with a continuous serial information signal to convert the second modulated signal of the data frame into an NRZ modulated signal.

The second conversion circuit converts the NRZ modulated signal output from the first conversion circuit into parallel address or data of an address and a predetermined bit unit and outputs the data.

The third conversion circuit is supplied with data of a predetermined bit unit and converts the data into an NRZ-modulated signal of a serial data frame of a predetermined number of bytes.

The fourth conversion circuit converts the NRZ modulation signal output from the third conversion circuit into a second modulation signal, adds the NRZ modulation signal of the initial frame before the conversion signal, and serially outputs the signal.

[Action]

In the present invention, the serial digital modulation signal can be converted into a parallel digital signal by the first and second conversion circuits, and the parallel digital signal can be converted into a serial digital modulation signal by the third and fourth conversion circuits. Can be converted.

Also, the digital modulation signal has an initial frame of NR.
Since the data frame is Z-modulated and the data frame is second-modulated, the same waveform pattern as the modulation signal waveform of the initial frame does not exist in the modulation signal waveform of the data frame, and the occurrence of erroneous synchronization can be prevented.

〔Example〕

 FIG. 1 shows a block diagram of an embodiment of the circuit of the present invention.

First, the information signal used for transmission in the circuit of the present invention will be described. The information signal is in data block units as shown in FIG. Each data block is shown in Fig. 2 (B).
As shown in FIG. 5, the initial frame and the data frame have exactly the same structure as FIG. 5 (A). In this data frame block, as shown in FIG. 2C, an initial frame is NRZ (non-return zero) modulated and a data frame is PE (phase encoding) modulated.

The NRZ modulation is a modulation in which a "1" bit is at an H level and a "0" bit is at an L level. Since this modulated signal is a serial digital signal itself, there is no need for special demodulation. PE modulation is a modulation in which a "1" bit is a falling edge at the center of a data bit and a "0" bit is a rising edge at the center of a data bit.
Mutual conversion with the modulated signal is very simple.

In FIG. 1, the information signal Din is input to the terminal 20,
A clock CLK having a bit period rising at the boundary of each bit shown in FIG.

The above information signal Din is supplied to the initial frame detector 22, and the presence or absence of the signal waveform of FIG. 2 (C) corresponding to a total of 4 bits including the initial bit and the start bit is detected here, and the detected signal is timed. It is supplied to the generator 23. Further, the detector 22 supplies the information signal Din to the reformatter 24, the error detector 25, and the read / write controller 26. The timing generator 23 generates various timing signals by using the clock signal CLK after being reset by the detection signal, and supplies the timing signals to each part of the circuit.

The reformatter 24, which is the first conversion circuit, is instructed by the timing signal to start the data frame,
The PE modulation signal which is the data frame in the information signal Din is converted into the NRZ modulation signal. The error detector 25 generates a reset signal when the data frame has a bit pattern that cannot be a PE modulation signal, as indicated by the timing signal, and supplies the reset signal to all circuits. The read / write controller 26 takes out the control bit R / in the initial frame according to the instruction of the timing signal, and according to the value, write enable ▲ ▼ and read enable ▲
▼, each of the chip select is generated and the terminals 27a ...
Output from 27c. The NRZ modulated signal of the data frame output from the reformatter 24 is converted into an 8-bit parallel signal by the serial / parallel converter 28 which is the second conversion circuit.

When the control bit R / is "0" and the write mode is set, the address of the first 2 bytes (16 bits) of the parallel signal is generated by the address counter 2 by the timing signal.
The data of the following 128 bytes is sequentially latched in the data register 30 in byte units by the write / enable and the timing signal. The address counter 29 sequentially counts up for each byte of data according to the timing signal, and the above 16-bit address and 8-bit data are output from terminals 31 and 32, respectively.

When the control bit R / is "1" and the read mode is set, the 128-byte data in the data frame is ignored and only the address is output from the terminal 31 as in the write mode. As a result, 8-bit unit data sequentially read from the memory described later is latched in the data register 33 by the read enable signal and the timing signal.

The data output from the data register 33 is converted into a serial signal by the parallel / serial converter 34, which is a third conversion circuit, and is supplied to the formatter 35. This serial signal has the same waveform as the NRZ modulation signal. The formatter 35 converts the NRZ modulated signal into a PE modulated signal and outputs the PE modulated signal according to the instruction of the timing signal.

The formatter 35, which is the fourth conversion circuit, is an H level output until conversion is instructed by the timing signal, and this becomes an initial bit. Further, the start bit generator 36 generates a start bit of H level for 2 bits according to the read enable signal and the timing signal. As a result, an information signal composed of the initial frame of the NRZ modulated signal and the data frame of the PE modulated signal is output from the terminal 37.

FIG. 3 shows a block diagram of an embodiment of a memory card to which the circuit of the present invention is applied. The memory card 20 includes an interface circuit 41 shown in FIG. 1 and a memory 42. The terminal 27a of the interface circuit 41-
27c and 31, 32 are connected to the memory 42,
Writing and reading of the memory 42 are performed. The terminals 20, 21, and 37 of the interface circuit 41 are used by being connected to, for example, a personal computer or the like via the terminals 44a to 44c of the memory card 40.

In this way, by providing the interface circuit 41, the terminals for external connection of the memory card are the terminals 44a to.
44c and the power supply terminal are sufficient, and the number is reduced as compared with the conventional case.

In addition, since the information signal is modulated differently between the initial frame and the data frame, the waveforms of the initial bit and the start bit for synchronization in the modulated signal of the initial frame do not exist in the modulated signal of the data frame, and erroneous synchronization occurs. Is prevented from occurring.

The data frame of the information signal is not limited to the PE modulation signal and may be a modulation signal such as FM modulation which is inverted at the center of the bit, and is not limited to the above embodiment.

[Effect of device]

As described above, according to the interface circuit of the present invention,
Mutual conversion between a serial digital modulation signal and a parallel digital signal can be performed without the occurrence of false synchronization. For example, when applied to a memory card, the number of external connection terminals of the memory card can be reduced, which is extremely useful in practice. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the circuit of the present invention, FIG. 2 is a diagram for explaining information signals used for transmission in the circuit of the present invention, and FIG. 3 is an implementation of a memory card to which the circuit of the present invention is applied. An example block diagram, FIG. 4 is a block diagram of an example of a conventional memory card, and FIG. 5 is a diagram for explaining an information signal of a conventional serial communication. 22 ... Initial frame detector, 23 ... Timing generator, 24 ... Reformatter, 28 ... Serial / parallel converter, 29 ... Address counter, 30,
33 ... Data register, 34 ... Parallel / serial converter, 35 ... Formatter, 36 ... Start bit generator, 41 ... Interface circuit, 42 ... Memory.

Claims (1)

[Scope of utility model registration request] 1. A second modulation different from NRZ modulation so that a predetermined number of bytes of an address or a data frame of address and data is inverted at the center of a bit after a signal in which an initial frame for synchronization is NRZ modulated for each block. A first conversion circuit for converting the second modulation signal of the data frame into an NRZ modulation signal by being supplied with a continuous serial information signal, and an NRZ modulation signal output from the first conversion circuit A parallel address or a second conversion circuit for converting the address into an address and data in a predetermined bit unit and outputting the data, and NRZ modulation of the data in a predetermined number of bytes supplied with the data in the predetermined bit unit. A third conversion circuit for converting the NRZ modulated signal output from the third conversion circuit into the second modulated signal, N of the initial frame before
An interface circuit including a fourth conversion circuit for adding an RZ modulation signal and outputting the serially.