JPS59206934A - Serial interface circuit - Google Patents

Abstract

PURPOSE:To simplify a serial interface circuit composed of N-bit shift registers by omitting a counter circuit, by using an (N+1)-bit shift register and setting the output of the first register to a specific one. CONSTITUTION:The reset signal 20 of a serial interface (SIFC) is connected to the S-terminal of a shift register (SR)21 and the R-terminal of SRs 22-29. The output of the SR29 becomes a serial data transfer completion signal 12 and the signal 12 is connected with an internal circuit 13. To initialize an interface circuit, the output of the SR21 is set to H and outputs of the SRs 22-29 are set to ''4'', by setting the reset signal 20 to H. When serial data are received, the SR21 reads the data at the first rise of a clock signal SCK and the SR22 reads the output H of the SR21. The output of the SR22 becomes H. The H is shifted to the SR23 at the next clock SCK and the transfer of the serial data is terminated when the SR29 becomes H at the 8th clock SCK. Therefore, a counter circuit can be omitted and, as a result, the circuit configuration can be simplified.

Description

[Detailed description of the invention] The present invention relates to serial interface circuits.

Conventionally, parallel interface circuits and serial interface circuits have been known as interface circuits for transferring data between microcomputers and their peripheral devices. The former sends data in parallel, so in order to send N bits of data, at least N+ signal lines are required for sending N signal lines and control signals.
One signal line is required, and in a microcomputer, if the data bus line or input/output port is dedicated for these, it becomes one (1).On the other hand, in a serial interface circuit, the signal line is divided in a time-sharing manner. In integrated circuits, if a serial interface circuit is used, only two signal lines are required: a signal line for carrying data and a signal line for control. It is very commonly used because it can reduce the number of data. However, since serial interface circuits send data in a time-division manner, the data receiving side has to synchronize with the control signal sent via the control signal line. It also requires a circuit to convert serial data into parallel data, which has the disadvantage of making the circuit more complex than a parallel interface circuit.Especially with conventional serial interface circuits, In order to check whether the data transfer of N bits is completed, a counting circuit is provided to count the data transfer circuit, and when the data transfer is completed N times, a transfer end signal is generated to make the data usable. Figure 1 shows a conventional example of an 8-bit serial interface circuit of this type.

In FIG. 1, shift 1/registers 1 to 8 read input data at the rising edge of the CK multiplier signal, and output the input data to the Q terminal. 9 is the serial data signal and is the D of 1.
The Q outputs of 1 to 7 are connected to the D terminals of 2 to 8, respectively.
connected to the input.

10 is a clock signal for synchronizing serial data (hereinafter 80
(abbreviated as "signal") and is connected to the CK terminals 1 to 8. 11 is a counting circuit which generates a transfer end signal 12 at the 1008th rising edge of the signal 80, and internal circuit 13.
Notify the user that the data is ready for use. In this type of system, an 8-bit serial interface circuit requires a 3-bit counter to generate the data transfer end signal, making the circuit significantly more complex than a para-1 nor interface circuit. There was a drawback.

An object of the present invention is to provide a serial interface circuit that can be realized with a simpler circuit configuration than conventional serial interface circuits.

According to the present invention, an N-bit data transfer end signal can be generated in an N-bit serial interface circuit without using a counting circuit, so the circuit can be significantly simplified compared to a conventional serial interface circuit. be able to.

Next, one embodiment of the present invention will be described using FIG. 2.

20 is a reset signal for the serial interface circuit, which is connected to the set terminal of shift register 21 and the reset terminal of shift 1/registers 22 to 29, and the output of shift register 29 is the serial data transfer end signal 1.
2 and is connected to the internal circuit 13. FIG. 3 is a timing diagram of this circuit. First, in order to initialize the interface circuit, the reset signal 20 of the serial interface circuit is set to 'H', the output of the shift register 21 is set to 'H', and the output of the shift register 21 is set to 'H'. Set the output of 29 to “L”. (Figure 3a) When serial data is received in this state, the shift register 21 reads the first bit of serial data 9 at the first rising edge of the signal at 80, and at the same time the shift register 22 reads the output of the shift register 21. , the output of the shift register 22 becomes 0H''. Since all the input data of the shift 1 registers 23 to 29 are reset to ``L'', the output also becomes ``L'' level.

Similarly, the 'H' output of the shift register 22 is 'Temata signal 1'.
0 is synchronized with the rising edge of signal 10 and shifted to the next stage shift register, and at 80, at the 8th rise of signal 10, 6H" is output to the Q output of shift register 29. In this state, shift registers 21 to 29 28 is the data from the 1st bit to the 8th bit of the serial data being transferred.Therefore, the Q output of the shift register 29 can be used as the data transfer end signal, and the internal circuit 13 can transfer the data of the interface circuit. After use, if the reset signal 20 of the interface circuit is set to H'' again to initialize the interface circuit, the next serial data can be received.

Therefore, by using the present invention, there is no need for a counter circuit for generating a data transfer end signal, and the serial interface circuit can be greatly simplified. 1
In serial interface circuits in which P1 has multiple bits or the number of data bits is not in the 2H series, counter circuits are generally complex, so a great effect can be obtained.

[Brief Description of the Drawings] Figure 1 is a diagram showing a conventional example of a serial interface circuit, Figure 2 is a diagram showing an embodiment of the present invention, and Figures 6-3 are diagrams showing a detailed explanation of the present invention. It is a diagram. 1-8, 21-29...Shift register, 9.
...Serial data input terminal, 10...
Serial clock input, 11... Counter circuit, 12... Data transfer end signal, 13...
. . . Internal circuit, 20 . . . Initialization signal for interface circuit. 71

Claims (1)

[Claims] An N-bit serial interface circuit configured with shift 17 registers has an N+1-bit shift 1/register, and the output of the shift register to which serial data is first input is set to a constant value t-%, It is characterized by comprising means for setting the output of another shift register to a value different from that of the shift 1 register to which the serial data is first input, and means for testing the output t of the N+1-th shift 1 register. serial interface circuit.