JP2002198944A - Serial signal transmitting unit, information processing system and serial signal transmitting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit serially a sending data of more than 2 bites constitution efficiently without increasing the number of transmitting lines. SOLUTION: In this system, a clock data generating circuit 35 outputs a bit-sequence of '1, 0, 0, 0, 0, 0, 0, 0' as a clock information when a lower rank bite is designated by a byte position signal, and outputs a bit-sequence of '1, 1, 0, 0, 0, 0, 0, 0' as a clock information when a higher rank bite is designated by a byte position signal. Thus it enables to restore the bytes constitution sent serially with transmitting clock accurately from the clock information at the receiving-side by transmitting serially two kinds of bit-sequence having the same period and the different duty ratio selectively by adjusting to the byte position of a serial data s38 transmitted serially through a shift register 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a serial signal transmission device for realizing a high-speed serial interface, an information processing system using the same, and a serial signal transmission method.

[0002]

2. Description of the Related Art In recent years, various portable computers which can be operated by a battery have been developed. Some of these types of portable computers are
Some are configured so that they can be mounted on expansion units as needed. In order to enable the portable computer to make effective use of the resources of the expansion unit, it is important to connect the bus of the computer body to the bus in the expansion unit. This bus connection allows devices on the bus in the expansion unit to be handled in the same way as devices in the portable computer body.

In many portable computers, a PC
An I bus (Peripheral Component Interconnect Bus) is used. Therefore, the bus connection between the computer main body and the expansion unit is performed by providing docking connectors having a number of pins corresponding to the number of signal lines of the PCI bus on the computer main body side and the expansion unit side, respectively. This is usually done by physically connecting the two PCI buses via a PC.

However, this configuration requires a large area for mounting the docking connector, which is disadvantageous in reducing the size and thickness of the computer main body. Further, since the connector mounting positions on the computer main body side and the expansion unit side must be matched, when developing a new product, the physical housing structure is restricted.

[0005]

From such a background,
Development of a technique for transferring a transaction between the PCI buses by a high-speed serial interface has been demanded. By using the high-speed serial interface, it is possible to connect the computer main unit and the expansion unit with a thin and flexible serial cable.

In realizing a high-speed serial interface, it is necessary to transmit clock information indicating transmission timing of serial data together with serial data. In this case, at least two types of transmission lines are required: a data transmission line for transmitting serial data and a clock transmission line for transmitting clock information. Further, when serial transmission of transmission data having a 2-byte configuration or more is performed, information indicating the byte position of the serial data being transmitted is transmitted through another transmission path so that the reception side can restore the correct byte configuration. Alternatively, it is necessary to convert the transmission data into serial data in byte units and serially transmit using different data transmission paths for each byte position.

However, when either method is used, the number of transmission lines increases, which causes problems such as an increase in the serial cable width.

The present invention has been made in view of the above-mentioned circumstances, and efficiently transmits transmission data of a 2-byte configuration or more without increasing the number of transmission lines by improving the transmission method of clock information. It is an object of the present invention to provide a serial signal transmission device, an information processing system, and a serial signal transmission method that are capable of performing the above.

[0009]

In order to solve the above-mentioned problems, a serial signal transmission device according to the present invention converts parallel data into serial data, and converts the serial data into a first data.
Serial data transmitting means for serially transmitting the data through the transmission line, and n times (n
> 1) generating a plurality of types of bit strings having different periods with respect to each other as clock information indicating timing synchronized with the serial transmission of the serial data. Clock information transmitting means for selectively transmitting serially the plurality of types of bit strings via a second transmission path in accordance with a byte position.

This serial signal transmission device has a cycle of n times (n> 1) the transmission clock so that the receiving side can correctly restore the byte configuration of the transmission clock and the transmission data from the clock information. A plurality of types of bit strings having different duty ratios are generated as clock information. Then, the plurality of types of bit strings are selectively transmitted in accordance with byte positions of serial data to be serially transmitted. By using a mechanism to add byte information to clock information and transmit it,
It is possible to efficiently transmit transmission data of 2 bytes or more without increasing the number of transmission lines.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a serial signal transmission device according to one embodiment of the present invention. Hereinafter, the configuration will be described by exemplifying a case where the personal computer (PC) main body 100 and the extension unit 200 are connected using the serial transmission line 300 formed of a cable. The serial transmission path 300 includes a transmission path for data transfer and a transmission path for clock transfer.

The PC main body 100 is provided with a transmission device for serially transmitting parallel data of 16 bits (1 word). This transmission device performs serial transmission in synchronization with a multiplied clock s36 of a transmission reference clock s31. As shown in the figure, a selector 31, a latch circuit 32, a shift register 33, a byte data decision circuit 34, a clock data Generation circuit 35, latch circuit 3
6, a shift register 37, a PLL 38, and a timing signal output circuit 39.

The selector 31 receives the lower byte data (L) s 32 and the upper byte data (H) s33 constituting the 16-bit (one word) parallel data to be transmitted, alternately selects and outputs them. I do. This selection is performed based on the L and H byte position signals alternately output from the byte data determination circuit 34 in synchronization with the transmission reference clock s31. The latch circuit 32 includes the selector 3
The 8-bit data of the upper or lower byte selected by 1 is latched in synchronization with the transmission reference clock s31, and the 8-bit latch data s34 is output to the shift register 33.

The shift register 33 converts parallel data from the latch circuit 32 into serial data and transmits the data serially.
The latch data is fetched in synchronization with the timing signal s37 obtained by step 9, and is transmitted serially in synchronization with the multiplied-by-8 clock s36 from the PLL.

The byte data determination circuit 34 is a circuit for outputting a byte position signal indicating a byte data position at which serial data is to be transmitted, based on the transmission reference clock s31. In the case of the present embodiment, either the lower byte or the upper byte may be designated, so that it can be realized by a single toggle flip-flop.

The clock data generating circuit 35 is for generating clock information of a cycle corresponding to the reference clock s31. When the lower byte is designated by the byte position signal, for example, "1, 0, 0, 0" , 0,0,0,
A bit string of "0" is output as clock information, and when an upper byte is designated by a byte position signal, for example, a bit string of "1, 1, 0, 0, 0, 0, 0, 0" is output as clock information. .

The latch circuit 36 latches the 8-bit clock information output from the clock data generation circuit 35 in synchronization with the transmission reference clock s31, and outputs the 8-bit latch data s35 to the shift register 37.

The shift register 37 converts parallel data s35 from the latch circuit 36 into serial data and transmits the serial data serially. The timing signal s37 obtained by the timing signal output circuit 39 is provided.
Fetches the latch data s35 in synchronization with
The data is serially transmitted in synchronization with the octupled clock s36 from L38.

The PLL 38 generates an eight-multiplied clock s36 as a transmission clock from the transmission reference clock s31. The timing signal output circuit 39 outputs an eight-multiplied clock s
36 and divides the parallel data into the shift register 3
A timing signal s37 for giving a timing to load to the third and the third 37 is generated. Also, the timing signal s37
Is input to the PLL 38 as a signal for performing a phase comparison with the transmission reference clock s31.

The receiving device provided on the docking station 200 side includes a shift register 4 as shown in FIG.
1, a latch circuit 42, an upper byte latch circuit 43, a lower byte latch circuit 44, a shift register 45, a latch circuit 47, a decoder 47, a PLL 48, and a timing signal output circuit 49.

The shift register 41 stores the serial data s
The serial data s38 is sequentially fetched in synchronization with the octupled clock s3a obtained by the PLL 48. The latch circuit 42 is a circuit for converting serial data fetched by the shift register 41 into parallel data and holding the parallel data.

The upper byte latch circuit 43 and the lower byte latch circuit 44 are circuits for holding and outputting upper byte data and lower byte data, respectively.
When the upper / lower byte identification signal s3d output from is "1" (upper byte), the reception reference clock s3g
At the rise of the parallel data s from the latch circuit 42
3c, and the lower byte latch circuit 44 outputs the upper / lower byte identification signal s output from the decoder 47.
When 3d is "0" (lower byte), the parallel data s3c from the latch circuit 42 is latched at the rise of the reception reference clock s3g.

The shift register 45 is for taking in clock information s39 transmitted serially.
Clock information s39 is sequentially taken in synchronism with the octupled clock s3a obtained by LL48. Latch circuit 4
Reference numeral 6 converts and holds the clock information captured by the shift register 45 into parallel data.

The decoder 47 decodes the bit string of the clock information output from the latch circuit 46 to identify the byte information of the transmitted data. In this embodiment,
When the bit string of the clock information output from the latch circuit 46 = “1,1,0,0,0,0,0,0”, the upper / lower byte identification signal s3d = “1”, and the bit string of the clock information = When “1,0,0,0,0,0,0,0”,
It outputs the upper / lower byte identification signal s3d = "0".

The PLL 48 is for generating an eight-multiplied clock s3a from the serially transmitted clock information s39, detects an edge (bit “1”) of the clock information s39, and detects one cycle of the detected edge. / 8
An eight-multiplied clock s3a having a double cycle (frequency is eight times) is output. In this case, serially transmitted clock information s
A phase comparison is performed at the rising edge of 39, and the phase adjustment of the falling edge of the 8-multiplied clock s3a is performed. The phase of the eight-multiplied clock s3a is adjusted so that the fall of the eight-multiplied clock s3a matches the serially transmitted clock information s39 from “0” to “1”.

The timing signal output circuit 49 is a circuit that receives an eight-multiplied clock s3a and outputs a timing signal s3b and a reception reference clock s3g from the eight-multiplied clock s3a.

FIG. 2 shows two types of bit strings s39 serially transmitted as clock information (clock data).
And the relationship with the octupled clock s3a restored on the receiving side.

As described above, the two types of bit strings “1, 0,
0,0,0,0,0,0 "and" 1,1,0,0,
0, 0, 0, 0 "have a cycle of T and only a different duty when the time series change of the serial signal is observed. Thus, the PLL 48 on the receiving side.
In this case, even if the bit string of “1, 0, 0, 0, 0, 0, 0, 0” or “1, 1, 0, 0, 0, 0, 0, 0” is transmitted, the serial data The octupled clock s3a, which is the transmission clock of, can be obtained correctly.

Also, "1,0,0,0,0,0,0,
Decoding the byte structure of serially transferred data by identifying which bit string of “0” or “1,1,0,0,0,0,0,0” was transmitted by the decoder 47 Can be.

Next, the operation of the serial signal transmission device of FIG. 1 will be described with reference to the timing chart of FIG.

In the first section from "Phase" 1 to 8, lower byte data (L) s32 is selected by selector 31 and is latched by latch circuit 32 at the rise of reference clock s31. The data is sent to the shift register 33 as s34. Continue,
In a section indicated by “Phase” 1 to 8, the upper byte data (H) s33 is selected by the selector 31 and is latched by the latch circuit 32 at the rise of the reference clock s31, and is shifted as the latch data s34 into the shift register 33. Sent to

From the shift register 33, the lower byte data (0 to 7) and the upper byte data (8 to 15) are sequentially transmitted as a serial data string s38 in synchronization with the multiplied clock s36.

At the time of serial transmission of lower byte data (0 to 7), "1, 0, 0, 0, 0, 0,
Clock information s39 consisting of a bit sequence of “0, 0” is sequentially transmitted, and at the time of serial transmission of the upper byte data (8 to 15), simultaneously with “1, 1, 0, 0, 0,
Clock information s39 consisting of a bit string of 0, 0, 0 "is sequentially transmitted.

The serial data string s38 is sequentially converted into parallel data in 8-bit units via a shift register 41 and a latch circuit 42, and is output from the latch circuit 42 as latch data s3c.

When the lower byte data (L) is output as the latch data s3c, "1, 0, 0, 0,
Clock information s3 consisting of a bit string of 0, 0, 0, 0 "
9 is decoded by the decoder 47, whereby the upper / lower byte identification signal s3d becomes "0". Therefore, the lower byte data (L) is latched by the lower byte latch circuit 44 at the timing of the reference clock s3g, and is output as the lower byte data s3f.

When the upper byte data (H) is output as the latch data s3c, "1, 1,
The decoder 47 decodes the clock information s39 composed of a bit string of 0, 0, 0, 0, 0, 0 ",
The upper / lower byte identification signal s3d becomes "1". Therefore, the upper byte data (H) is latched by the upper byte latch circuit 43 at the timing of the reference clock s3g,
It is output as upper byte data s3e.

As described above, by selectively transmitting two types of bit strings having the same cycle and different duty ratios as clock information in accordance with the byte position of the serial data, the receiving side uses the clock information to transmit a transmission clock and a serial transmission signal. It is possible to correctly restore the byte configuration of the data to be obtained. Therefore, it is possible to serially transmit one word of parallel data with a clock eight times the transmission reference clock without increasing the number of data transmission paths.

It should be noted that the PLL of 8 times as in this embodiment is used.
Is used as the bit string for the clock information generated by the clock data generation circuit 35 as shown in FIGS.
As shown in (g), “1,0,0,0,0,0,0,0” “1,1,0,0,0,0,0,0” “1,1,1,0 , 0,0,0,0 "" 1,1,1,1,0,0,0,0 "" 1,1,1,1,1,0,0,0 "" 1,1,1, It is possible to use seven patterns of 1,1,1,0,0 "" 1,1,1,1,1,1,1,0 ". Therefore, up to 7 bytes of parallel data can be serially transmitted on one data transmission line.

When an n-times PLL is used, parallel data consisting of a maximum of n × (n−1) bits can be transmitted through one data transmission line.

In this embodiment, only the transmission from the computer to the extension unit has been described. However, since data is actually transmitted and received in both directions, the transmission device is provided to each of the computer and the extension unit. And a receiving device. Furthermore, the present embodiment can be suitably used not only for signal transmission between the computer main unit and the extension unit, but also for signal transmission between the host device and the peripheral device if the information processing system includes the host device and its peripheral devices. It is possible.

The parallel / serial conversion need not necessarily be performed in byte units, but can be performed in arbitrary units.

Further, the above-described embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

[0043]

As described above, according to the present invention,
By improving the transmission method of clock information, it becomes possible to efficiently transmit transmission data of a 2-byte configuration or more without increasing the number of transmission lines.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a serial signal transmission device according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing a relationship between clock information used in the serial signal transmission device of the embodiment and a transmission clock restored on the receiving side.

FIG. 3 is a timing chart showing the operation of the serial signal transmission device of the embodiment.

FIG. 4 is an exemplary view showing a pattern of a bit string of clock information which can be used in the serial signal transmission device of the embodiment.

[Explanation of symbols]

 Reference Signs List 31 selector 32 latch circuit 33 shift register 34 byte data determination circuit 35 clock data generation circuit 36 latch circuit 37 shift register 38 PLL 39 timing signal output circuit 41 shift register 42 latch circuit 43 Upper byte latch circuit 44 Lower byte latch circuit 45 Shift register 46 Latch circuit 47 Decoder 48 PLL 49 Timing signal output circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (reference) // G06F 5/00 G06F 5/00 S

Claims (9)

[Claims] 1. A serial data transmitting means for converting parallel data into serial data and serially transmitting the serial data via a first transmission line, wherein the serial data transmitting means is n times (n> 1) a transmission clock of the serial data. A plurality of types of bit strings having periods and different duty ratios are generated as clock information indicating timing synchronized with the serial transmission of the serial data, and are aligned with byte positions of serial data serially transmitted by the serial data transmitting unit. And a clock information transmitting means for selectively transmitting the plurality of types of bit strings serially through a second transmission path. 2. The parallel data comprises upper byte data and lower byte data, and the clock information transmitting means has a cycle of n times (n> 1) a transmission clock of the serial data, and First and second bit strings having different duty ratios are generated, the first bit string is serially transmitted at the time of serial transmission of the upper byte data, and the second bit string is serially transmitted at the time of serial transmission of the lower byte data. The serial signal transmission device according to claim 1, wherein: 3. Clock generating means for receiving the clock information via the second transmission line, and generating a clock signal having a cycle of 1 / n times a bit string constituting the clock information, Determining means for determining the type of a bit string constituting the data stream; receiving serial data transmitted via the first transmission path using a clock signal generated by the clock generating means; 2. The serial signal transmission device according to claim 1, further comprising: means for converting the received serial data into byte-aligned parallel data based on the result. 4. Each of a plurality of types of bit strings constituting the clock information has a first bit and a last bit at least logically inverted, and the clock generation means detects an edge of the bit string of the received clock information, 4. The serial signal transmission device according to claim 3, wherein a clock signal having a period that is 1 / n times the period of the detected edge is generated. 5. A serial data transmitting means for converting parallel data into serial data and serially transmitting the serial data via a first transmission path, and a byte position of serial data serially transmitted by said serial data transmitting means. In accordance with the above, a plurality of types of bit strings having the same cycle and different duty ratios from each other are
A serial signal transmission device comprising: clock information transmitting means for selectively transmitting serially via a second transmission path as clock information necessary for restoring a transmission clock of the serial data. 6. An information processing system including a host device and a peripheral device used for expanding the function of the host device, wherein parallel data to be transmitted from one of the host device and the peripheral device to the other is transmitted. One of the host device and the peripheral device via a first transmission line in a serial transmission line for connecting the host device and the peripheral device to the serial data; Serial data transmitting means for serially transmitting the serial data from the device to the other receiving device; a plurality of types of bit strings having a cycle n times (n> 1) of the transmission clock of the serial data and different duty ratios from each other; Is generated as clock information indicating the timing synchronized with the serial transmission of the serial data. A clock for selectively transmitting the plurality of types of bit strings from the transmitting device to the receiving device via a second transmission path in the serial transmission path in accordance with a byte position of serial data to be transmitted. Information transmitting means, for receiving the clock information transmitted from the transmitting side device via the second transmission path, and generating a clock signal having a period of 1 / n times a bit string constituting the clock information. A clock generation unit; a determination unit for determining a type of a bit string constituting the clock information; and a clock generated by the clock generation unit to convert serial data transmitted from the transmission-side device via the first transmission path. And receiving the serial data based on the result of the determination by the determination means. The information processing system characterized by comprising a means for converting the Rudeta. 7. A serial signal transmission method for converting parallel data into serial data and transmitting the serial data, wherein the parallel data is converted into serial data, and the serial data is serially transmitted via a first transmission path. Serial data transmission step; and clock information indicating timings of synchronizing a plurality of types of bit strings having a cycle n times (n> 1) of the serial data transmission clock and different duty ratios with the serial transmission of the serial data A clock information transmitting step of selectively transmitting the plurality of types of bit strings serially via a second transmission path in accordance with a byte position of serial data serially transmitted by the serial data transmitting step; Receiving the clock information via the second transmission path,
A clock generation step of generating a clock signal having a period of 1 / n times a bit string constituting the clock information; a discrimination step of discriminating a type of the bit string constituting the clock information; Receiving the serial data transmitted by using the clock signal generated in the clock generating step, and converting the received serial data into byte-aligned parallel data based on the determination result in the determining step. And a serial signal transmission method. 8. An output unit for converting first data having a first data width into second data narrower than the first data width and outputting the second data, and for transmitting the second data. A plurality of types of bit strings having a cycle that is a predetermined multiple of that of the transmission clock and having different duty ratios are generated as clock information indicating timing synchronized with the data transmission of the second data, and the second bit string is output by the output unit. A signal transmission unit for selectively transmitting the plurality of types of bit strings in accordance with a predetermined timing position of the second data. 9. An output step of converting first data having a first data width into second data narrower than the first data width and outputting the second data, and transmitting the second data. A plurality of types of bit strings having a cycle that is a predetermined multiple of the transmission clock and having different duty ratios are generated as clock information indicating timing synchronized with the data transmission of the second data, and the second bit string is output by the output step. A clock information transmitting step of selectively transmitting the plurality of types of bit strings in accordance with a predetermined timing position of the second data.