JPH0673389B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention is applied to a case where a semiconductor element having a large difference in height such as an optical semiconductor element and a normal semiconductor element is integrated on the same substrate. The present invention relates to a method of manufacturing a semiconductor device that can obtain good results.

2. Description of the Related Art In recent years, optical semiconductor devices such as laser diodes and ordinary semiconductor devices such as field effect transistors are combined and formed on the same substrate.

FIG. 1 is a cutaway side view of a main part of such a semiconductor device.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs active layer, 3 is an n ⁺ -type GaAs buffer layer, 4 is an n-type AlGaAs glad layer, 5 is an n-type GaAs active layer, and 6 is p. Type AlGaAs clad layer, 7 p-type GaAs contact layer, 8 n-side contact electrode, 9 p-side contact electrode, 10 source electrode, 11 drain electrode, 12 gate electrode, LD laser diode part, FT Is a field effect transistor part, S1 is a laser
The total thickness of the semiconductor layer in the diode portion LD, S2 is n
The respective thicknesses in the type GaAs active layer 2 are shown.

FIG. 2 shows an equalization circuit diagram of the semiconductor device shown in FIG. 1, and the same parts as those described with reference to FIG. 1 are designated by the same symbols.

The thickness S1 of the entire semiconductor layer in the laser diode portion LD in this conventional example is about 5 to 10 [μm], and the n-type in the field effect transistor portion FT.
Since the thickness S2 of the GaAs active layer 2 is about 0.3 [μm], if both are directly formed on the surface of the same substrate, the step difference will be extremely large.

Therefore, in this conventional example, a part of the semi-insulating GaAs substrate 1 is removed to form a recess having a depth corresponding to the thickness of the laser diode portion LD, and the laser diode portion LD is formed in the recess. And the field effect transistor portion FT outside the recess, that is, on the original surface of the semi-insulating GaAs substrate 1.
Are formed, and the entire surface is made substantially flat.

In this way, although the difficulty of the photoresist process is alleviated, when the recess is formed by the conventional technique, the sloped surface in the recess is formed in a considerably raised state. The wiring connecting the laser diode portion LD and the field effect transistor portion FT may be broken.

FIG. 3 is a cutaway side view of a main part showing another conventional example.
The same parts as those described with reference to FIGS. 2 and 2 are designated by the same symbols.

In this conventional example, since the laser diode portion LD and the field effect transistor portion FT are formed on the same surface of the semi-insulating GaAs substrate 1, there is a problem of disconnection like the conventional example shown in FIG. Does not occur, but because of the remarkable step,
The photoresist process is difficult, and in particular, it is difficult to form a fine pattern required for the field effect transistor portion FT.

As described above, it is an unavoidable problem that the conventional technique is more difficult to manufacture and deterioration of characteristics caused by the difficulty.

By the way, the formation of the recess in the conventional example described with reference to FIG. 1 has a significant relation to the present invention, and therefore will be described in more detail here.

FIG. 4 to FIG. 8 are side sectional views of a semiconductor device at a main part of a process for explaining a case where a recess is formed according to a conventional technique. Hereinafter, these drawings will be referred to. While explaining.

See Fig. 4 (a) For example, molecular beam epitaxy growth (molecular)
beam epitaxy (MBE) is applied to grow an n-type GaAs active layer 22 on a semi-insulating GaAs substrate 21.

(B) For example, the silicon dioxide (SiO ₂ ) film 23 is formed to a thickness of, for example, about 4000 [Å] by applying a sputtering method.

See FIG. 5 (c) The silicon dioxide film 23 is patterned by a normal photolithography technique to form an opening 23A on the region where the recess is to be formed.

See FIG. 6 (d) Semi-insulating GaAs using the silicon dioxide film 23 as a mask
The substrate 21 is patterned to form the recess 24. still,
It goes without saying that the depth of the recess 24 is determined in consideration of the height of the laser diode portion. In addition, when performing this patterning, 8H ₂ O ₂ + 1H is used as an etchant.
₂ SO ₄ + 1H ₂ O is used.

See FIG. 7 (e) After removing the silicon dioxide film 23 used as the mask and putting it in the state shown in the figure, various processes are carried out to complete the semiconductor device.

See FIG. 8 (f) This figure shows a state in which a photoresist film 25 is formed in order to carry out one of the processes.

Now, when the wiring is formed, the angle θ of the inclined surface in the recess 24 shown in FIG. 7 formed as described above becomes 45 ° or more, and the edge has a sharp bend. In that case, disconnection is likely to occur at the edge. Further, as shown in FIG. 8, when the photoresist film 25 is formed, the edge portion, that is, the portion indicated by the arrow A is thin, and the portion formed by the arrow B is thick. Therefore, uniform processing becomes impossible.

FIGS. 9 to 11 further explain the inconvenience of the recess formed in the steps described with reference to FIGS. 4 to 8. FIG. 9 is a plan view of relevant parts, and FIG. 9 is a sectional view taken along the line aa 'seen in FIG. 9, and FIG. 11 is a sectional view taken along the line bb' seen in FIG. 9, respectively, and the portions described with reference to FIGS. The same parts are designated by the same symbols, and the symbols 24A and 24A 'indicate inclined surfaces.

Generally, in the case of manufacturing a semiconductor device, it is often advantageous to use a surface having a surface index of (100) as a main surface in terms of characteristics when the semiconductor device is completed.

Therefore, assuming that the main surface of the semi-insulating GaAs substrate 21 shown in FIG. 9 is (100) and the recess 24 is formed, the line a-
The plane seen in Fig. 10 cut at a'is (01 1 ),
It becomes the plane (011) seen in FIG. 11 taken along the line bb '.

As can be understood from the drawings, the (01 1 ) plane has the same cross-sectional shape as the recess 24 described in FIGS. 4 to 8, but the (011) plane has a so-called reverse taper. It has a cross-sectional shape.

Therefore, it is clearly impossible to draw out the wiring in the direction parallel to the (011) plane.

In the above-mentioned prior art, in the example of forming the recess in the substrate, the step generated by the recess is left as it is.

However, it is thought that anyone would think that if a semiconductor layer is grown and filled in such a recess, the surface will be flat and the step will be eliminated.

However, in the case where the edge has a sharp bend, such as the recess formed by the above-mentioned conventional technique,
Good embedding of the semiconductor layer cannot be expected.

12 to 14 are side sectional views of essential parts of a semiconductor device in a process key point for explaining an example of a conventional technique for burying a semiconductor layer in a recess. Hereinafter, these figures will be referred to. While explaining. The same parts as those described with reference to FIGS. 4 to 11 are designated by the same symbols.

See FIG. 12 (a) A recess 24 is formed in the substrate 21 through a process similar to the process described with reference to FIGS. 4 to 6.

See FIG. 13 (b) The semiconductor layer 26 is grown by applying an appropriate epitaxial growth method.

See FIG. 14. (c) The unnecessary portion of the semiconductor layer 26 on the surface of the substrate 21 is mechanically removed by, for example, lapping or chemically removed by etching, and the semiconductor layer 26 is recessed 24 as shown in the figure. To be embedded inside.

According to the above-mentioned technique, the uniformity in the wafer and the manufacturing yield are poor, which is not practical.

FIG. 15 to FIG. 17 are side sectional views of a main part of a semiconductor device in a process key point for explaining another example of the conventional technique of embedding a semiconductor layer in a recess. The description will be made with reference.

See FIG. 15. (a) The recess 24 is formed in the substrate 21 by taking steps similar to the steps described with reference to FIG.

(B) A mask film 27 made of a suitable material having an opening, for example, SiO _2, is formed on the recess 24.

See Fig. 16 (c) Liquid phase epitaxy
The semiconductor layer 26 is grown by applying a selective epitaxial growth method utilizing the y: LPE method or the like, and then the mask film 27 is removed.

An abnormal growth portion 26 'is formed at the edge of the semiconductor layer 26 grown here.

(D) The anomalous signs 26 'are removed by applying the chemical etching method.

According to the above-described technique, it is difficult to flatten the surface by etching only the abnormal growth portion 26 ′ that occurs when the semiconductor layer 26 is formed, and as shown in FIG. Since the etched portion 21A is formed and problems such as wiring cutting occur, the manufacturing yield is reduced.

As can be seen from the above description, it is difficult for the prior art to planarize the recess by filling it with a semiconductor layer.

It is an object of the present invention to form a semiconductor element having a large difference in height on the same substrate, and to connect the semiconductor elements with a wiring by using a so-called planar type semiconductor device. Prevents disconnection of wiring connecting elements.

According to the method for manufacturing a semiconductor device according to the present invention, a step of forming a mask pattern having an inclined surface at an end on a semiconductor substrate, and anisotropic etching in the vertical direction on the entire surface of the substrate A step of transferring the mask pattern to form a low substrate surface which is continuous on the semiconductor substrate through a step portion composed of a surface and an inclined surface; and a multi-layer semiconductor layer structure is grown on the entire surface of the substrate including the low substrate surface. A step of forming a mask pattern having an inclined surface on the lower substrate surface, and an anisotropic etching in the vertical direction on the entire surface of the substrate to form the multilayer semiconductor layer structure in the lower substrate surface. A step of transferring the mask pattern and removing the other multilayer semiconductor layer structure on the surface of the substrate, and an optical semiconductor device having a multilayer semiconductor layer structure formed in the lower substrate surface. A step of forming a semiconductor element on the surface of the substrate, the optical semiconductor element and the semiconductor element on the inclined surface formed on the substrate and on the inclined surface formed in the multilayer semiconductor layer structure. And a step of forming a wiring layer for connecting the wirings are included.

According to this configuration, for example, a high-height semiconductor element such as a laser diode is formed on a low substrate surface, and a low-height semiconductor element such as a field effect transistor is formed on the substrate surface. Even if the connecting wiring is provided, no disconnection occurs, and it is easy to make both surfaces flat, that is, a planar type.

FIG. 18 to FIG. 20, FIG. 23, and FIG. 24 are side sectional views of a main part of a semiconductor device in a process key point for explaining an embodiment of the present invention. A description will be given with reference to the drawings.

See FIG. 18. (a) A photoresist film 32 is formed on a semi-insulating GaAs substrate 31.

As the photoresist used here, for example, AZ13
50 (manufactured by SHIPLEY, USA) can be used.

(B) The photoresist film 32 is patterned to form an opening 32A having a gentle slope 32B.

As described above, a method of forming the opening 32A having the sloping inclined surface 32B will be described in detail later.
A has a great influence on the baking in the next step (c).

(C) Baking is performed under the conditions of a temperature of 200 [° C.] and a time of several [minutes].

Normally, the baking temperature of the photoresist film is 12
About 0 [° C.] is selected, but in the case of the present invention, the above-mentioned baking temperature is adopted because of the necessity of forming the gently sloping surface 32B.

See FIG. 19 (d) Ion etching method using argon (Ar) ions, that is, sputter etching method is applied, etching is performed until the photoresist film 32, which is a mask, is almost entirely sputtered and left. By removing the photoresist film, a low substrate surface 31C that is continuous with the surface 31A of the semi-insulating GaAs substrate 31 via a step portion 31B that is a gently sloping surface is formed. That is, the recess 31 'is obtained.

Such etching utilizes the difference in etching rate between the photoresist film 32 and the semi-insulating GaAs substrate 31, and as described above, argon ions are used and the acceleration energy is 500 [eV]. In that case, the etching rate of GaAs with respect to the photoresist can be changed depending on the incident angle of the ion beam with respect to the surface of the substrate, and can be increased by about 4 times.

The angle θ formed by the step portion 31B formed as described above and the surface 31A can be about 16 °.

See Fig. 20 (e) MBE method, MOCVD (metal organic chemical vapor)
A multilayer semiconductor layer 33 is grown by selecting an appropriate technique such as a deposition) method or a liquid phase epitaxial growth method.

Here, the semiconductor layer 33 is composed of, for example, 5 to 6 layers, and is composed of semiconductor layers necessary for forming a laser diode, such as a buffer layer, a clad layer, an active layer, a clad layer, and a cap layer. It is configured. However, for the sake of simplicity, it is shown in a single layer state in FIG.

See FIG. 23. (f) A recess formed in the substrate 31 on the surface of the semiconductor layer 33.
Since there is a recess in which 31 '(see FIG. 19) has been transferred, a mesa-shaped photoresist film 34' is formed in the recess.

In order to form the photoresist film 34 ', the photoresist can be spin-coated on the entire surface and then patterned by applying the technique adopted in the step (b). The details will be described later, as described above.

See FIG. 24. (g) As in the step (d), by applying the sputter etching method using argon ions, etching is performed until the photoresist film 34 ′ is entirely sputtered. As shown, a mesa-shaped semiconductor layer 33 is formed in the recess.

The semiconductor layer 33 thus obtained functions as a laser diode if electrodes are formed, and
It is also easy to form a field effect transistor on the original surface of the substrate 31.

In the present invention, since emphasis is placed on the independence of the semiconductor layer, for example, the semiconductor layer 33 found in the embodiment, the semiconductor layer 33 is formed in a mesa shape in the recess, but if such consideration is not required, It is also possible to form the semiconductor layer 33 on the entire surface in the recess, and a reference example in that case will be described below. However,
Such a structure is not the subject of the present invention.

FIG. 21 and FIG. 22 are side sectional views of essential parts of the semiconductor device in process steps for explaining the reference example, which will be described below with reference to these drawings.

See FIG. 21. (h) After the steps described with reference to FIG.
On the surface of 33, there is a recess in which the recess 31 'formed in the substrate 31 is transferred, and therefore a photoresist film 34 is formed to fill the recess.

To form the photoresist film 34, the photoresist film is spin-coated on the entire surface and then patterned by applying the technique adopted in the step (b). The exposure and the like in this case will also be described in detail later.

See FIG. 22. (i) Similar to the step (d), by applying a sputter etching method using argon ions, etching is performed until the photoresist film 34 is almost entirely sputtered and left. When the photoresist film is removed,
As shown in the figure, the multi-layer semiconductor layer 33 remains only in the recess 31 ′ of the substrate 31 and the rest is removed.

FIG. 25 and FIG. 26 are a plan view and a side cut view of a main part for representing a recess formed in a substrate by applying the present invention,
The same parts as those described with reference to FIGS. 18 to 24 are designated by the same symbols.

According to the present invention, the cutting side surface of the main part shown in FIG. 26 can be obtained by cutting along either line aa 'or line bb' in FIG.

As is apparent from the figure, regardless of the plane orientation of the substrate 31, even when viewed from a direction different by 90 °, it is found that the low substrate surface 31C is continuous with the substrate surface 31A via the gentle step portion 31B. This is a major difference from the prior art described with reference to FIGS. 9 to 11, and therefore, according to the present invention, the wiring can be drawn out in four directions of the recess 31 '.

Therefore, if the recess 31 'is formed in a circular shape instead of a square shape, the wiring can be pulled out in any direction of 360 °.

FIG. 27 and FIG. 28 are a plan view and a sectional side view of a main part showing an embodiment in which the recess 31 ′ is circular, and FIGS.
The same parts as those described with reference to the drawings are designated by the same symbols.

As shown in the figure, the circular low substrate surface 31C is continuous with the entire substrate surface 31A via the slight step portion 31B.

Here, a method of forming the photoresist films 32, 34, 34 'described with reference to FIGS. 18, 21, and 23 will be described.

29 and 30 are sectional side views of essential parts of a semiconductor device or the like at process steps for explaining the case of forming a photoresist film having a gently inclined surface at the edge.

In FIG. 29, 41 is a semi-insulating GaAs substrate, 42 is a positive photoresist film, 43 is a glass mask, 43A is a mask pattern, 44 is ultraviolet rays, and G _P is a gap.

As can be seen, the photoresist film 42 and the glass
When ultraviolet rays 44 are irradiated with an appropriate gap G _P between the mask 43 and the mask 43, so-called pattern blurring occurs at the edge of the mask pattern 43A, and underexposure occurs at that portion. As shown in FIG. 30, when developed with, a recess 44 having a gentle inclined surface 42A is formed.

FIG. 31 is a sectional side view of an essential part of a semiconductor device at a process key point for explaining a technique different from the exposure method described with reference to FIG. 29, and the same parts as those described with reference to FIG. 29 are the same. It is indicated by a symbol.

In the figure, 45 is a positive type electron beam resist film, 46 is a dense electron beam, and 47 is a sparse electron beam.

When irradiating the electron beam / resist film 45 shown in the drawing with an electron beam, the dense electron beam 46 is radiated to the portion where the resist film 45 is to be left completely, and the portion where a gentle inclined surface is to be formed is sparse. The electron beam 47 is irradiated so that the portion where the resist film 45 is to be completely removed is not irradiated with the electron beam.

When the resist film 45 irradiated with the electron beam with the exposure amount changed in this way is developed, the same pattern as the pattern having the gentle inclined surface 42A and the recess 44 shown in FIG. 30 is formed.

FIG. 32 is a side sectional view of an essential part of a semiconductor device in a process key point for explaining a technique different from the exposure method described with reference to FIGS. 29 and 31, and with respect to FIGS. 29 and 31. The same parts as those described are designated by the same symbols.

In the figure, 48 is a dielectric film made of, for example, silicon dioxide, and 49 is a mask made of metal.

In this example, a mask 49 made of a metal is arranged from the substrate 41 through an appropriate gap G _P , and a dielectric film 48 is formed by applying a sputtering method. One having 48A and a recess 44 is obtained.

Next, an example of forming a recess having a gently sloping surface by utilizing the difference in etching rate depending on the crystal composition will be described.

Figure 33 shows x value and etching rate in Al _X Ga _1-X As
It is a diagram showing the relationship with RT _E.

As can be seen from the figure, with Al _X Ga _1-X As, the etching rate RT _E also increases with increasing x value.

By utilizing this phenomenon, a gently sloping surface can be formed in the Al _X Ga _1-X As layer.

34 to 36 are side sectional views of a main part of a semiconductor device in process steps for explaining the embodiment, which will be described below with reference to these drawings.

See Fig. 34 (a) By applying MBE method or MOCVD method, GaAs
On the substrate 51, as the value x increases gradually, Al _X G
The a _1-X As layer 52 is formed to have a thickness of, for example, about 10 μm.

See FIG. 35. (b) A mask film 53 made of photoresist, silicon dioxide, silicon nitride or the like is formed on the surface of the Al _X Ga _1-X As layer 52.

(C) The mask film 53 is patterned by applying a normal photolithography technique to form stripe openings 53A in the <011> direction.

(D) Hydrofluoric acid-based etching solution, for example, HF: CH ₃ CO
When the Al _X Ga _1-X As layer 52 is etched using OH: H ₂ O ₂ : H ₂ O = 0.5: 2: 1: 1 or HF: HNO ₃ : H ₂ O = 1: 3: 2. , The higher the Al content, the higher the etching rate, so that a recess 54 having a sloping slope 52A is obtained, as shown in the figure.

Following removal of Figure 36 refer to (e) mask film 53, depending on the etching the entire surface using an isotropic etchant, Al _X Ga _1-X As
When the layer 52 is completely removed, the recess 54 is transferred to the GaAs substrate 51 to form a recess 55 having a gentle slope 51A.

From the above description, it can be understood that, according to the present invention, it is easy to form a recess having a gently sloping surface in a substrate.

This embodiment is characterized in that a chemical etching method can be applied to form the recess 54.

FIG. 37 is a fragmentary side view showing a semiconductor device for explaining a reference example, and this reference example is manufactured by using the technique of the reference example described with reference to FIGS. 21 and 22.

In the figure, 61 is a semi-insulating GaAs substrate, 62 is a recess, 62A is an inclined surface of the recess 62, 63 is an n-side contact layer, 64 is an n-side cladding layer, 65 is an active layer, and 66 is a p-side. Clad layer, 67 p-side contact layer, 68 active layer of field effect transistor portion FT, 69 p-side contact electrode, 70 source electrode, 71 drain electrode, 72 gate electrode, 73 insulating film, 74 Is wiring,
75 is the n-side contact electrode, L _D is the depth of the recess 62, L _S is the recess
The width of the inclined surface 62A at 62 is shown.

Various data in the constituent elements of the semiconductor device are as follows.

The depth L _D for the recess 62: 10.2 [μm] width L _S of the inclined face 62A: 30 [μm] for n-side contact layer 63 semiconductor: n ⁺ -type GaAs impurity concentration: 1 × 10 ¹⁸ [cm ^-3] thickness Thickness: 5 [μm] About n-side clad layer 64 Semiconductor: n-type Al _0.3 Ga _0.7 As Impurity concentration: 5 × 10 ¹⁷ [cm ^-3 ] Thickness: 2 [μm] About active layer 65 Semiconductor: n-type GaAs Impurity Concentration: 1 x 10 ¹⁷ [cm ^-3 ] Thickness: 0.2 [μm] About p-side cladding layer 66 Semiconductor: p-type Al _0.3 Ga _0.7 As Impurity concentration: 5 x 10 ¹⁷ [cm ^-3 ] Thickness: 2 [ μm] About p-side contact layer 67 Semiconductor: p ^{+ R} type GaAs Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 1 [μm] About active layer 68 Semiconductor: n type GaAs Impurity concentration: 1 × 10 ¹⁷ [cm ^-3] thickness: 0.3 [μm] for the p-side contact electrode 69 materials: materials for AuZn source electrode 70 and drain electrode 71: materials for AuGe / Ni gate electrode 72: the Al insulating film 73 material: dioxide silicon Wiring 74 material: Au / Cr n-side contact electrode 75 for the material: a step of manufacturing the semiconductor device shown in Au · Gu / Ni Figure 37 is as follows.

(A) The steps as described with reference to FIGS. 18 to 22 are used to form the recess 62, and then each semiconductor layer, that is,
n-side contact layer 63, n-side clad layer 64, active layer 65, p
The side clad layer 66 and the p-side contact layer 67 are grown, unnecessary portions of the respective semiconductor layers are removed, and only those filling the recess 62 are left.

Ion etching conditions for forming the recess 62 are: etchant: Ar gas atmosphere pressure: 2 × 10 ^-4 [Torr] acceleration energy: 500 (eV) beam injection method: 70 ° to the substrate surface, A positive photoresist was used as the mask, and the film thickness was 8 [μm].

(B) For example, the active layer 68 for forming the field effect transistor portion FT is formed by applying the MBE method.

(C) The p-side contact electrode 69 in the laser diode portion LD is formed by applying the lift-off method and the vapor deposition method.

(D) The source electrode in the field effect transistor part FT by applying the lift-off method and the vapor deposition method.
A 70 and a drain electrode 71 are formed.

(E) By applying the lift-off method and the vapor deposition method, the gate electrode in the field effect transistor portion FT
Forming 72.

(F) The insulating film 73 of silicon dioxide is formed by applying the sputtering method.

(G) Depending on the application of the lithographic technique, the insulating film
73 is patterned.

(H) The wiring 74 is formed by applying the lift-off method and the vapor deposition method.

(I) The n-side contact electrode 75 in the laser diode portion LD is formed by applying the lift-off method and the vapor deposition method.

The yield of the photoresist process in the reference example was extremely good, and a fine pattern could be easily formed.

As an example, it is easy to obtain a stripe width of 3 [μm] in the laser diode portion LD and a source-gate, gate-drain, gate width, etc. of the field-effect transistor portion FT of 2 [μm]. I was able to.

FIG. 38 is an equivalent circuit diagram of the semiconductor device shown in FIG. 37, and the same portions as those described with reference to FIG. 37 are designated by the same symbols.

FIG. 39 is a fragmentary side view showing an example of a semiconductor device having a configuration in which a laser diode portion LD and a field effect transistor portion FT are continuous via a gentle slope.
The same parts as those described with reference to FIG. 37 are designated by the same symbols.

In the process of manufacturing this semiconductor device, the process described with reference to FIGS. 23 and 24 can be used to form a gentle slope on each semiconductor layer in the laser diode portion LD. No extra steps are required when manufacturing the semiconductor device of
This is no different from the case of manufacturing the semiconductor device shown in FIG.

In each of the embodiments or reference examples, the active layer is grown on the semi-insulating GaAs substrate to form the field effect transistor portion FT, but as is often done,
The active region may be formed by ion-implanting a desired impurity into the semi-insulating GaAs substrate.

FIG. 40 is a fragmentary side view showing the reference example, and FIG.
The same symbols as those used in FIGS. 39 to 39 represent the same powders or have the same meanings. To manufacture the semiconductor device of this reference example, the technique of the reference example described with reference to FIGS. 21 and 22 is applied.

This reference example is largely different from the embodiments or reference examples described with reference to FIGS. 37 to 39, by applying the ion implantation method, and implanting Si ions into the semi-insulating GaAs substrate 61. , N-type active region 76, n ⁺ -type source region 77,
That is, the n ⁺ type drain region 78 is formed.

41 and 42 are side cutaway views of essential parts of a semiconductor device in process steps for explaining a reference example when manufacturing a semiconductor device in which a pin diode and a field effect transistor are combined, Hereinafter, description will be given with reference to these drawings. The technique of the reference example described with reference to FIGS. 21 and 22 is applied to this reference example.

See Fig. 41. (a) By applying the MBE method, a semi-insulating GaAs substrate 8
N ⁺ type GaAs layer 82, n ⁻ type GaAS layer 83, n ⁻ type Al _0.3 Ga _0.7 As
Grow layer 84.

The data regarding each semiconductor layer in this case are as follows.

About n ⁺ type GaAs layer 82 Impurity concentration: 5 × 10 ¹⁷ [cm ⁻³ ] Thickness: 0.3 [μm] About n ⁻ type GaAs layer 83 Impurity concentration: 5 × 10 ¹⁴ [cm ⁻³ ] Thickness: 3.5 [ μm] n ⁻ type Al _0.3 Ga _0.7 As layer Impurity concentration: 5 × 10 ¹⁴ [cm ⁻³ ] Thickness: 1 [μm] (b) Take steps as described with reference to FIGS. 18 to 22. , Forming a recess 85 having a gently sloping surface 85A.

In this case, the depth L _D of the recess 85 was 4.8 [μm], and the width L _S of the inclined surface 85A was 30 [μm]. The width L _S is 30 (μ
It is easy to set the thickness to m] or more and about 100 [μm].

(C) The semi-insulating GaAs layer 86 filling the inside of the recess 85 is formed by the steps described with reference to FIGS. 18 to 22.

(D) For example, by applying the MBE method, the n-type GaAs active layer 87 for forming the field effect transistor portion FT
To form.

The impurity concentration of the n-type GaAs active layer 87 is 1 × 10 ¹⁷ [cm ^-3 ].
The thickness and the thickness are about 0.3 μm.

(E) For example, the p-type diffusion region 88 having a diameter of about 100 [μm] is formed by applying an ion implantation method.

(F) By applying a normal technique, for example, Au.
A source electrode 89 and a drain electrode 90 made of Ge / Ni, an n-side contact electrode 91, a p-side electrode 92 made of AuZn, and a gate electrode 93 made of Al are formed.

See FIG. 42 (g) An insulating film made of silicon dioxide, for example, by applying a sputtering method and an appropriate lithography technique.
Forming 94.

(H) The wiring 95 made of Au / Cr is formed and completed by applying a vapor deposition method and an appropriate lithography technique.

FIG. 43 is an equivalent circuit diagram of a semiconductor device manufactured according to the reference example described with reference to FIGS. 41 and 42.

44 to 48 are side sectional views of a main part of a semiconductor device in process steps for explaining another embodiment, which will be described below with reference to these drawings.

See FIG. 44. (a) An insulating film 102 made of silicon dioxide or silicon nitride is formed in the <011> direction on a semi-insulating GaAs substrate 101 having a surface index of (100).

(B) The exposed partial surface of the semi-insulating GaAs substrate 101 is treated with an anisotropic etchant such as H ₂ SO ₄ : H ₂ O ₂ : H ₂ O = 1: 8: 1 for about 7 [ μm] to form the recess 103.

At this time, the etching rate is 8 [μm /
Minutes].

See FIG. 45. (c) After removing the insulating film 102, about 4 [minutes] of etching is performed using, for example, H ₂ SO ₄ : H ₂ O ₂ : H ₂ O 18: 1: 1 as an etchant. To do.

This second etching is extremely important, and accordingly, the edge of the recess 103 becomes a gently sloping surface 103A.

At this time, the etching rate is 0.8 [μm /
Minutes].

See Fig. 46 (d) By applying MBE method, n-side contact layer 1
04, n-side clad layer 105, active layer 106, p-type clad layer 10
7. The p-side contact layer 108 is continuously grown.

Various data in each of these semiconductor layers are as follows.

About n-side contact layer 104 Semiconductor: n ⁺ type GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 3 [μm] About n-side clad layer 105 Semiconductor: n type AlGaAs Impurity concentration: 3 × 10 ¹⁷ [ cm ^-3 ] Thickness: 1.5 [μm] About active layer 106 Semiconductor: n-type GaAs Impurity concentration: 1 × 10 ¹⁷ [cm ^-3 ] Thickness: 0.1 [μm] About p-side clad layer 107 Semiconductor: p-type AlGaAs Impurity concentration: 3 x 10 ¹⁷ [cm ^-3 ] Thickness: 1.5 [μm] About p-side contact layer 108 Semiconductor: p ⁺ type GaAs Impurity concentration: 1 x 10 ¹⁹ [cm ^-3 ] Thickness: 1 [μm] (E) Two mesas for each semiconductor layer formed in the recess 103.
Etching is performed to expose a part of the surface of the n-side contact layer 104.

See FIG. 47. (f) The buffer layer 109 and the active layer 110 are grown by applying the MBE method.

Various data on these semiconductor layers are as follows.

About buffer layer 109 Semiconductor: Undoped GaAs Thickness: About 0.7 [μm] About active layer 110 Semiconductor: n-type GaAs Impurity active: 1 × 10 ¹⁷ [cm ^-3 ] Thickness: 0.2 [μm] (g) Buffer A mesa etch is performed to isolate layer 109 and active layer 110 from the others.

See Fig. 48. (h) By applying the vapor deposition method and the lift-off method, the p-side contact electrode 111 in the laser diode portion LD and the source electrode 1 of the field effect transistor portion FT
12 and the drain electrode 113 and the n-side contact electrode 114 of the laser diode portion LD are formed.

Au / Zn / Au may be used for the p-side contact electrode 111, and heat treatment at a temperature of 450 ° C. for 5 minutes is performed.

Source electrode 112, drain electrode 113, n-side contact electrode
Au / Ge may be used for 114, and the temperature is 420 [° C] 1
[Minute] heat treatment is performed.

The heat treatments described above are performed in an N ₂ atmosphere.

(I) Wiring 1 that connects the field effect transistor portion FT and the n-side contact electrode 114 in the laser diode portion LD by applying the vapor deposition method and the lift-off method
Forming fifteen.

Cr / Au may be used for the wiring 115.

(J) By applying the vapor deposition method and the lift-off method, for example, the gate electrode 116 made of Al is formed.

Also in this embodiment, since the step has the gently sloping surface 103A, even though the photolithography process is performed about 10 times until the semiconductor device is completed, the shoulder portion of the step is No breakage of the resist occurs, and therefore there is no abnormal etching, residual wiring metal, or disconnection of the wiring at that portion.

FIGS. 49 (a) and 49 (b) show that when a recess having a gently sloping surface obtained by applying the present invention is filled with an epitaxially grown semiconductor layer, the thickness of the semiconductor layer is FIG. 3 is a diagram of data showing that the semiconductor device is uniformly maintained in the wafer and a side view of a main part of the semiconductor device. Incidentally, this data was measured by the data obtained in the examples described with reference to FIGS. 18 to 20, 23 and 24.

In FIG. 49 (a), the vertical axis represents the depth d of the recess, and the horizontal axis represents the distance l, where WA is the wafer and WA 'is a part of the wafer.

FIG. 49 (b) is an enlarged view of a part of the wafer WA ', where 121 is a semi-insulating GaAs substrate, 122 is an epitaxially grown semiconductor layer, 123 is a recess, and 123A is an inclined surface of the recess. Shown respectively. The width L of the inclined surface 123A in the recess 123 is
_S is -18 [μm].

This data is obtained by measuring the height d of the step including the epitaxially grown semiconductor layer 122 in the recess 123 at nine points on the line passing through the center of the wafer WA, and it is 6.7 ± 0.3.
[Μm] has been realized, and only a non-uniformity of ± 4.3 [%] is observed, which is an extremely large improvement as compared with the case of using the polishing method described with reference to FIGS. 12 to 14. Is.

Further, the above-mentioned measurement was carried out five times in a lot of two wafers for a total of ten wafers, and the uniformity was ± 5 [%] for all the wafers.
Within the range, the uniformity and the yield are good, and the data is similarly obtained for the depth of 10 [μm].

FIG. 50 is data showing how the dimensional accuracy and yield in the photoresist process are improved by the structure described with reference to FIG. 39. (a) is the angle θ of the slope in the sample and A diagram showing a relationship with a deviation from W ₀ which is a basic pattern width, (b) is a side view of a main part cut of a sample, (c)
[FIG. 3] is a plan view of an essential part of a sample.

In the figure, 124 is a substrate, 125 is a positive type photoresist film, d is a step, W ₀ , W ₁ and W ₂ are pattern widths, and θ is the angle of the slope.

The step d on the substrate 124 of the sample for which the data of FIG. 50 (a) was obtained is 7 [μm]. The positive type photoresist film 125 is formed on this substrate 124, and the width is 20 [μm]. A photoresist pattern was formed using the pattern on the glass mask of, and the widths W ₁ and W ₂ were measured.

As in the past, in the case of a steep step where the angle θ is around 45 °, as the photoresist film thickness under the step increases,
The pattern width deviates greatly.

If the angle θ is made small by implementing the present invention, that is, the slope is formed gently, it is possible to reduce the pattern width variation to such an extent that there is no practical problem.
It can be seen that a pattern having substantially the same quality as that of (= 0 °) can be formed. Therefore, it is clear that in the formation of the wiring pattern using the lift-off method and the vapor deposition method, a process having an extremely high yield can be realized. The thickness of the photoresist film used in this example is about 2 [μ in the flat portion.
m], the exposure and development conditions were selected so that the optimum pattern could be formed in the flat portion.

Advantageous Effects of Invention In the method for manufacturing a semiconductor device according to the present invention, a step of forming a mask pattern having an inclined surface at an end on a semiconductor substrate, and anisotropic etching in the vertical direction on the entire surface of the substrate A step of transferring the mask pattern to form a low substrate surface which is continuous on the semiconductor substrate through a step portion composed of a surface and an inclined surface; and a multi-layer semiconductor layer structure is grown on the entire surface of the substrate including the low substrate surface. A step of forming a mask pattern having an inclined surface on the lower substrate surface, and an anisotropic etching in the vertical direction on the entire surface of the substrate to form the multilayer semiconductor layer structure in the lower substrate surface. A step of transferring the mask pattern and removing the other multilayer semiconductor layer structure on the surface of the substrate, and an optical semiconductor device having a multilayer semiconductor layer structure formed in the lower substrate surface. A step of forming a semiconductor element on the surface of the substrate, the optical semiconductor element and the semiconductor element on the inclined surface formed on the substrate and on the inclined surface formed in the multilayer semiconductor layer structure. And a step of forming a wiring layer for connecting the wirings are included.

According to this configuration, the semiconductor element formed using the single crystal layer and the semiconductor element formed using the substrate are
Since the surfaces can be made to be substantially on the same plane, it is possible to form the wiring connecting the respective semiconductor elements on a flat surface or on a gently sloping surface. No wire breakage will occur. Further, since the surfaces of the respective semiconductor elements are substantially on the same plane, the photo resist process, the photo process and the like are facilitated, which is effective for forming a fine pattern. Furthermore, since the thickness of the semiconductor layer formed on the low substrate surface is maintained substantially uniform over the entire surface of the wafer, the manufacturing yield of the semiconductor device is good.

[Brief description of drawings]

FIG. 1 is a side view of a main part of a semiconductor device manufactured by the prior art, FIG. 2 is an equalization circuit diagram of the semiconductor device shown in FIG. 1, and FIG. 3 is another semiconductor manufactured by the prior art. FIG. 4 to FIG. 8 are sectional side views of essential parts of the device, and FIG. 4 to FIG. 8 are sectional side views of essential parts of the semiconductor device in process steps for explaining the prior art. A plan view of a main part and a line a for explaining the inconvenience of the recess formed in the step described with reference to FIG.
FIGS. 12 to 14 are sectional views taken along line -a 'and line bb', and FIGS. 12 to 14 are semiconductor devices in process steps for explaining an example of a conventional technique for filling a semiconductor layer in a recess. FIG. 15 to FIG. 17 are sectional side views of essential parts of a semiconductor device in process steps for explaining another example of the prior art for filling a semiconductor layer in a recess. FIGS. 20 to 23, and 24 are side views of a main part of a semiconductor device at a process step for explaining an embodiment of the present invention, FIGS. 21 and 22 are reference examples. A side view of a main part cut of a semiconductor device in a process key point for explaining, FIG. 25 and FIG. 26 are a plan view and a main part cutaway showing a recess formed in a substrate by applying the present invention. Side views, FIGS. 27 and 28 are plan views and a cutaway side view of an essential part of an embodiment in which the recess is circular, and FIGS. 29 and 30 are flaps having a gently inclined surface at the edge. A side view of the essential parts of the semiconductor device, etc., at the steps required to explain the case of forming a photoresist film, and FIG. 31 describes a technique different from the exposure method described with reference to FIG. 29. FIG. 32 is a sectional side view of a main part of a semiconductor device in a process key point for carrying out a process, and FIG. 32 is a semiconductor device in a process key point for explaining a technique different from the exposure method described with reference to FIGS. 29 and 31. essential portion cutaway side view of FIG. 33 diagram representing the relationship between the in x values and the etch rate in the Al _X Ga _1-X as, FIG. 34 through FIG. 36 Al _X G
a _1-X As side view of the main part of the semiconductor device cut along the process steps for explaining the embodiment utilizing the etching rate difference, and FIG. 37 shows the semiconductor device manufactured according to the reference example. Fig. 38 is an equivalent circuit diagram and Fig. 39 is a laser
A side view of a main part of a semiconductor device having a structure in which a diode portion and a field effect transistor portion are continuous through a gentle slope, FIG. 40 is a field effect type utilizing an active region formed in a substrate. FIG. 41 and FIG. 42 are side views showing a cutaway view of a main part of a semiconductor device that constitutes a transistor portion.
n is a side view of a main part of a semiconductor device at a process step for explaining a case of manufacturing a semiconductor device in which a diode and a field effect transistor are combined, FIG. 43 is an equivalent circuit diagram,
44 to 48 are side sectional views of a main part of a semiconductor device in a process key point for explaining an embodiment in which a gentle slope is formed by using chemical etching, FIGS. 49 (a) and (a). b) is a diagram showing the uniformity of the thickness of the semiconductor layer in the recess and a side view of the main part of the model semiconductor device.
50 (a), (b) and (c) show how the dimensional accuracy and manufacturing yield in the photoresist process applied to manufacture the semiconductor device shown in FIG. 39 are improved. FIG. 3 is a diagram showing a relationship between the angle of the slope and the deviation of the pattern width for explaining the above, a side view of a main part of the sample cut away, and a plan view of the main part of the sample. In the figure, 31 is a semi-insulating GaAs substrate, 31 'is a recess, 31A.
Is the surface of the substrate 31, 31B is the stepped portion, 31C is the low substrate surface, and 32 is
Is a photoresist film, 32A is an opening, 32B is an inclined surface, 33 is a semiconductor layer, and 34 is a photoresist film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Miura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hideki Machida 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Shigenobu Yamagoshi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Teruo Sakurai 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa FUJITSU LIMITED (56) References Applied Physics Letters 44 [3], 1 February 1984, p. 325-P. 327 Journal of Light ve Technology LT-1 [1] March 1983 P.M. 261 ~ P. 267

Claims (1)

[Claims] 1. A step of forming a mask pattern having an inclined surface at an end on a semiconductor substrate, and anisotropic etching in the vertical direction on the entire surface of the substrate to transfer the mask pattern to the substrate to form a semiconductor. A step of forming a low substrate surface continuous on the substrate through a step portion formed by the surface and an inclined surface; a step of growing a multilayer semiconductor layer structure on the entire surface of the substrate including the low substrate surface; Forming a mask pattern having an end surface having an inclined surface; and performing a vertical anisotropic etching on the entire surface of the substrate to form the mask pattern on the multilayer semiconductor layer structure in the lower substrate surface.
Transferring the pattern and removing the other multilayer semiconductor layer structure on the substrate surface other than that, forming an optical semiconductor element on the multilayer semiconductor layer structure formed in the lower substrate surface, and on the substrate surface Forming a semiconductor element, and forming a wiring layer connecting the optical semiconductor element and the semiconductor element on the inclined surface formed on the substrate and on the inclined surface formed in the multilayer semiconductor layer structure. A method of manufacturing a semiconductor device, comprising: