WO2023227212A1

WO2023227212A1 - Method for processing an optoelectronic device and optoelectronic device

Info

Publication number: WO2023227212A1
Application number: PCT/EP2022/064235
Authority: WO
Inventors: Lutz Hoeppel
Original assignee: Ams-Osram International Gmbh
Priority date: 2022-05-25
Filing date: 2022-05-25
Publication date: 2023-11-30
Also published as: TW202405898A

Abstract

The invention concerns a method for processing an optoelectronic device, wherein one or more structured reflective layer portions with a sacrificial top layer are deposited on a surface of a semiconductor layer stack by means of sputtering or vaporizing and subsequent lift- off technique. The sacrificial top layer is removed, and a cap layer of a different material deposited thereupon. The resulting structure may then be dry etched to form a mesa shaped optoelectronic device with its side portions being covered by a passivation layer. Portions of a protective layer and the cap layer are removed on the one or more structured reflective layer portions to gain an electrical access to the reflective layer.

Description

METHOD FOR PROCESSING AN OPTOELECTRONIC DEVICE AND OPTOELECTRONIC DEVICE

BACKGROUND

When processing optoelectronic devices , a reflective layer is often deposited on the surface , which then needs to be accessed by dry etching through a passivation layer on top of the reflective material . For this purpose , the reflective material , most of the time conductive itself , is covered by a conductive cap layer that is compatible with the dryetch process . The term "compatible" in this regard means , the respective cap material should not be consumed too much during the dryetch process and still exhibit true etch capability although at low rate to avoid that the material is j ust redeposited into the etch chamber .

In some instances , the reflective layer as well as the cap layer is deposited by sputtering and patterned by means of lift-off technique . The sputtering process usually leads to dot like grains around the macroscopic rim of the mirror mainly consisting of the cap material . Such unwanted features can practically no longer be removed after deposition without damaging the entire cap .

It is an obj ective of the present application to overcome the above issue and enable a simple processing approach for optoelectronic devices in particular so called pLEDs .

SUMMARY OF THE INVENTION

This and other obj ectives are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

The inventor has realized that some of the above issues are caused by the sputtering process itself in combination with the lift-off technique . Those techniques are preferred over conventional depositing but require , due to the spatially varying layout across the wafer , a tape lift-off process prior to the actual resist stripping process to remove excess sputtered material either from the resist or together with some parts of the resist . This removal process is facilitated by a sticky tape . With a rather thin resist layer of the order of 1pm and significantly larger feature sizes the adhesive part of the tape can easily touch the top surface of the sputtered material within an opening of the resist thus leading to sticky residues . Resist stripping media can' t remove them on a reliable basis within a limited time governed by the finite solubility of the parts of sputtered material in such solvents .

To overcome this issue , the inventor proposes to also deposit a sacrificial layer on top of the reflective material ( i . e . a metal ) prior to the application of the lift-off process . The sacrificial layer covers the material of the reflective layer sputtered onto the surface of the semiconductor layer stack and prevent residual of the adhesive to remain on the reflective material after the lift off process . After removing the excess metal and stripping the resist , this sacrificial is removed in a wet chemical etch step selectively to the reflective layer material and the semiconductor stack . In other words , a wet etching process is used that does not etch the reflective material or the semiconductor stack .

By utilizing the sacrificial layer one can facilitate the removal of contaminants and residual of the adhesive . ZnO is a suitable material that can be used as a sacrificial layer . After removal , the actual cap, that remains part of the product , is deposited full wafer .

In some instances , a method is proposed for processing an optoelectronic device . The method comprises the step of providing an epitaxially grown semiconductor layer stack having an active layer . The epitaxially grown semiconductor layer stack can be grown on a growth substrate including for example sapphire or any other suitable material . The epitaxially grown semiconductor layer may include one or more buffer layers to match the lattice constant of the growth substrate to the desired semiconductor material . The buffer layers are also used to bury any deficits and obtain a smooth and even surface .

The epitaxially grown semiconductor layer comprises differently doped portions . For example , one or more n-doped regions are grown on the growth substrate followed by the active layer and one or more p-doped layers . The doped layers may inherit different functionalities including but not limited to current transport or current distribution layers . The active layer may comprise one or more quantum wells . In some instances , Quantum well intermixing may be conducted during growth of the layer stack to achieve an increase in the bandgap of the active layer in portions of the active layer that is close to mesa edges of the subsequently formed optoelectronic device .

In accordance with the proposed principle , one or more structured reflective layer portions with a sacrificial top layer are deposited on the surface of the semiconductor layer stack by means of sputtering or evaporation and subsequent lift-off techniques . After removing the excess material of the reflective layer portions and stripping the resist , the sacrificial top layer is removed, in particular by wet etching the sacrificial top layer . Then, a cap layer is deposited on the one or more structured reflective layer portions and the remaining surface of the semiconductor layer stack .

This can be done by sputtering , evaporation or any other suitable technique . The cap layer does not show any taper toward the reflective material rim due to its full wafer deposition . Moreover it can act as an etch stop layer in a subsequent dry-etch process .

Subsequently, a protective layer on top of the cap layer material is optionally deposited . As this protective layer is deposited onto the cap layer, also in areas of the cap layer over the surface of the semiconductor layer stack, ( i . e . between the reflective material portions ) any creeping of material of the protective layer into holes in the semiconductor layer stack is prevented . A hard layer is deposited on top of the protective layer or the cap layer , respectively in a subsequent step . Then, one or more dry etch processes are performed to form a mesa structure around the one or more structured reflective layer portions , wherein the mesa structure exposes the active layer . The exposed portions of the active layer can be annealed in some instances and a passivation layer is deposited thereupon . Finally, portions of the cap layer and the optional protective layer are removed on one or more structured reflective layer portions .

In some instances , the step of depositing one or more structured reflective layer portions comprises sputtering a reflective material onto a surface of the semiconductor layer stack so as to form one or more structured reflective layer portion on the surface . Likewise , the sacrificial layer is sputtered or otherwise deposited on the structured reflective layer . Then, a lift-off technique is used to remove the material of the reflective layer from areas outside the one or more structured reflective layer portions . In some instances , a photo resist layer is deposited onto the surface of the semiconductor layer stack and subsequently structured prior to sputtering the reflective material

The reflective layer may comprise silver , particularly having a thickness between 80 nm and 250 nm and particularly between 100 nm and 200 nm and particularly between 130 nm and 180 nm. Silver is a conductive and highly reflective material . Depending on the wavelength of the optoelectronic device , other reflective metals like Gold can be used . The sacrificial top layer may comprise at last one of ITO and TiW . The sacrificial top layer has a thickness between 20 nm and 60 nm and particularly between 40 nm and 50 nm.

In some instances due to the sputtering process , the reflective layer may comprise a curved surface with a thickness closer to edge portions being smaller than in the centre . In this regard, it is possible that after deposition of the sacrificial layer, said layer also inherits the curved surface . However , depending on the deposition parameter a flatter surface shape is achievable . Likewise , the reflective layer can be flattened either by mechanical or chemical means after the sputtering process or by careful selecting the parameters of the deposition process . Although a sputtering process is referenced herein, the s killed person may recognize that other deposition processes can be used to form the one or more structured reflective layer portions and the sacrificial layer on top . The cap layer , that is deposited on top of the one or more structured reflective layer portions after removal of the sacrificial layer comprises a KOH stable material and in particular ITO . It comprises a thickness between 20 nm and 80 nm and in particular between 40 nm and 60 nm .

In some more aspects , the optional protective layer may comprise a Hafniumoxide , HfOx . In this regard it should be noted that HfOx comprises a certain edge resilience towards KOH and other etchants used in subsequent steps , whereas such resilience is dependent on the process parameter during its deposition . Its thickness may also vary and can be in range between 15 nm and 50 nm and in particular between 25 nm and 35 nm . The hard mask layer may include SiNx . In some instances , the hard mas k layer can include a layer structure with several layer of different material to ensure a step wise mesa etching process . This may be useful if annealing or other steps are performed during different dry etchant steps .

Some aspects concern the step of conducting one or more dry etches . For example , a photoresist layer is deposited such that portions of the layer cover and extend over the one or more structured reflective layer portions . The additional photoresist does partially protect the hard mask layer during a first etchant step such that an edge in the hard mas k is formed . The dry-etching process may expose portions of the hard mas k layer up to a first depth . The photoresist layer is then removed and the dry-etching process can be continued . This will result in a mesa structure exposing the active layer around the reflective layer and the cap layer . During the first and/or second etching step one or more annealing steps are performed in some instances . For example , the side surfaces of the mesa structure are annealed using a KOH bath . To protect the edges of the active layer in the mesa structure , a thin passivation layer e . g . A12O3 is deposited using an ALD ( atomic layer deposition) process . This passivation layer may comprise a thickness of about 30 nm to 100 nm and in particular about 40 nm to 75 nm. The dry etch process forming the mesa structure may also expose side portions of the cap layer . Those exposed side portions are deposited on the semiconductor layer stack . In other words , the mesa edges are horizontally spaced apart from the rim of the reflective layer .

Finally, the step of removing portions of the protective layer and the cap layer leaves the surface of the reflective layer unexposed . Hence , a small material portion of the cap layer will remain over the reflective material . This will prevent an uneven removal of reflective layer material , which is otherwise caused by the etchant . The etchant used for removing portions of the protective layer and the cap layer can be a Cl based reactive ion etch process .

Some further aspects concern an optoelectronic device . The optoelectronic device comprises a mesa structured semiconductor layer stack including an active layer and a top surface . A reflective layer is arranged in a central region of the top surface , such that a bottom surface opposite the top surface may suitably act as a light emission surface in operation of the optoelectronic device .

Further , a conductive cap layer covers the reflective layer in the central region and also extends onto a second region of the top surface surrounding the central region . The second region is adj acent to the mesa structure . In other words , side edges of the second region facing away the central region form a portion of the mesa of the semiconductor layer stack . A passivation layer covers the sides of the mesa structured semiconductor layer stack and extends over the cap layer . Finally, a cavity is formed in the passivation layer over the central portion, said cavity reaching partially into the cap layer . Hence , the cavity leaves the actual material of the reflective layer uncovered .

In some instances , the optoelectronic device further comprises a protective layer deposited on the cap layer, wherein the protective layer comprises HfOx having a thickness between 15 nm and 50 nm and in particular between 25 nm and 35 nm. In some other aspects , the passivation layer comprises A12O3 . The passivation layer may comprise a thickness of about 30 nm to 100 nm and in particular about 40 nm to 75 nm. The cap layer comprises in some instances a KOH stable material in particular ITO having a thickness between 20 nm and 80 nm and in particular between 40 nm and 60 nm.

SHORT DESCRIPTION OF THE DRAWINGS

Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

Figures 1 to 11 illustrate various method steps of processing an optoelectronic device in accordance with some aspects of the proposed principle ;

Figures 12 illustrates another embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

Figure 13 a top view onto the contact area of an optoelectronic device in accordance with some aspects of the proposed principle .

DETAILED DESCRIPTION

The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea . In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

Figure 12 illustrates an optoelectronic device manufactured in accordance with several aspects of the proposed principle .

Although only a single optoelectronic device manufactured by the proposed method is currently illustrated in Figure 12 , the s killed artisan may recognize that a plurality of optoelectronic devices can be processed and manufactured in accordance with the present invention on a single wafer .

Consequently, the embodiment illustrated herein comprises a growth substrate 10 , for example , in form of a sapphire substrate . One or more plurality of differently doped regions are epitaxially grown on the growth substrate 10 , illustrated herein as a single layer 11 having an active region I la embedded therein .

The differently doped regions grown may comprise buffer layers directly grown on the sapphire substrate 10 to match different lattice constants as well as provide a smooth and even growth surface . Some further layers may act as an outcoupling structure and can be roughened or otherwise processed after the optoelectronic device is rebonded . In the present example , an n-doped region is deposited on the buffer layers . The doping concentration follows a certain distribution to ensure small resistance and good charge carrier inj ection into the active layer Ila .

Active layer I la is illustrated herein as a single layer for simplicity purposes . However, active layer I la often comprises one or more quantum well layers separated by quantum barrier layers having different material composition to implement different bandgap barriers . On top of active region Ila, a p-doped material is deposited to provide the current inj ection into the active region .

In accordance with the present invention, the optoelectronic device illustrated herein is shaped with a mesa structure surrounding the optoelectronic device on each side . The sidewalls forming the cavity 16a are slightly inclined and are covered by a passivation layer 18a extending also along over portions of the n-doped material of layer 11 in the mesa cavity .

A reflective material 12 , for example a silver layer is provided in a central region on top of the p-doped area of layer 11 above active layer Ila . The silver mirror is completely surrounded by a cap layer made of ITO or any other conductive material , hence , reflective material is spaced apart from the mesa edge structure . This will ensure that current inj ection preferable occurs in the area covered by reflective material thus reducing charge carrier density close to the edge regions thereby improving efficiency . Together with further measures like Quantum well intermixing as mentioned below, the quantum efficiency may be increased . The cap layer 14 covers the top surface of material 12 and extends along the top surface of the p-doped area adj acent to reflective material and mirror 12 towards the edges of the mesa structure . The top layer 14 is covered by a protective layer 15 made of hafnium oxide HfOx, which also extends over the cap layer till the edges of the mesa structure . The protective layer 15 is a residual from the previous processing steps as it will be explained in further details below .

A cavity 19 is included exposing a surface portion 14b of the cap layer 14 in a central region of cap layer 14 . Cavity 19 reaches through the protective layer 15 , as well as the top passivation layer 18 and removes a portion of material of cap layer 14 , but leaving a material bridge in area 14b behind . Thus , the underlying silver material of reflective layer 14 is protected against corrosion . Due to the first material bridge made of ITO , a corrosion free of passivation opening on top of the reflective server mirror 12 is achieved . The same time , the cap layer 14 as well as the reflective layer 12 is conductive , thus allowing to be able to fill a metal for contacting the p-doped region into the cavity 19 .

The material of top passivation layer 18 is the same material as the passivation layer on the side edges 18a and may comprise , for example , AL2O3 . This material is used during the annealing process of the sidewall edges of the optoelectronic device to reduce crystal defects caused by the dry etching process of the mesa structure . In addition, not illustrated herein, a quantum well intermixing was performed on the side and edge portions of the optoelectronic device ; that is the p-region adj acent to the etched mesa structure . The induced material and the annealing process of the quantum well intermixing change the band gap in the active layer .

Figure 13 illustrates a top view onto the cavity 19 in accordance with the present invention . The cavity 19 is shaped in a rectangular form with a slightly around edges . The bottom of the cavity includes the cap layer material and provides a smooth and corrosion free surface . In particular, the underlying silver is not corroded by the various processing steps and provides highly conductive and reflective area towards of the P doped region of the semiconductor material .

Figure 1 to 12 illustrate several method steps of processing an optoelectronic device in accordance with the proposed principle .

Figure 1 illustrates a first step providing a growth substrate 10 , on which one or more differently doped layers are epitaxially grown . For example , buffer layers are grown on the growth substrate 10 in the first place to provide a smooth growth surface for subsequently n- doped or p-doped layers . In the example illustrated herein an n-doped layer is grown on the growth substrate and the buffer layers , respectively, followed by one or more quantum well layers I la . The one or more quantum well layers I la act as an active layer in a subsequent operation of the optoelectronic device , wherein charge carriers are recombining under the emission of photons . A p-doped region is deposited on top of the multi-quantum well structure and the active layer I la . The differently doped semiconductor materials are selected in accordance with the desired emission wavelength of the optoelectronic device . For example , GaN based materials and derivates thereof may be used for the generation of the blue and green light , respectively . Other materials like GaAs or GaAlP based materials including Indium as well as can be used to implement optoelectronic devices for the emission of red light .

In accordance with the proposed principle a structured photoresist layer 20 is provided on the top surface of the p-doped layer in preparation for a subsequent lift-off technique . The photoresist comprises a slight under-etch, which can be conducted by two slightly different photoresist materials or by a two-step depositing and exposure process . In the latter case , a first layer of photoresist is deposited on the surface and exposed using a first photomas k . Then, a second layer is deposited and exposed with a second photomas k . The second photomask used for the expose has a slightly different cross section . Other options for processing the under-etch can be used as well .

Referring now to Figure 2 . A sputtering process is performed depositing a reflective material , in this case , silver , as layer 12 on the surface of the p- doped region as well as material layer 12a on the photoresist layer 20 . The sputtering process does not necessarily result in a smooth and flat surface , but may generate a slightly curved shape for the silver material in the cavity provided by the structured photoresist on the surface of the p-doped region . In particular due to the under-etch, the silver material comprises a relatively sharp edge . The shape and form of the sputtered silver is adj ustable by proper selection of the process parameters . For example , the curvature can be reduced, by for instance choosing a thinner resist thickness . It has been found that the sputtering process may be more suitable compared to other deposition methods , although evaporation is a possible alternative deposition method . The lift-off process is then conducted in a subsequent step by providing an adhesive tape onto the top surface and removing the excess silver material in areas 12a including photoresist 20 .

However , such lift-off the technique may often result in an undesired leftover of the adhesive tape thereby contaminating the reflective layer on the top surface of the p-doped material . To prevent such residues , the present application proposes depositing a sacrificial layer 13 additionally on top of layer 12 as well as on layer 12a . This sacrificial layer can be sputtered onto the surface , but also be applied by various different means . The sacrificial layer comprises TiW or ZnO . Such material allows for a selective etch-off process without damaging the underlying reflective layer of the top surface of the semiconductor layer stack .

As illustrated in Figure 3 the lift-off process is performed using an adhesive tape or similar element removing the sacrificial layer portions 13a, the reflective material 12a as well as the photoresist 20 from the surface of the layer stack, but leaving the reflective material 12 and the sacrificial layer 30 behind . The sides 130 of the reflective material 11 follow the shape of the previously patterned photoresist layer . The pattern of the photoresist and the sputtering or deposition process allows for shaping the material of reflective layer 12 in accordance with the needs and requirements .

The next step in Figure 4 illustrates the result of a wet etching process removing the sacrificial layer 13 from the top surface of the reflective layer without damaging the surface of the reflective layer or the surface of the semiconductor layer stack . The resulting structure is then processed in various further steps to implement the optoelectronic device . The wet chemical etching of the sacrificial layer 13 allows for complete removal of dot-like residues that appear all around the silver rim during the sputtering process of the silver/sacrif icial layer stack .

The subsequent final cap layer doesn ' t show any taper toward the silver rim due to its full wafer deposition and can protect the silver and reflective layer 12 . This process is shown in Figure 5 , in which cap layer 14 made of ITO is deposited over the reflective material 12 and on the surrounding surface of the p-doped structure . The cap layer is a conductive material and will protect the underlying reflective material layer 12 .

The next subsequent step illustrated in Figure 6 is optional and can be left out if cap layer 14 is able to protect the silver layer 12 from the subsequent process steps . If not a thin layer of an 03 proof material like hafnium oxide HfOx is deposited on top of cap layer 14 and the surrounding area . The protective layer 15 is used during the subsequent hard mas k etch and the cleaning with KOH to protect the underlying cap layer 14 and silver layer 12 from being etched . However , depending on the subsequent processing steps , the protective layer 15 can be omitted .

A hard mas k 16 made of SiNx is now deposited on top of protective layer 15 . The hard mas k is used for the dry etch processes to structure the mesa of the optoelectronic device . For this purpose , a photoresist layer 17 is deposited on the top surface of hard mas k layer 16 and subsequently patterned . Surface regions of the hard mask layer 16 surrounding the reflective layer 12 as illustrated are exposed .

The dry etch process is performed in several steps , and various alternatives can therefore be used . In the present exemplary embodiment shown in Figure 8 , a first dry etching process using reactive ion etching and the like is performed removing partially the exposed portion of the hard mask layer 17 , resulting in the step like structure . In the present example , the process is interrupted prior to removing the hard mask completely . However, it can be useful in some instances to remove portions of layer 15a and 14a , respectively . In some instances , the first dry etching step is conducted until the active layer I la is exposed . This will enable annealing the active layer and protecting it by a passivation layer prior to resuming the dry etch process . Cavities 16a are formed surrounding the reflective layer 12 and of the cap layer as well as the protective layer on top in a subsequent second etching step shown in Figure 9 . The photoresist layer 17 is then removed and a subsequent dry etching step is conducted removing portions of p- doped area, the active region I la as well as of the n-doped layer 11 . The dry etching process is stopped when the mesa structure is completely formed comprising inclined sidewalls 16b surrounding the optoelectronic device . The sidewalls 16b may comprise a plurality of crystal and other defects , which requires a subsequent KOH base cleaning and annealing step .

The results of the dry etching process illustrated in Figure 9 is achieved by the presented exemplary two-step process . However, other alternative processes are conceivable , in which for example the exposed active layer is annealed and healed and subsequently covered by a small passivation layer to protect the active layer I la during the dry etching steps .

In any case , after the cleaning process is completed, a thin passivation layer 18 made of A12O3 is deposited on the sidewalls of the optoelectronic semiconductor device to protect the exposed surface of active layer 18a . The passivation layer in this example also extends over the overall surface including the cap layer 14 and protective layer 15 as well as into cavity 16a

Finally, a portion on top of the passivation layer 18 and the reflective material layer 12 is removed, exposing cavity 19 and portion 14b of cap layer 14 .

LIST OF REFERENCES

10 growth substrate

11 semiconductor layer stack Ila active layer

12 , 12a reflective layer

13 , 13a sacrificial top layer

14 , 14a cap layer

15 , 15a protective layer 16 hard mask

16a mesa structure , cavity

16b side edge portions

17 photoresist

18 , 18a passivation layer 19 cavity

20 photoresist layer

130 edges

Claims

CLAIMS Method for processing an optoelectronic device comprising the steps :

Providing an epitaxially grown semiconductor layer stack having an active layer ;

Depositing one or more structured reflective layer portions with a sacrificial top layer on the surface of the semiconductor layer stack by means of sputtering or evaporation and subsequent liftoff technique ;

Removing the sacrificial top layer, in particular by wet etching the sacrificial top layer ;

Depositing a cap layer on the one or more structured reflective layer portions and the remaining surface of the semiconductor layer stack;

Depositing a protective layer on top of the cap layer;

Depositing a hard mas k layer on top of the protective layer;

Conducting one or more dry etches to form a mesa structure around the one or more structured reflective layer portions , wherein the mesa structure exposes the active layer;

Covering the active layer by a passivation layer ;

Removing portions of the protective layer and the cap layer on the one or more structured reflective layer portions . Method according to claim 1 , wherein the step of depositing one or more structured reflective layer portions comprises :

Sputtering a reflective material onto a surface of the semiconductor layer stack as to form one or more structured reflective layer portion on the surface ;

Depositing a sacrificial layer on the structured reflective layer . Method according to claim 2 , wherein the step of depositing one or more structured reflective layer portions comprises :

Depositing a structured resist layer onto the surface of the semiconductor layer stack . Method according to any of the preceding claims , wherein the reflective layer portions comprise silver, particularly having a thickness between 80 nm and 250 nm and particularly between 100 nm and 200 nm and particularly between 130 nm and 180 nm. Method according to any of the preceding claims , wherein the sacrificial top layer comprises at last one of ITO and TiW having a thickness between 20 nm and 60 nm and particularly between 40 nm and 50 nm . Method according to any of the preceding claims , wherein the sacrificial top layer comprises a curved surface with a thickness close to edge portions being smaller than in the centre . Method according to any of the preceding claims , wherein the cap layer comprises a KOH stable material in particular ITO having a thickness between 20 nm and 80 nm and in particular between 40 nm and 60 nm . Method according to any of the preceding claims , wherein the protective layer comprises HfOx having a thickness between 15 nm and 50 nm and in particular between 25 nm and 35 nm. Method according to any of the preceding claims , wherein the hard mas k layer comprises SiNx . Method according to any of the preceding claims wherein the step of conducting one or more dry etches comprises :

Depositing a photoresist layer such that portions of the layer cover and extend over the one or more structured reflective layer portions ;

Dry-etching exposed portions of the hard mask layer to a first depth;

Removing the photoresist layer;

Dry etching the hard mask layer as to expose the active layer;

Annealing the exposed surface of the semiconductor layer stack with KOH . Method according to any of the preceding claims wherein the step of covering the active layer comprises :

Depositing a thin layer, particularly by atomic layer deposition of A12O3 having a thickness of about 30 nm to 100 nm and in particular about 40 nm to 75 nm . Method according to any of the preceding claims wherein during conducting one or more dry etches , side portions of the cap layer are exposed, said side portions deposited on the semiconductor layer stack . Method according to any of the preceding claims wherein the step of removing portions of the protective layer and the cap layer leaves the surface of the reflective layer unexposed . Optoelectronic device , comprising : a mesa structured semiconductor layer stack including an active layer and having a top surface . a reflective layer in a central region of the top surface . a conductive cap layer covering the reflective layer in the central region and extending onto a second region of the top surface surrounding the central region . a passivation layer covering side edges of the mesa structured semiconductor layer stack and extending over the cap layer . a cavity in the passivation layer over the central portion, said cavity reaching partially into the cap layer . Optoelectronic device according to claim 14 , further comprising a protective layer over the cap layer , wherein the protective layer comprises HfOx having a thickness between 15 nm and 50 nm and in particular between 25 nm and 35 nm . Optoelectronic device according to claim 14 or 15 wherein the passivation layer comprises A12O3 having a thickness of about 30 nm to 100 nm and in particular about 40 nm to 75 nm . Optoelectronic device according to any of claims 14 to 16 , wherein the cap layer comprises a KOH stable material in particular ITO having a thickness between 20 nm and 80 nm and in particular between 40 nm and 60 nm.