CN113206144B - Preparation method of thin film transistor, thin film transistor and display panel - Google Patents
Preparation method of thin film transistor, thin film transistor and display panel Download PDFInfo
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- CN113206144B CN113206144B CN202110450638.5A CN202110450638A CN113206144B CN 113206144 B CN113206144 B CN 113206144B CN 202110450638 A CN202110450638 A CN 202110450638A CN 113206144 B CN113206144 B CN 113206144B
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- KMUONIBRACKNSN-UHFFFAOYSA-N potassium dichromate Chemical compound [K+].[K+].[O-][Cr](=O)(=O)O[Cr]([O-])(=O)=O KMUONIBRACKNSN-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The application discloses a preparation method of a thin film transistor, the thin film transistor and a display panel, wherein the preparation method of the thin film transistor comprises the following steps: forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer and a second metal layer on the substrate in sequence; etching the second metal layer to form a first channel in the second metal layer; forming a passivation layer over the second metal layer; etching the ohmic contact layer below the first channel by taking the passivation layer as a mask so as to form a second channel below the first channel; a second insulating layer is formed over the second metal layer. The thin film transistor prepared can be prevented from having semiconductor steps, so that the problem of electric leakage caused by the semiconductor steps is avoided.
Description
Technical Field
The application relates to the technical field of liquid crystal display, in particular to a preparation method of a thin film transistor, the thin film transistor and a display panel.
Background
When a thin film transistor is prepared, a 4Mask process is usually adopted; when the metal layer and the semiconductor layer are etched by adopting a 4Mask process, a semiconductor step exists between the channel of the metal layer and the channel of the semiconductor layer, and the existence of the semiconductor step can cause electric leakage of the thin film transistor.
Disclosure of Invention
The present disclosure provides a method for manufacturing a thin film transistor, and a display panel, and aims to solve the technical problem of leakage caused by a semiconductor step in the thin film transistor.
In order to achieve the above object, the present application provides a method for manufacturing a thin film transistor, the method comprising:
forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer and a second metal layer on the substrate in sequence;
etching the second metal layer to form a first channel in the second metal layer;
forming a passivation layer over the second metal layer;
etching the ohmic contact layer below the first channel by taking the passivation layer as a mask so as to form a second channel below the first channel;
a second insulating layer is formed over the second metal layer.
Optionally, between the step of sequentially forming the first metal layer, the first insulating layer, the active layer, the ohmic contact layer, and the second metal layer over the substrate, and the step of forming the passivation layer over the second metal layer, the method further includes:
forming a photoresist layer above the second metal layer, and patterning the photoresist layer;
taking the photoresist layer after the patterning treatment as a mask, and etching the second metal layer to form a first channel on the second metal layer;
and stripping the photoresist layer.
Optionally, between the step of forming a photoresist layer over the second metal layer and performing patterning on the photoresist layer and the step of stripping the photoresist layer, the method further includes:
patterning the second metal layer by taking the photoresist layer after patterning as a mask;
patterning the ohmic contact layer by taking the patterned photoresist layer as a mask;
patterning the active layer by taking the photoresist layer after patterning as a mask;
and etching the second metal layer after patterning by taking the photoresist layer after patterning as a mask to form the first channel.
Optionally, the photoresist layer includes a first photoresist region and a second photoresist region, a thickness of the first photoresist region is smaller than a thickness of the second photoresist region, the first photoresist region is located above the first trench, the second photoresist region is not overlapped with the first photoresist region, the patterned photoresist layer is used as a mask, and after the step of patterning the active layer, the method further includes:
and etching the photoresist layer to remove the first photoresist region and reserve the second photoresist region.
Optionally, the sequentially forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer, and a second metal layer over the substrate includes:
forming a first metal layer above the substrate, and performing patterning processing on the first metal layer;
forming the first insulating layer over the patterned first metal layer;
forming the active layer over the first insulating layer;
forming the ohmic contact layer over the active layer;
forming the second metal layer over the ohmic contact layer.
Optionally, after the step of forming the second insulating layer over the second metal layer, the method further includes:
patterning the second insulating layer;
forming a pixel electrode layer over the patterned second insulating layer;
and patterning the pixel electrode layer.
Optionally, after the step of etching the ohmic contact layer under the first trench by using the passivation layer as a mask, the method further includes:
and etching the exposed area of the active layer, wherein the thickness of the etched exposed area of the active layer is 30 nm-120 nm, and the exposed area is positioned below the second channel.
Optionally, the thickness of the passivation layer is 50nm to 100nm.
In addition, in order to achieve the above object, the present application also provides a thin film transistor, which is prepared according to any one of the above methods for preparing a thin film transistor.
In addition, in order to achieve the above object, the present application also provides a display panel including the thin film transistor prepared by the method for preparing a thin film transistor according to any one of the above aspects.
According to the preparation method of the thin film transistor, the thin film transistor and the display panel, the first metal layer, the first insulating layer, the active layer, the ohmic contact layer and the second metal layer are sequentially formed on the substrate, the second metal layer is etched to form the first channel on the second metal layer, the passivation layer is formed above the second metal layer and can play a role in protection, the ohmic contact layer below the first channel is etched by taking the passivation layer as a mask, the second channel is formed below the first channel under the condition that the second metal layer is not etched, when the second channel is etched, the passivation layer protects the second metal layer, the second metal layer cannot be laterally deviated during etching, the position and the size of the second channel correspond to the position and the size of the first channel, the second metal layer and the ohmic contact layer are not relatively deviated between the cross sections of the respective channels, no semiconductor step exists, and the second insulating layer is further formed above the second metal layer, so that the prepared thin film transistor does not have the semiconductor step, and the technical problem of electric leakage caused by the semiconductor step in the thin film transistor is solved.
Drawings
FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a thin film transistor according to the present application;
FIG. 2 is a schematic flow chart of a second embodiment of a method for fabricating a thin film transistor according to the present application;
fig. 3A to 3L are schematic views of a method for manufacturing a thin film transistor according to a third embodiment of the present invention;
FIG. 4 is a schematic diagram of an embodiment of a thin film transistor of the present application;
fig. 5A and 5B are schematic diagrams illustrating the existence of semiconductor steps in the fabrication of a thin film transistor according to an exemplary technique.
The reference numbers illustrate:
the implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
When the thin film transistor is manufactured based on the 4Mask process, a channel of the metal layer and a channel of the semiconductor layer below the metal layer are etched from top to bottom by using the same photoresist layer as a protective layer, wherein when the thin film transistor is manufactured based on the 4Mask process, the metal layer is laterally etched to cause the metal layer to deviate inwards, the deviation can cause the transverse sections of the metal layer and the semiconductor layer not to correspond to each other, a semiconductor step can be formed due to the deviation, and the manufactured thin film transistor has the problem of electric leakage due to the existence of the semiconductor step; referring to fig. 5A to 5B, fig. 5A to 5B are schematic diagrams illustrating a principle that a semiconductor step is generated when a thin film transistor is manufactured by an exemplary technique, in fig. 5A, 13 is an exemplary photoresist layer, 12 is an exemplary metal layer, and 11 is an exemplary semiconductor layer, and when a channel of the exemplary metal layer 12 and a channel of the exemplary semiconductor layer 11 are obtained by etching, the exemplary photoresist layer 13 is taken as a mask, and etching is performed from top to bottom, and during the etching, the exemplary metal layer 12 generates a deviation relative to the exemplary semiconductor layer 11, so that the deviation is generated, one reason is that when etching is performed from top to bottom, not only etching in a vertical direction but also etching in a horizontal direction or a horizontal direction is performed, so that the exemplary metal layer 12 is laterally etched, and as shown in fig. 5B, the deviation forms a semiconductor step, and the existence of the semiconductor step causes a leakage of the thin film transistor.
Referring to fig. 1, a first embodiment of the present application provides a method for manufacturing a thin film transistor, including:
step S10, forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer and a second metal layer on the substrate in sequence;
a Thin-Film Transistor (TFT) is a core device of a liquid crystal display panel, and is functionally defined as a three-terminal device that implements a switching function, where the three terminals include a source electrode, a drain electrode, and a gate electrode, and a data line of the drain electrode charges and discharges to and from a pixel electrode of the source electrode through the TFT under the control of the gate electrode.
When manufacturing a thin film transistor, first, a substrate is provided, where the substrate is made of a material including, but not limited to, glass, quartz, sapphire, organic polymer, silicon, and other semiconductor materials, and in this embodiment, the substrate is made of glass; forming a first metal layer above the substrate, wherein the physical vapor deposition method or other methods can be adopted for depositing the first metal layer; the material of the first metal layer comprises but is not limited to aluminum, copper, molybdenum, titanium, nickel and alloy or composite layer structure thereof, and the material is selected as the first metal layer to realize the effects of low impedance, high adhesion and simple processing technology during patterning treatment; in addition, the structure of the thin film transistor includes a bottom gate structure, a top gate structure, and a dual gate structure, in this embodiment, the structure of the thin film transistor is a bottom gate structure, that is, the first metal layer is a gate, and the second metal layer is a source and a drain.
After a first metal layer is formed, sequentially forming a first insulating layer, an active layer, an ohmic contact layer and a second metal layer, wherein the first insulating layer is formed above the first metal layer, the active layer is formed above the first insulating layer, the ohmic contact layer is formed above the active layer, the second metal layer is formed above the ohmic contact layer, in addition, patterning can be further performed on the first metal layer after the first metal layer is formed, and the first insulating layer is formed above the patterned first metal layer; after the second metal layer is formed, the second metal layer may be subjected to a patterning process.
Step S20, etching the second metal layer to form a first channel in the second metal layer;
the first channel is formed in the second metal layer, the second metal layer is etched to form a source electrode and a drain electrode, and the first channel is formed between the source electrode and the drain electrode, and the etching process may be a wet etching process.
Step S30, forming a passivation layer above the second metal layer;
the passivation layer is a thin film which is formed on the surface of the second metal layer and used for preventing corrosion, the thickness of the passivation layer can be 50 nm-100 nm, the passivation layer is formed by passivating the surface of the second metal layer, the passivation treatment mode includes but is not limited to chemical liquid oxidation passivation treatment, physical passivation treatment and thermal oxidation degree treatment, the chemical liquid oxidation passivation treatment is adopted in the embodiment, when the passivation layer is formed by chemical liquid oxidation passivation treatment, passivation liquid is determined according to the material of the second metal layer, the material of the second metal layer is aluminum in the embodiment, the passivation liquid is potassium dichromate (K3 Cr4O 7) with the content of 3-50 g/L, the passivation treatment is carried out on the second metal layer through spraying or soaking, the passivation layer is formed on the surface of the second metal layer, the passivation layer can play a role in protecting the second metal layer, and when a second channel is obtained through etching, the second metal layer is prevented from being etched.
Step S40, with the passivation layer as a mask, etching the ohmic contact layer below the first channel to form a second channel below the first channel;
the second channel is a channel formed on the ohmic contact layer, the second channel is located below the first channel, and when the second channel is obtained through etching, in order to avoid corrosion of the second metal layer by etching treatment, the passivation layer is used as a mask body for etching in the embodiment, and due to the protection effect of the passivation layer, when the ohmic contact layer is etched, the second metal layer is not etched in the transverse direction or the horizontal direction, so that no deviation exists between the second channel of the ohmic contact layer and the first channel of the second metal layer, and a semiconductor step (N + tail) between the second metal layer and the ohmic contact layer is avoided, so that the problem of electric leakage caused by the semiconductor step is avoided; dry etching may be used for etching the ohmic contact layer.
In addition, after the second channel is formed, an exposed area of the active layer, which is located below the second channel, may be etched, and the exposed area of the active layer may be etched by dry etching, in order to avoid the ohmic contact layer remaining in the second channel, wherein the exposed area of the active layer has a thickness of 30nm to 120nm after the active layer is etched.
Step S50, forming a second insulating layer over the second metal layer.
After forming the second channel, forming a second insulating layer over the second metal layer, the second insulating layer serving as a protection layer to prepare the thin film transistor(ii) a In addition, after the second insulating layer is formed, patterning may be performed on the second insulating layer, where the patterning includes coating, exposing, developing, etching, and removing a photoresist, a pixel electrode layer is formed over the patterned second insulating layer, a conductive transparent film may be deposited by a physical vapor deposition method to form a pixel electrode, and the patterning may be performed on the pixel electrode layer, where the patterning includes coating, exposing, developing, etching, and removing a photoresist, and a material of the pixel electrode may be tin-doped tin indium oxide (In) 2 O 3 -SnO 2 ITO), the pixel electrode may be made of other materials, and is not limited herein.
In this embodiment, a first metal layer, a first insulating layer, an active layer, an ohmic contact layer, and a second metal layer are sequentially formed on a substrate, the second metal layer is etched to form a first channel in the second metal layer, a passivation layer is formed above the second metal layer, the passivation layer can play a role in protection, the passivation layer is used as a mask to etch the ohmic contact layer located below the first channel, and when the second metal layer is not etched, a second channel is formed below the first channel.
Referring to fig. 2, a second embodiment of the present application provides a method for manufacturing a thin film transistor, based on the first embodiment shown in fig. 1, the method includes, between step S10 and step S30:
step S60, forming a photoresist layer above the second metal layer, and patterning the photoresist layer;
in this embodiment, after the second metal layer is formed, a photoresist layer needs to be formed over the second metal layer, and patterning is performed on the photoresist layer, an ashing photomask process may be used for performing patterning on the photoresist layer, wherein when the patterning is performed on the photoresist layer, a first photoresist region and a second photoresist region may be formed on the photoresist layer, the thickness of the first photoresist region is smaller than that of the second photoresist region, the first photoresist region is located above a first trench to be etched, and the first photoresist region and the second photoresist region are not overlapped.
Step S70, taking the patterned photoresist layer as a mask, and etching the second metal layer to form a first channel on the second metal layer;
and etching the second metal layer which is not protected by the photoresist layer by taking the photoresist layer after the patterning treatment as a mask to form a first channel, wherein it can be understood that when the second metal layer which is not protected by the photoresist layer is etched, the first channel can also be formed by a plurality of etching processes as required: in this embodiment, the patterned photoresist layer is used as a mask, the second metal layer not protected by the photoresist layer is etched by wet etching, the second metal layer is patterned, the patterned photoresist layer is used as a mask, the ohmic contact layer not protected by the photoresist layer is etched by dry etching, the ohmic contact layer is patterned, the patterned photoresist layer is further used as a mask, the active layer not protected by the photoresist layer is etched by dry etching, the active layer is patterned, and on this basis, the photoresist layer is etched by dry etching, so as to remove the first photoresist region and leave the second photoresist region, expose the second metal layer, and the patterned photoresist layer is used as a mask to etch the patterned second metal layer to form a first channel.
And S80, stripping the photoresist layer.
After the first channel is formed, the photoresist layer is stripped, the passivation layer is formed above the second metal layer, the passivation layer is used as a mask to perform etching to obtain the second channel, the problem that a semiconductor step is formed in the process of obtaining the second channel by etching the photoresist layer is avoided, and therefore the electric leakage problem caused by the semiconductor step is avoided.
In this embodiment, the photoresist layer is formed over the second metal layer, the photoresist layer is patterned, the patterned photoresist layer is used as a mask, the second metal layer is etched to form a first channel in the second metal layer, and the photoresist layer is stripped, so that the problem that a semiconductor step exists when the second channel is obtained based on the photoresist layer combined with an etching process can be avoided, and the technical problem that the existence of the semiconductor step further causes electric leakage of the thin film transistor is avoided.
Referring to fig. 3A to 3L, a third embodiment of the present application provides a method for manufacturing a thin film transistor.
In the present embodiment, a substrate 1 is first provided, a first metal layer 2 is formed over the substrate, a first insulating layer 3 is formed over the first metal layer 2, an active layer 4 is formed over the first insulating layer 3, an ohmic contact layer 6 is formed over the active layer 4, a second metal layer 6 is formed over the ohmic contact layer, a photoresist layer 7 is formed over the second metal layer, the photoresist layer 7 is patterned, the photoresist layer includes a first photoresist region and a second photoresist region, the thickness of the first photoresist region is smaller than that of the second photoresist region, the photoresist layer 7 is used as a mask, the second metal layer 6 is patterned by a wet etching process, the photoresist layer is further used as a mask, the ohmic contact layer 5 and the active layer 4 are etched by a dry etching process to pattern the ohmic contact layer 5 and the active layer 4, the photoresist layer 7 is further thinned by a dry etching method, the first photoresist region is removed, the second metal layer 6 is etched to form a first channel, a source and a drain are formed after etching the second metal layer 6, the source and drain regions between the source and the drain are formed, the second metal layer 7 is thinned by a dry etching method, the passivation layer 8, the second metal layer is formed without exposing the ohmic contact layer 6, the second metal layer 4, the second metal layer 9, wherein the channel is not exposed, the second metal layer 6 is etched, the channel region is formed above the passivation layer 4, the passivation layer 9, the channel region is etched, the channel region is formed, the passivation layer 9, the channel region is further, the channel region is not exposed, the ohmic contact layer 9, the channel region is formed, the passivation layer 4, the channel region is etched, the passivation layer 9, the channel region is formed by a passivation layer 9, the channel region is not exposed, the channel region is formed, the channel region is further exposed, a pixel electrode 10 is formed above the reserved exposed area, and in addition, the pixel electrode 10 also covers a partial area above the second insulating layer 9, thereby realizing the preparation of the thin film transistor.
In the present embodiment, the first metal layer 2 is formed on the substrate 1, the first insulating layer 3 is formed on the first metal layer 2, the active layer 4 is formed on the first insulating layer 3, the ohmic contact layer 5 is formed on the active layer 4, the second metal layer 6 is formed on the ohmic contact layer 5, the patterned photoresist layer 7 is formed on the second metal layer 6, the patterned photoresist layer 7 is used as a mask for etching, the patterned second metal layer 6, the patterned ohmic contact layer 5 and the patterned ohmic contact layer 4 are obtained, the second metal layer 6 is etched to form a first channel, the passivation layer 8 is formed on the second metal layer 6, the ohmic contact layer 5 is etched using the passivation layer 8 as a mask, a second channel is formed on the ohmic contact layer 5, an exposed region of the active layer 4 is formed below the second channel, the second insulating layer 9 is formed on the second metal layer 6, the pixel electrode 10 is formed on the second insulating layer 9, the passivation layer 8 is used for protecting the second channel, the second channel is etched, and a step corrosion of the second metal layer 6 is prevented, so that a semiconductor thin film is not corroded between the second metal layer 6.
Referring to fig. 4, fig. 4 is a schematic diagram of an embodiment of a thin film transistor according to the present application.
In the present embodiment, the bottom is the substrate 1, the first metal layer 2 is disposed above the substrate 1, the first insulating layer 3 is disposed above the first metal layer 2, the active layer 4 is disposed above the first insulating layer 3, the ohmic contact layer 5 is disposed above the active layer 4, the second metal layer 6 is disposed above the ohmic contact layer 5, the passivation layer 8 is disposed above the second metal layer 6, in addition, the second insulating layer 9 covers an exposed region of the passivation layer 8, an exposed region of the second metal layer 6, an exposed region of the ohmic contact layer 5, an exposed region of the active layer 4, and an exposed region of the first insulating layer 3, a partial region above the second insulating layer 9 includes the pixel electrode 10, wherein the pixel electrode 10 covers a partial region of the second insulating layer 9 and a partial region of the second metal layer 6; because no deviation exists between the second metal layer 6 and the ohmic contact layer 5, the existence of a semiconductor step is avoided, and the problem of electric leakage of the thin film transistor caused by the semiconductor step is avoided.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on this understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes several instructions for causing a computer device to execute the methods described in the embodiments of the present application.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (9)
1. A preparation method of a thin film transistor is characterized by comprising the following steps:
forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer and a second metal layer on the substrate in sequence;
etching the second metal layer to form a first channel in the second metal layer;
forming a passivation layer over the second metal layer;
etching the ohmic contact layer below the first channel by taking the passivation layer as a mask so as to form a second channel below the first channel, wherein the position and the size of the second channel correspond to those of the first channel, and no relative deviation exists between the second metal layer and the ohmic contact layer at the cross section of the respective channel;
etching the exposed area of the active layer, wherein the thickness of the etched exposed area of the active layer is 30 nm-120 nm, and the exposed area is positioned below the second channel, so that the ohmic contact layer is prevented from remaining in the second channel;
a second insulating layer is formed over the second metal layer.
2. The method of manufacturing a thin film transistor according to claim 1, wherein between the step of sequentially forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer, and a second metal layer over a substrate and the step of forming a passivation layer over the second metal layer, further comprising:
forming a photoresist layer above the second metal layer, and patterning the photoresist layer;
taking the photoresist layer after the patterning treatment as a mask, and etching the second metal layer to form a first channel on the second metal layer;
and stripping the photoresist layer.
3. The method of manufacturing a thin film transistor according to claim 2, wherein between the step of forming a photoresist layer over the second metal layer and patterning the photoresist layer and the step of stripping the photoresist layer, further comprising:
patterning the second metal layer by taking the photoresist layer after patterning as a mask;
patterning the ohmic contact layer by taking the patterned photoresist layer as a mask;
patterning the active layer by taking the photoresist layer after patterning as a mask;
and etching the second metal layer after patterning by taking the photoresist layer after patterning as a mask to form the first channel.
4. The method of claim 3, wherein the photoresist layer comprises a first photoresist region and a second photoresist region, the first photoresist region has a thickness smaller than that of the second photoresist region, the first photoresist region is located above the first trench, the second photoresist region is not overlapped with the first photoresist region, the patterned photoresist layer is used as a mask, and after the step of patterning the active layer, the method further comprises:
and etching the photoresist layer to remove the first photoresist region and reserve the second photoresist region.
5. The method of manufacturing a thin film transistor according to claim 1, wherein the step of sequentially forming a first metal layer, a first insulating layer, an active layer, an ohmic contact layer, and a second metal layer over a substrate comprises:
forming a first metal layer above the substrate, and performing patterning processing on the first metal layer;
forming the first insulating layer over the patterned first metal layer;
forming the active layer over the first insulating layer;
forming the ohmic contact layer over the active layer;
forming the second metal layer over the ohmic contact layer.
6. The method of manufacturing a thin film transistor according to claim 1, further comprising, after the step of forming a second insulating layer over the second metal layer:
patterning the second insulating layer;
forming a pixel electrode layer over the patterned second insulating layer;
and patterning the pixel electrode layer.
7. The method of manufacturing a thin film transistor according to any one of claims 1 to 6, wherein the thickness of the passivation layer is 50nm to 100nm.
8. A thin film transistor, characterized in that it is produced by the method of producing a thin film transistor according to any one of claims 1 to 7.
9. A display panel characterized by comprising the thin film transistor according to claim 8.
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